自学教程：C++ HAS_PCH_SPLIT函数代码示例

static void i915_restore_display(struct drm_device *dev){	struct drm_i915_private *dev_priv = dev->dev_private;	u32 mask = 0xffffffff;	/* Display arbitration */	if (INTEL_INFO(dev)->gen <= 4)		I915_WRITE(DSPARB, dev_priv->regfile.saveDSPARB);	if (!drm_core_check_feature(dev, DRIVER_MODESET))		i915_restore_display_reg(dev);	if (drm_core_check_feature(dev, DRIVER_MODESET))		mask = ~LVDS_PORT_EN;	if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))		I915_WRITE(PCH_LVDS, dev_priv->regfile.saveLVDS & mask);	else if (INTEL_INFO(dev)->gen <= 4 && IS_MOBILE(dev) && !IS_I830(dev))		I915_WRITE(LVDS, dev_priv->regfile.saveLVDS & mask);	if (!IS_I830(dev) && !IS_845G(dev) && !HAS_PCH_SPLIT(dev))		I915_WRITE(PFIT_CONTROL, dev_priv->regfile.savePFIT_CONTROL);	if (HAS_PCH_SPLIT(dev)) {		I915_WRITE(PCH_PP_ON_DELAYS, dev_priv->regfile.savePP_ON_DELAYS);		I915_WRITE(PCH_PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS);		I915_WRITE(PCH_PP_DIVISOR, dev_priv->regfile.savePP_DIVISOR);		I915_WRITE(PCH_PP_CONTROL, dev_priv->regfile.savePP_CONTROL);		I915_WRITE(RSTDBYCTL,			   dev_priv->regfile.saveMCHBAR_RENDER_STANDBY);	} else if (IS_VALLEYVIEW(dev)) {		I915_WRITE(VLV_BLC_HIST_CTL(PIPE_A),			   dev_priv->regfile.saveBLC_HIST_CTL);		I915_WRITE(VLV_BLC_HIST_CTL(PIPE_B),			   dev_priv->regfile.saveBLC_HIST_CTL);	} else {		I915_WRITE(PFIT_PGM_RATIOS, dev_priv->regfile.savePFIT_PGM_RATIOS);		I915_WRITE(BLC_HIST_CTL, dev_priv->regfile.saveBLC_HIST_CTL);		I915_WRITE(PP_ON_DELAYS, dev_priv->regfile.savePP_ON_DELAYS);		I915_WRITE(PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS);		I915_WRITE(PP_DIVISOR, dev_priv->regfile.savePP_DIVISOR);		I915_WRITE(PP_CONTROL, dev_priv->regfile.savePP_CONTROL);	}	/* only restore FBC info on the platform that supports FBC*/	intel_disable_fbc(dev);	/* restore FBC interval */	if (HAS_FBC(dev) && INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev))		I915_WRITE(FBC_CONTROL, dev_priv->regfile.saveFBC_CONTROL);	if (!drm_core_check_feature(dev, DRIVER_MODESET))		i915_restore_vga(dev);	else		i915_redisable_vga(dev);}

bool intel_hdmi_compute_config(struct intel_encoder *encoder,			       struct intel_crtc_config *pipe_config){	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);	struct drm_device *dev = encoder->base.dev;	struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;	int clock_12bpc = pipe_config->adjusted_mode.crtc_clock * 3 / 2;	int portclock_limit = hdmi_portclock_limit(intel_hdmi);	int desired_bpp;	if (intel_hdmi->color_range_auto) {		/* See CEA-861-E - 5.1 Default Encoding Parameters */		if (intel_hdmi->has_hdmi_sink &&		    drm_match_cea_mode(adjusted_mode) > 1)			intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235;		else			intel_hdmi->color_range = 0;	}	if (intel_hdmi->color_range)		pipe_config->limited_color_range = true;	if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev))		pipe_config->has_pch_encoder = true;	/*	 * HDMI is either 12 or 8, so if the display lets 10bpc sneak	 * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi	 * outputs. We also need to check that the higher clock still fits	 * within limits.	 */	if (pipe_config->pipe_bpp > 8*3 && intel_hdmi->has_hdmi_sink &&	    clock_12bpc <= portclock_limit && HAS_PCH_SPLIT(dev)) {		DRM_DEBUG_KMS("picking bpc to 12 for HDMI output/n");		desired_bpp = 12*3;		/* Need to adjust the port link by 1.5x for 12bpc. */		pipe_config->port_clock = clock_12bpc;	} else {		DRM_DEBUG_KMS("picking bpc to 8 for HDMI output/n");		desired_bpp = 8*3;	}	if (!pipe_config->bw_constrained) {		DRM_DEBUG_KMS("forcing pipe bpc to %i for HDMI/n", desired_bpp);		pipe_config->pipe_bpp = desired_bpp;	}	if (adjusted_mode->crtc_clock > portclock_limit) {		DRM_DEBUG_KMS("too high HDMI clock, rejecting mode/n");		return false;	}	return true;}

static void intel_disable_hdmi(struct intel_encoder *encoder){	struct drm_device *dev = encoder->base.dev;	struct drm_i915_private *dev_priv = dev->dev_private;	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);	u32 temp;	u32 enable_bits = SDVO_ENABLE | SDVO_AUDIO_ENABLE;	temp = I915_READ(intel_hdmi->sdvox_reg);	/* HW workaround for IBX, we need to move the port to transcoder A	 * before disabling it. */	if (HAS_PCH_IBX(dev)) {		struct drm_crtc *crtc = encoder->base.crtc;		int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1;		if (temp & SDVO_PIPE_B_SELECT) {			temp &= ~SDVO_PIPE_B_SELECT;			I915_WRITE(intel_hdmi->sdvox_reg, temp);			POSTING_READ(intel_hdmi->sdvox_reg);			/* Again we need to write this twice. */			I915_WRITE(intel_hdmi->sdvox_reg, temp);			POSTING_READ(intel_hdmi->sdvox_reg);			/* Transcoder selection bits only update			 * effectively on vblank. */			if (crtc)				intel_wait_for_vblank(dev, pipe);			else				DRM_MSLEEP(50);		}	}	/* HW workaround, need to toggle enable bit off and on for 12bpc, but	 * we do this anyway which shows more stable in testing.	 */	if (HAS_PCH_SPLIT(dev)) {		I915_WRITE(intel_hdmi->sdvox_reg, temp & ~SDVO_ENABLE);		POSTING_READ(intel_hdmi->sdvox_reg);	}	temp &= ~enable_bits;	I915_WRITE(intel_hdmi->sdvox_reg, temp);	POSTING_READ(intel_hdmi->sdvox_reg);	/* HW workaround, need to write this twice for issue that may result	 * in first write getting masked.	 */	if (HAS_PCH_SPLIT(dev)) {		I915_WRITE(intel_hdmi->sdvox_reg, temp);		POSTING_READ(intel_hdmi->sdvox_reg);	}}

static void i915_save_display(struct drm_device *dev){	struct drm_i915_private *dev_priv = dev->dev_private;	/* Display arbitration control */	if (INTEL_INFO(dev)->gen <= 4)		dev_priv->regfile.saveDSPARB = I915_READ(DSPARB);	/* This is only meaningful in non-KMS mode */	/* Don't regfile.save them in KMS mode */	if (!drm_core_check_feature(dev, DRIVER_MODESET))		i915_save_display_reg(dev);	/* LVDS state */	if (HAS_PCH_SPLIT(dev)) {		dev_priv->regfile.savePP_CONTROL = I915_READ(PCH_PP_CONTROL);		if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))			dev_priv->regfile.saveLVDS = I915_READ(PCH_LVDS);	} else if (IS_VALLEYVIEW(dev)) {		dev_priv->regfile.savePP_CONTROL = I915_READ(PP_CONTROL);		dev_priv->regfile.savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS);		dev_priv->regfile.saveBLC_HIST_CTL =			I915_READ(VLV_BLC_HIST_CTL(PIPE_A));		dev_priv->regfile.saveBLC_HIST_CTL_B =			I915_READ(VLV_BLC_HIST_CTL(PIPE_B));	} else {		dev_priv->regfile.savePP_CONTROL = I915_READ(PP_CONTROL);		dev_priv->regfile.savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS);		dev_priv->regfile.saveBLC_HIST_CTL = I915_READ(BLC_HIST_CTL);		if (IS_MOBILE(dev) && !IS_I830(dev))			dev_priv->regfile.saveLVDS = I915_READ(LVDS);	}	if (!IS_I830(dev) && !IS_845G(dev) && !HAS_PCH_SPLIT(dev))		dev_priv->regfile.savePFIT_CONTROL = I915_READ(PFIT_CONTROL);	if (HAS_PCH_SPLIT(dev)) {		dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PCH_PP_ON_DELAYS);		dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PCH_PP_OFF_DELAYS);		dev_priv->regfile.savePP_DIVISOR = I915_READ(PCH_PP_DIVISOR);	} else {		dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PP_ON_DELAYS);		dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PP_OFF_DELAYS);		dev_priv->regfile.savePP_DIVISOR = I915_READ(PP_DIVISOR);	}	/* save FBC interval */	if (HAS_FBC(dev) && INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev))		dev_priv->regfile.saveFBC_CONTROL = I915_READ(FBC_CONTROL);	if (!drm_core_check_feature(dev, DRIVER_MODESET))		i915_save_vga(dev);}

static void intel_enable_hdmi(struct intel_encoder *encoder){	struct drm_device *dev = encoder->base.dev;	struct drm_i915_private *dev_priv = dev->dev_private;	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);	u32 temp;	u32 enable_bits = SDVO_ENABLE;	if (intel_hdmi->has_audio)		enable_bits |= SDVO_AUDIO_ENABLE;	temp = I915_READ(intel_hdmi->hdmi_reg);	/* HW workaround for IBX, we need to move the port to transcoder A	 * before disabling it, so restore the transcoder select bit here. */	if (HAS_PCH_IBX(dev))		enable_bits |= SDVO_PIPE_SEL(intel_crtc->pipe);	/* HW workaround, need to toggle enable bit off and on for 12bpc, but	 * we do this anyway which shows more stable in testing.	 */	if (HAS_PCH_SPLIT(dev)) {		I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);		POSTING_READ(intel_hdmi->hdmi_reg);	}	temp |= enable_bits;	I915_WRITE(intel_hdmi->hdmi_reg, temp);	POSTING_READ(intel_hdmi->hdmi_reg);	/* HW workaround, need to write this twice for issue that may result	 * in first write getting masked.	 */	if (HAS_PCH_SPLIT(dev)) {		I915_WRITE(intel_hdmi->hdmi_reg, temp);		POSTING_READ(intel_hdmi->hdmi_reg);	}	if (IS_VALLEYVIEW(dev)) {		struct intel_digital_port *dport =			enc_to_dig_port(&encoder->base);		int channel = vlv_dport_to_channel(dport);		vlv_wait_port_ready(dev_priv, channel);	}}

int i915_restore_state(struct drm_device *dev){	struct drm_i915_private *dev_priv = dev->dev_private;	int i;	pci_write_config(dev->dev, LBB, dev_priv->saveLBB, 1);	/* Hardware status page */	I915_WRITE(HWS_PGA, dev_priv->saveHWS);	i915_restore_display(dev);	/* Interrupt state */	if (HAS_PCH_SPLIT(dev)) {		I915_WRITE(DEIER, dev_priv->saveDEIER);		I915_WRITE(DEIMR, dev_priv->saveDEIMR);		I915_WRITE(GTIER, dev_priv->saveGTIER);		I915_WRITE(GTIMR, dev_priv->saveGTIMR);		I915_WRITE(_FDI_RXA_IMR, dev_priv->saveFDI_RXA_IMR);		I915_WRITE(_FDI_RXB_IMR, dev_priv->saveFDI_RXB_IMR);		I915_WRITE(PCH_PORT_HOTPLUG, dev_priv->savePCH_PORT_HOTPLUG);	} else {		I915_WRITE(IER, dev_priv->saveIER);		I915_WRITE(IMR, dev_priv->saveIMR);	}	DRM_UNLOCK(dev);	if (drm_core_check_feature(dev, DRIVER_MODESET))		intel_init_clock_gating(dev);	if (IS_IRONLAKE_M(dev)) {		ironlake_enable_drps(dev);		intel_init_emon(dev);	}	if (INTEL_INFO(dev)->gen >= 6) {		gen6_enable_rps(dev_priv);		gen6_update_ring_freq(dev_priv);	}	DRM_LOCK(dev);	/* Cache mode state */	I915_WRITE(CACHE_MODE_0, dev_priv->saveCACHE_MODE_0 | 0xffff0000);	/* Memory arbitration state */	I915_WRITE(MI_ARB_STATE, dev_priv->saveMI_ARB_STATE | 0xffff0000);	for (i = 0; i < 16; i++) {		I915_WRITE(SWF00 + (i << 2), dev_priv->saveSWF0[i]);		I915_WRITE(SWF10 + (i << 2), dev_priv->saveSWF1[i]);	}	for (i = 0; i < 3; i++)		I915_WRITE(SWF30 + (i << 2), dev_priv->saveSWF2[i]);	intel_iic_reset(dev);	return 0;}

static void i915_save_display(struct drm_device *dev){	struct drm_i915_private *dev_priv = dev->dev_private;	/* Display arbitration control */	if (INTEL_INFO(dev)->gen <= 4)		dev_priv->regfile.saveDSPARB = I915_READ(DSPARB);	/* LVDS state */	if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))		dev_priv->regfile.saveLVDS = I915_READ(PCH_LVDS);	else if (INTEL_INFO(dev)->gen <= 4 && IS_MOBILE(dev) && !IS_I830(dev))		dev_priv->regfile.saveLVDS = I915_READ(LVDS);	/* Panel power sequencer */	if (HAS_PCH_SPLIT(dev)) {		dev_priv->regfile.savePP_CONTROL = I915_READ(PCH_PP_CONTROL);		dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PCH_PP_ON_DELAYS);		dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PCH_PP_OFF_DELAYS);		dev_priv->regfile.savePP_DIVISOR = I915_READ(PCH_PP_DIVISOR);	} else if (!IS_VALLEYVIEW(dev)) {		dev_priv->regfile.savePP_CONTROL = I915_READ(PP_CONTROL);		dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PP_ON_DELAYS);		dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PP_OFF_DELAYS);		dev_priv->regfile.savePP_DIVISOR = I915_READ(PP_DIVISOR);	}	/* save FBC interval */	if (HAS_FBC(dev) && INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev))		dev_priv->regfile.saveFBC_CONTROL = I915_READ(FBC_CONTROL);}

static inti915_capabilities(struct drm_device *dev, struct sbuf *m, void *data){	const struct intel_device_info *info = INTEL_INFO(dev);	sbuf_printf(m, "gen: %d/n", info->gen);	if (HAS_PCH_SPLIT(dev))		sbuf_printf(m, "pch: %d/n", INTEL_PCH_TYPE(dev));#define B(x) sbuf_printf(m, #x ": %s/n", yesno(info->x))	B(is_mobile);	B(is_i85x);	B(is_i915g);	B(is_i945gm);	B(is_g33);	B(need_gfx_hws);	B(is_g4x);	B(is_pineview);	B(has_fbc);	B(has_pipe_cxsr);	B(has_hotplug);	B(cursor_needs_physical);	B(has_overlay);	B(overlay_needs_physical);	B(supports_tv);	B(has_bsd_ring);	B(has_blt_ring);	B(has_llc);#undef B	return (0);}

static voidinit_vbt_defaults(struct drm_i915_private *dev_priv){	extern struct drm_device *i915;	struct drm_device *dev = i915;	dev_priv->crt_ddc_pin = GMBUS_PORT_VGADDC;	/* LFP panel data */	dev_priv->lvds_dither = 1;	dev_priv->lvds_vbt = 0;	/* SDVO panel data */	dev_priv->sdvo_lvds_vbt_mode = NULL;	/* general features */	dev_priv->int_tv_support = 1;	dev_priv->int_crt_support = 1;	/* Default to using SSC */	dev_priv->lvds_use_ssc = 1;	/* Core/SandyBridge/IvyBridge use 120MHz reference clock for LVDS */	if (HAS_PCH_SPLIT(dev))		dev_priv->lvds_ssc_freq = intel_bios_ssc_frequency(dev, 0);	else		dev_priv->lvds_ssc_freq = intel_bios_ssc_frequency(dev, 1);	fprintf(stderr, "Set default to SSC at %dMHz/n", dev_priv->lvds_ssc_freq);	/* eDP data */	dev_priv->edp.bpp = 18;}

/* XXX: query mode clock or hardware clock and program max PWM appropriately * when it's 0. */static u32 i915_read_blc_pwm_ctl(struct drm_device *dev){	struct drm_i915_private *dev_priv = dev->dev_private;	u32 val;	WARN_ON_SMP(!spin_is_locked(&dev_priv->backlight.lock));	/* Restore the CTL value if it lost, e.g. GPU reset */	if (HAS_PCH_SPLIT(dev_priv->dev)) {		val = I915_READ(BLC_PWM_PCH_CTL2);		if (dev_priv->regfile.saveBLC_PWM_CTL2 == 0) {			dev_priv->regfile.saveBLC_PWM_CTL2 = val;		} else if (val == 0) {			val = dev_priv->regfile.saveBLC_PWM_CTL2;			I915_WRITE(BLC_PWM_PCH_CTL2, val);		}	} else {		val = I915_READ(BLC_PWM_CTL);		if (dev_priv->regfile.saveBLC_PWM_CTL == 0) {			dev_priv->regfile.saveBLC_PWM_CTL = val;			if (INTEL_INFO(dev)->gen >= 4)				dev_priv->regfile.saveBLC_PWM_CTL2 =					I915_READ(BLC_PWM_CTL2);		} else if (val == 0) {			val = dev_priv->regfile.saveBLC_PWM_CTL;			I915_WRITE(BLC_PWM_CTL, val);			if (INTEL_INFO(dev)->gen >= 4)				I915_WRITE(BLC_PWM_CTL2,					   dev_priv->regfile.saveBLC_PWM_CTL2);		}	}	return val;}

/** * intel_enable_pipe - enable a pipe, asserting requirements * @dev_priv: i915 private structure * @pipe: pipe to enable * @pch_port: on ILK+, is this pipe driving a PCH port or not * * Enable @pipe, making sure that various hardware specific requirements * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. * * @pipe should be %PIPE_A or %PIPE_B. * * Will wait until the pipe is actually running (i.e. first vblank) before * returning. */static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,			      bool pch_port){	int reg;	u32 val;	/*	 * A pipe without a PLL won't actually be able to drive bits from	 * a plane.  On ILK+ the pipe PLLs are integrated, so we don't	 * need the check.	 */	if (!HAS_PCH_SPLIT(dev_priv->dev))		assert_pll_enabled(dev_priv, pipe);	else {		if (pch_port) {			/* if driving the PCH, we need FDI enabled */			assert_fdi_rx_pll_enabled(dev_priv, pipe);			assert_fdi_tx_pll_enabled(dev_priv, pipe);		}		/* FIXME: assert CPU port conditions for SNB+ */	}	reg = PIPECONF(pipe);	val = I915_READ(reg);	if (val & PIPECONF_ENABLE)		return;	I915_WRITE(reg, val | PIPECONF_ENABLE);	intel_wait_for_vblank(dev_priv->dev, pipe);}

static void intel_hdmi_get_config(struct intel_encoder *encoder,				  struct intel_crtc_config *pipe_config){	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;	u32 tmp, flags = 0;	int dotclock;	tmp = I915_READ(intel_hdmi->hdmi_reg);	if (tmp & SDVO_HSYNC_ACTIVE_HIGH)		flags |= DRM_MODE_FLAG_PHSYNC;	else		flags |= DRM_MODE_FLAG_NHSYNC;	if (tmp & SDVO_VSYNC_ACTIVE_HIGH)		flags |= DRM_MODE_FLAG_PVSYNC;	else		flags |= DRM_MODE_FLAG_NVSYNC;	pipe_config->adjusted_mode.flags |= flags;	if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)		dotclock = pipe_config->port_clock * 2 / 3;	else		dotclock = pipe_config->port_clock;	if (HAS_PCH_SPLIT(dev_priv->dev))		ironlake_check_encoder_dotclock(pipe_config, dotclock);	pipe_config->adjusted_mode.crtc_clock = dotclock;}

static void assert_panel_unlocked(struct drm_i915_private *dev_priv,				  enum pipe pipe){	int pp_reg, lvds_reg;	u32 val;	enum pipe panel_pipe = PIPE_A;	bool locked = locked;	if (HAS_PCH_SPLIT(dev_priv->dev)) {		pp_reg = PCH_PP_CONTROL;		lvds_reg = PCH_LVDS;	} else {		pp_reg = PP_CONTROL;		lvds_reg = LVDS;	}	val = I915_READ(pp_reg);	if (!(val & PANEL_POWER_ON) ||	    ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))		locked = false;	if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)		panel_pipe = PIPE_B;	if (panel_pipe == pipe && locked) fprintf(stderr,	     "panel assertion failure, pipe %c regs locked/n",	     pipe_name(pipe));}

static u32 i915_read_blc_pwm_ctl(struct drm_i915_private *dev_priv){	u32 val;	/* Restore the CTL value if it lost, e.g. GPU reset */	if (HAS_PCH_SPLIT(dev_priv->dev)) {		val = I915_READ(BLC_PWM_PCH_CTL2);		if (dev_priv->saveBLC_PWM_CTL2 == 0) {			dev_priv->saveBLC_PWM_CTL2 = val;		} else if (val == 0) {			I915_WRITE(BLC_PWM_PCH_CTL2,				   dev_priv->saveBLC_PWM_CTL2);			val = dev_priv->saveBLC_PWM_CTL2;		}	} else {		val = I915_READ(BLC_PWM_CTL);		if (dev_priv->saveBLC_PWM_CTL == 0) {			dev_priv->saveBLC_PWM_CTL = val;			dev_priv->saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2);		} else if (val == 0) {			I915_WRITE(BLC_PWM_CTL,				   dev_priv->saveBLC_PWM_CTL);			I915_WRITE(BLC_PWM_CTL2,				   dev_priv->saveBLC_PWM_CTL2);			val = dev_priv->saveBLC_PWM_CTL;		}	}	return val;}

static int i915_setup_compression(struct drm_device *dev, int size){	struct drm_i915_private *dev_priv = dev->dev_private;	struct drm_mm_node *compressed_fb, *uninitialized_var(compressed_llb);	int ret;	compressed_fb = kzalloc(sizeof(*compressed_fb), GFP_KERNEL);	if (!compressed_fb)		goto err_llb;	/* Try to over-allocate to reduce reallocations and fragmentation */	ret = drm_mm_insert_node(&dev_priv->mm.stolen, compressed_fb,				 size <<= 1, 4096, DRM_MM_SEARCH_DEFAULT);	if (ret)		ret = drm_mm_insert_node(&dev_priv->mm.stolen, compressed_fb,					 size >>= 1, 4096,					 DRM_MM_SEARCH_DEFAULT);	if (ret)		goto err_llb;	if (HAS_PCH_SPLIT(dev))		I915_WRITE(ILK_DPFC_CB_BASE, compressed_fb->start);	else if (IS_GM45(dev)) {		I915_WRITE(DPFC_CB_BASE, compressed_fb->start);	} else {		compressed_llb = kzalloc(sizeof(*compressed_llb), GFP_KERNEL);		if (!compressed_llb)			goto err_fb;		ret = drm_mm_insert_node(&dev_priv->mm.stolen, compressed_llb,					 4096, 4096, DRM_MM_SEARCH_DEFAULT);		if (ret)			goto err_fb;		dev_priv->fbc.compressed_llb = compressed_llb;		I915_WRITE(FBC_CFB_BASE,			   dev_priv->mm.stolen_base + compressed_fb->start);		I915_WRITE(FBC_LL_BASE,			   dev_priv->mm.stolen_base + compressed_llb->start);	}	dev_priv->fbc.compressed_fb = compressed_fb;	dev_priv->fbc.size = size;	DRM_DEBUG_KMS("reserved %d bytes of contiguous stolen space for FBC/n",		      size);	return 0;err_fb:	kfree(compressed_llb);	drm_mm_remove_node(compressed_fb);err_llb:	kfree(compressed_fb);	pr_info_once("drm: not enough stolen space for compressed buffer (need %d more bytes), disabling. Hint: you may be able to increase stolen memory size in the BIOS to avoid this./n", size);	return -ENOSPC;}

static void intel_enable_hdmi(struct intel_encoder *encoder){	struct drm_device *dev = encoder->base.dev;	struct drm_i915_private *dev_priv = dev->dev_private;	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);	u32 temp;	u32 enable_bits = SDVO_ENABLE;	if (intel_hdmi->has_audio)		enable_bits |= SDVO_AUDIO_ENABLE;	temp = I915_READ(intel_hdmi->sdvox_reg);	/* HW workaround for IBX, we need to move the port to transcoder A	 * before disabling it. */	if (HAS_PCH_IBX(dev)) {		struct drm_crtc *crtc = encoder->base.crtc;		int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1;		/* Restore the transcoder select bit. */		if (pipe == PIPE_B)			enable_bits |= SDVO_PIPE_B_SELECT;	}	/* HW workaround, need to toggle enable bit off and on for 12bpc, but	 * we do this anyway which shows more stable in testing.	 */	if (HAS_PCH_SPLIT(dev)) {		I915_WRITE(intel_hdmi->sdvox_reg, temp & ~SDVO_ENABLE);		POSTING_READ(intel_hdmi->sdvox_reg);	}	temp |= enable_bits;	I915_WRITE(intel_hdmi->sdvox_reg, temp);	POSTING_READ(intel_hdmi->sdvox_reg);	/* HW workaround, need to write this twice for issue that may result	 * in first write getting masked.	 */	if (HAS_PCH_SPLIT(dev)) {		I915_WRITE(intel_hdmi->sdvox_reg, temp);		POSTING_READ(intel_hdmi->sdvox_reg);	}}

voidintel_i2c_reset(struct drm_device *dev){	struct drm_i915_private *dev_priv = dev->dev_private;	if (HAS_PCH_SPLIT(dev))		I915_WRITE(PCH_GMBUS0, 0);	else		I915_WRITE(GMBUS0, 0);}

static intintel_gmbus_transfer(device_t idev, struct iic_msg *msgs, uint32_t nmsgs){	struct intel_iic_softc *sc;	struct drm_i915_private *dev_priv;	u8 *buf;	int error, i, reg_offset, unit;	u32 val, loop;	u16 len;	sc = device_get_softc(idev);	dev_priv = sc->drm_dev->dev_private;	unit = device_get_unit(idev);	sx_xlock(&dev_priv->gmbus_sx);	if (sc->force_bit_dev) {		error = intel_iic_quirk_xfer(dev_priv->bbbus[unit], msgs, nmsgs);		goto out;	}	reg_offset = HAS_PCH_SPLIT(dev_priv->dev) ? PCH_GMBUS0 - GMBUS0 : 0;	I915_WRITE(GMBUS0 + reg_offset, sc->reg0);	for (i = 0; i < nmsgs; i++) {		len = msgs[i].len;		buf = msgs[i].buf;		if ((msgs[i].flags & IIC_M_RD) != 0) {			I915_WRITE(GMBUS1 + reg_offset, GMBUS_CYCLE_WAIT |			    (i + 1 == nmsgs ? GMBUS_CYCLE_STOP : 0) |			    (len << GMBUS_BYTE_COUNT_SHIFT) |			    (msgs[i].slave << GMBUS_SLAVE_ADDR_SHIFT) |			    GMBUS_SLAVE_READ | GMBUS_SW_RDY);			POSTING_READ(GMBUS2 + reg_offset);			do {				loop = 0;				if (_intel_wait_for(sc->drm_dev,				    (I915_READ(GMBUS2 + reg_offset) &					(GMBUS_SATOER | GMBUS_HW_RDY)) != 0,				    50, 1, "915gbr"))					goto timeout;				if ((I915_READ(GMBUS2 + reg_offset) &				    GMBUS_SATOER) != 0)					goto clear_err;				val = I915_READ(GMBUS3 + reg_offset);				do {					*buf++ = val & 0xff;					val >>= 8;				} while (--len != 0 && ++loop < 4);			} while (len != 0);		} else {

int i915_restore_state(struct drm_device *dev){	struct drm_i915_private *dev_priv = dev->dev_private;	int i;	mutex_lock(&dev->struct_mutex);	i915_gem_restore_fences(dev);	if (IS_GEN4(dev))		pci_write_config_word(dev->pdev, GCDGMBUS,				      dev_priv->regfile.saveGCDGMBUS);	i915_restore_display(dev);	if (!drm_core_check_feature(dev, DRIVER_MODESET)) {		/* Interrupt state */		if (HAS_PCH_SPLIT(dev)) {			I915_WRITE(DEIER, dev_priv->regfile.saveDEIER);			I915_WRITE(DEIMR, dev_priv->regfile.saveDEIMR);			I915_WRITE(GTIER, dev_priv->regfile.saveGTIER);			I915_WRITE(GTIMR, dev_priv->regfile.saveGTIMR);			I915_WRITE(_FDI_RXA_IMR, dev_priv->regfile.saveFDI_RXA_IMR);			I915_WRITE(_FDI_RXB_IMR, dev_priv->regfile.saveFDI_RXB_IMR);			I915_WRITE(PCH_PORT_HOTPLUG, dev_priv->regfile.savePCH_PORT_HOTPLUG);			I915_WRITE(RSTDBYCTL,				   dev_priv->regfile.saveMCHBAR_RENDER_STANDBY);		} else {			I915_WRITE(IER, dev_priv->regfile.saveIER);			I915_WRITE(IMR, dev_priv->regfile.saveIMR);		}	}	/* Cache mode state */	if (INTEL_INFO(dev)->gen < 7)		I915_WRITE(CACHE_MODE_0, dev_priv->regfile.saveCACHE_MODE_0 |			   0xffff0000);	/* Memory arbitration state */	I915_WRITE(MI_ARB_STATE, dev_priv->regfile.saveMI_ARB_STATE | 0xffff0000);	for (i = 0; i < 16; i++) {		I915_WRITE(SWF00 + (i << 2), dev_priv->regfile.saveSWF0[i]);		I915_WRITE(SWF10 + (i << 2), dev_priv->regfile.saveSWF1[i]);	}	for (i = 0; i < 3; i++)		I915_WRITE(SWF30 + (i << 2), dev_priv->regfile.saveSWF2[i]);	mutex_unlock(&dev->struct_mutex);	intel_i2c_reset(dev);	return 0;}

int i915_save_state(struct drm_device *dev){	struct drm_i915_private *dev_priv = dev->dev_private;	int i;	pci_read_config_byte(dev->pdev, LBB, &dev_priv->saveLBB);	mutex_lock(&dev->struct_mutex);		dev_priv->saveHWS = I915_READ(HWS_PGA);	i915_save_display(dev);		if (HAS_PCH_SPLIT(dev)) {		dev_priv->saveDEIER = I915_READ(DEIER);		dev_priv->saveDEIMR = I915_READ(DEIMR);		dev_priv->saveGTIER = I915_READ(GTIER);		dev_priv->saveGTIMR = I915_READ(GTIMR);		dev_priv->saveFDI_RXA_IMR = I915_READ(_FDI_RXA_IMR);		dev_priv->saveFDI_RXB_IMR = I915_READ(_FDI_RXB_IMR);		dev_priv->saveMCHBAR_RENDER_STANDBY =			I915_READ(RSTDBYCTL);		dev_priv->savePCH_PORT_HOTPLUG = I915_READ(PCH_PORT_HOTPLUG);	} else {		dev_priv->saveIER = I915_READ(IER);		dev_priv->saveIMR = I915_READ(IMR);	}	if (IS_IRONLAKE_M(dev))		ironlake_disable_drps(dev);	if (INTEL_INFO(dev)->gen >= 6)		gen6_disable_rps(dev);		dev_priv->saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);		dev_priv->saveMI_ARB_STATE = I915_READ(MI_ARB_STATE);		for (i = 0; i < 16; i++) {		dev_priv->saveSWF0[i] = I915_READ(SWF00 + (i << 2));		dev_priv->saveSWF1[i] = I915_READ(SWF10 + (i << 2));	}	for (i = 0; i < 3; i++)		dev_priv->saveSWF2[i] = I915_READ(SWF30 + (i << 2));	mutex_unlock(&dev->struct_mutex);	return 0;}

static bool i915_pipe_enabled(struct drm_device *dev, enum pipe pipe){	struct drm_i915_private *dev_priv = dev->dev_private;	u32	dpll_reg;	if (HAS_PCH_SPLIT(dev))		dpll_reg = (pipe == PIPE_A) ? _PCH_DPLL_A : _PCH_DPLL_B;	else		dpll_reg = (pipe == PIPE_A) ? _DPLL_A : _DPLL_B;	return (I915_READ(dpll_reg) & DPLL_VCO_ENABLE);}

int i915_restore_state(struct drm_device *dev){	struct drm_i915_private *dev_priv = dev->dev_private;	int i;	pci_write_config_byte(dev->pdev, LBB, dev_priv->saveLBB);	/* Hardware status page */	I915_WRITE(HWS_PGA, dev_priv->saveHWS);	i915_restore_display(dev);	/* Interrupt state */	if (HAS_PCH_SPLIT(dev)) {		I915_WRITE(DEIER, dev_priv->saveDEIER);		I915_WRITE(DEIMR, dev_priv->saveDEIMR);		I915_WRITE(GTIER, dev_priv->saveGTIER);		I915_WRITE(GTIMR, dev_priv->saveGTIMR);		I915_WRITE(_FDI_RXA_IMR, dev_priv->saveFDI_RXA_IMR);		I915_WRITE(_FDI_RXB_IMR, dev_priv->saveFDI_RXB_IMR);	} else {		I915_WRITE(IER, dev_priv->saveIER);		I915_WRITE(IMR, dev_priv->saveIMR);	}	intel_init_clock_gating(dev);	if (IS_IRONLAKE_M(dev)) {		ironlake_enable_drps(dev);		intel_init_emon(dev);	}	if (IS_GEN6(dev))		gen6_enable_rps(dev_priv);	/* Cache mode state */	I915_WRITE (CACHE_MODE_0, dev_priv->saveCACHE_MODE_0 | 0xffff0000);	/* Memory arbitration state */	I915_WRITE (MI_ARB_STATE, dev_priv->saveMI_ARB_STATE | 0xffff0000);	for (i = 0; i < 16; i++) {		I915_WRITE(SWF00 + (i << 2), dev_priv->saveSWF0[i]);		I915_WRITE(SWF10 + (i << 2), dev_priv->saveSWF1[i]);	}	for (i = 0; i < 3; i++)		I915_WRITE(SWF30 + (i << 2), dev_priv->saveSWF2[i]);	intel_i2c_reset(dev);	return 0;}

/* Ensure that vital registers have been initialised, even if the BIOS * is absent or just failing to do its job. */void intel_setup_bios(struct drm_device *dev){	struct drm_i915_private *dev_priv = dev->dev_private;	 /* Set the Panel Power On/Off timings if uninitialized. */	if (!HAS_PCH_SPLIT(dev) &&	    I915_READ(PP_ON_DELAYS) == 0 && I915_READ(PP_OFF_DELAYS) == 0) {		/* Set T2 to 40ms and T5 to 200ms */		I915_WRITE(PP_ON_DELAYS, 0x019007d0);		/* Set T3 to 35ms and Tx to 200ms */		I915_WRITE(PP_OFF_DELAYS, 0x015e07d0);	}}

int i915_save_state(struct drm_device *dev){	struct drm_i915_private *dev_priv = dev->dev_private;	int i;	mutex_lock(&dev->struct_mutex);	i915_save_display(dev);	if (!drm_core_check_feature(dev, DRIVER_MODESET)) {		/* Interrupt state */		if (HAS_PCH_SPLIT(dev)) {			dev_priv->regfile.saveDEIER = I915_READ(DEIER);			dev_priv->regfile.saveDEIMR = I915_READ(DEIMR);			dev_priv->regfile.saveGTIER = I915_READ(GTIER);			dev_priv->regfile.saveGTIMR = I915_READ(GTIMR);			dev_priv->regfile.saveFDI_RXA_IMR = I915_READ(_FDI_RXA_IMR);			dev_priv->regfile.saveFDI_RXB_IMR = I915_READ(_FDI_RXB_IMR);			dev_priv->regfile.saveMCHBAR_RENDER_STANDBY =				I915_READ(RSTDBYCTL);			dev_priv->regfile.savePCH_PORT_HOTPLUG = I915_READ(PCH_PORT_HOTPLUG);		} else {			dev_priv->regfile.saveIER = I915_READ(IER);			dev_priv->regfile.saveIMR = I915_READ(IMR);		}	}	if (IS_GEN4(dev))		pci_read_config_word(dev->pdev, GCDGMBUS,				     &dev_priv->regfile.saveGCDGMBUS);	/* Cache mode state */	if (INTEL_INFO(dev)->gen < 7)		dev_priv->regfile.saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);	/* Memory Arbitration state */	dev_priv->regfile.saveMI_ARB_STATE = I915_READ(MI_ARB_STATE);	/* Scratch space */	for (i = 0; i < 16; i++) {		dev_priv->regfile.saveSWF0[i] = I915_READ(SWF00 + (i << 2));		dev_priv->regfile.saveSWF1[i] = I915_READ(SWF10 + (i << 2));	}	for (i = 0; i < 3; i++)		dev_priv->regfile.saveSWF2[i] = I915_READ(SWF30 + (i << 2));	mutex_unlock(&dev->struct_mutex);	return 0;}

static intgmbus_xfer(struct i2c_adapter *adapter,	   struct i2c_msg *msgs,	   int num){	struct intel_gmbus *bus = container_of(adapter,					       struct intel_gmbus,					       adapter);	struct drm_i915_private *dev_priv = bus->dev_priv;	int i, reg_offset, ret;	mutex_lock(&dev_priv->gmbus_mutex);	if (bus->force_bit) {		ret = intel_i2c_quirk_xfer(bus, msgs, num);		goto out;	}	reg_offset = HAS_PCH_SPLIT(dev_priv->dev) ? PCH_GMBUS0 - GMBUS0 : 0;	I915_WRITE(GMBUS0 + reg_offset, bus->reg0);	for (i = 0; i < num; i++) {		u16 len = msgs[i].len;		u8 *buf = msgs[i].buf;		if (msgs[i].flags & I2C_M_RD) {			I915_WRITE(GMBUS1 + reg_offset,				   GMBUS_CYCLE_WAIT |				   (i + 1 == num ? GMBUS_CYCLE_STOP : 0) |				   (len << GMBUS_BYTE_COUNT_SHIFT) |				   (msgs[i].addr << GMBUS_SLAVE_ADDR_SHIFT) |				   GMBUS_SLAVE_READ | GMBUS_SW_RDY);			POSTING_READ(GMBUS2+reg_offset);			do {				u32 val, loop = 0;				if (wait_for(I915_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_RDY), 50))					goto timeout;				if (I915_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)					goto clear_err;				val = I915_READ(GMBUS3 + reg_offset);				do {					*buf++ = val & 0xff;					val >>= 8;				} while (--len && ++loop < 4);			} while (len);		} else {

int i915_save_state(struct drm_device *dev){	struct drm_i915_private *dev_priv = dev->dev_private;	int i;	dev_priv->saveLBB = pci_read_config(dev->dev, LBB, 1);	/* Hardware status page */	dev_priv->saveHWS = I915_READ(HWS_PGA);	i915_save_display(dev);	/* Interrupt state */	if (HAS_PCH_SPLIT(dev)) {		dev_priv->saveDEIER = I915_READ(DEIER);		dev_priv->saveDEIMR = I915_READ(DEIMR);		dev_priv->saveGTIER = I915_READ(GTIER);		dev_priv->saveGTIMR = I915_READ(GTIMR);		dev_priv->saveFDI_RXA_IMR = I915_READ(_FDI_RXA_IMR);		dev_priv->saveFDI_RXB_IMR = I915_READ(_FDI_RXB_IMR);		dev_priv->saveMCHBAR_RENDER_STANDBY =			I915_READ(RSTDBYCTL);		dev_priv->savePCH_PORT_HOTPLUG = I915_READ(PCH_PORT_HOTPLUG);	} else {		dev_priv->saveIER = I915_READ(IER);		dev_priv->saveIMR = I915_READ(IMR);	}	if (IS_IRONLAKE_M(dev))		ironlake_disable_drps(dev);	if (INTEL_INFO(dev)->gen >= 6)		gen6_disable_rps(dev);	/* Cache mode state */	dev_priv->saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);	/* Memory Arbitration state */	dev_priv->saveMI_ARB_STATE = I915_READ(MI_ARB_STATE);	/* Scratch space */	for (i = 0; i < 16; i++) {		dev_priv->saveSWF0[i] = I915_READ(SWF00 + (i << 2));		dev_priv->saveSWF1[i] = I915_READ(SWF10 + (i << 2));	}	for (i = 0; i < 3; i++)		dev_priv->saveSWF2[i] = I915_READ(SWF30 + (i << 2));	return 0;}

static struct i2c_adapter *intel_gpio_create(struct drm_i915_private *dev_priv, u32 pin){	static const int map_pin_to_reg[] = {		0,		GPIOB,		GPIOA,		GPIOC,		GPIOD,		GPIOE,		0,		GPIOF,	};	struct intel_gpio *gpio;	if (pin >= ARRAY_SIZE(map_pin_to_reg) || !map_pin_to_reg[pin])		return NULL;	gpio = kzalloc(sizeof(struct intel_gpio), GFP_KERNEL);	if (gpio == NULL)		return NULL;	gpio->reg = map_pin_to_reg[pin];	if (HAS_PCH_SPLIT(dev_priv->dev))		gpio->reg += PCH_GPIOA - GPIOA;	gpio->dev_priv = dev_priv;	snprintf(gpio->adapter.name, sizeof(gpio->adapter.name),		 "i915 GPIO%c", "?BACDE?F"[pin]);	gpio->adapter.owner = THIS_MODULE;	gpio->adapter.algo_data	= &gpio->algo;	gpio->adapter.dev.parent = &dev_priv->dev->pdev->dev;	gpio->algo.setsda = set_data;	gpio->algo.setscl = set_clock;	gpio->algo.getsda = get_data;	gpio->algo.getscl = get_clock;	gpio->algo.udelay = I2C_RISEFALL_TIME;	gpio->algo.timeout = usecs_to_jiffies(2200);	gpio->algo.data = gpio;	if (i2c_bit_add_bus(&gpio->adapter))		goto out_free;	return &gpio->adapter;out_free:	kfree(gpio);	return NULL;}

static bool i915_pipe_enabled(struct drm_device *dev, enum i915_pipe pipe){	struct drm_i915_private *dev_priv = dev->dev_private;	u32	dpll_reg;	/* On IVB, 3rd pipe shares PLL with another one */	if (pipe > 1)		return false;	if (HAS_PCH_SPLIT(dev))		dpll_reg = PCH_DPLL(pipe);	else		dpll_reg = (pipe == PIPE_A) ? _DPLL_A : _DPLL_B;	return (I915_READ(dpll_reg) & DPLL_VCO_ENABLE);}

static inti830_lvds_get_backlight_native(xf86OutputPtr output){    ScrnInfoPtr scrn = output->scrn;    intel_screen_private *intel = intel_get_screen_private(scrn);    uint32_t blc_pwm_ctl, reg;    if (HAS_PCH_SPLIT(intel))      reg = BLC_PWM_CPU_CTL;    else      reg = BLC_PWM_CTL;    blc_pwm_ctl = INREG(reg);    blc_pwm_ctl &= BACKLIGHT_DUTY_CYCLE_MASK;    return blc_pwm_ctl;}