自学教程：C++ HC_LENGTH函数代码示例

static int tegra_ehci_setup(struct usb_hcd *hcd){	struct ehci_hcd *ehci = hcd_to_ehci(hcd);	struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);	int retval;#ifndef CONFIG_ARCH_TEGRA_2x_SOC	u32 val;#endif	/* EHCI registers start at offset 0x100 */	ehci->caps = hcd->regs + 0x100;	ehci->regs = hcd->regs + 0x100 +				HC_LENGTH(ehci, readl(&ehci->caps->hc_capbase));	dbg_hcs_params(ehci, "reset");	dbg_hcc_params(ehci, "reset");	/* cache this readonly data; minimize chip reads */	ehci->hcs_params = readl(&ehci->caps->hcs_params);	ehci->has_hostpc = tegra->has_hostpc;	ehci->broken_hostpc_phcd = true;#ifndef CONFIG_ARCH_TEGRA_2x_SOC	ehci->has_hostpc = 1;	val = readl(hcd->regs + HOSTPC_REG_OFFSET);	val &= ~HOSTPC1_DEVLC_STS;	val &= ~HOSTPC1_DEVLC_NYT_ASUS;	writel(val, hcd->regs + HOSTPC_REG_OFFSET);#endif	hcd->has_tt = 1;	retval = ehci_halt(ehci);	if (retval)		return retval;	/* data structure init */	retval = ehci_init(hcd);	if (retval)		return retval;	ehci->sbrn = 0x20;	ehci->controller_remote_wakeup = false;	ehci_reset(ehci);	tegra_usb_phy_reset(tegra->phy);#if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && /				!defined(CONFIG_TEGRA_SILICON_PLATFORM)	val =  readl(hcd->regs + TEGRA_STREAM_DISABLE);	val |= TEGRA_STREAM_DISABLE_OFFSET;	writel(val , hcd->regs + TEGRA_STREAM_DISABLE);#endif	ehci_port_power(ehci, 1);	return retval;}

/* called during probe() after chip reset completes */static int xhci_pci_setup(struct usb_hcd *hcd){	struct xhci_hcd		*xhci = hcd_to_xhci(hcd);	struct pci_dev		*pdev = to_pci_dev(hcd->self.controller);	int			retval;	hcd->self.sg_tablesize = TRBS_PER_SEGMENT - 2;	xhci->cap_regs = hcd->regs;	xhci->op_regs = hcd->regs +		HC_LENGTH(xhci_readl(xhci, &xhci->cap_regs->hc_capbase));	xhci->run_regs = hcd->regs +		(xhci_readl(xhci, &xhci->cap_regs->run_regs_off) & RTSOFF_MASK);	/* Cache read-only capability registers */	xhci->hcs_params1 = xhci_readl(xhci, &xhci->cap_regs->hcs_params1);	xhci->hcs_params2 = xhci_readl(xhci, &xhci->cap_regs->hcs_params2);	xhci->hcs_params3 = xhci_readl(xhci, &xhci->cap_regs->hcs_params3);	xhci->hcc_params = xhci_readl(xhci, &xhci->cap_regs->hc_capbase);	xhci->hci_version = HC_VERSION(xhci->hcc_params);	xhci->hcc_params = xhci_readl(xhci, &xhci->cap_regs->hcc_params);	xhci_print_registers(xhci);	/* Look for vendor-specific quirks */	if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&			pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&			pdev->revision == 0x0) {			xhci->quirks |= XHCI_RESET_EP_QUIRK;			xhci_dbg(xhci, "QUIRK: Fresco Logic xHC needs configure"					" endpoint cmd after reset endpoint/n");	}	/* Make sure the HC is halted. */	retval = xhci_halt(xhci);	if (retval)		return retval;	xhci_dbg(xhci, "Resetting HCD/n");	/* Reset the internal HC memory state and registers. */	retval = xhci_reset(xhci);	if (retval)		return retval;	xhci_dbg(xhci, "Reset complete/n");	xhci_dbg(xhci, "Calling HCD init/n");	/* Initialize HCD and host controller data structures. */	retval = xhci_init(hcd);	if (retval)		return retval;	xhci_dbg(xhci, "Called HCD init/n");	pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);	xhci_dbg(xhci, "Got SBRN %u/n", (unsigned int) xhci->sbrn);	/* Find any debug ports */	return xhci_pci_reinit(xhci, pdev);}

static int ehci_usb_probe(struct udevice *dev){	struct ehci_hccr *hccr = (struct ehci_hccr *)dev_get_addr(dev);	struct ehci_hcor *hcor;	hcor = (struct ehci_hcor *)((uintptr_t)hccr +				    HC_LENGTH(ehci_readl(&hccr->cr_capbase)));	return ehci_register(dev, hccr, hcor, NULL, 0, USB_INIT_HOST);}

static int ehci_brcm_reset(struct usb_hcd *hcd){	struct ehci_hcd		*ehci = hcd_to_ehci(hcd);	int ret;	ehci->big_endian_mmio = 1;	ehci->caps = (struct ehci_caps *) hcd->regs;#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0)	ehci->regs = (struct ehci_regs *) (hcd->regs +		HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase)));#else	ehci->regs = (struct ehci_regs *) (hcd->regs +		HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase)));#endif	dbg_hcs_params(ehci, "reset");	dbg_hcc_params(ehci, "reset");	/* cache this readonly data; minimize PCI reads */	ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);	/* This fixes the lockup during reboot due to prior interrupts */	ehci_writel(ehci, CMD_RESET, &ehci->regs->command);	mdelay(10);	/*	 * SWLINUX-1705: Avoid OUT packet underflows during high memory	 *   bus usage	 * port_status[0x0f] = Broadcom-proprietary USB_EHCI_INSNREG00 @ 0x90	 */	ehci_writel(ehci, 0x00800040, &ehci->regs->port_status[0x10]);	ehci_writel(ehci, 0x00000001, &ehci->regs->port_status[0x12]);	/* force HC to halt state */	ehci_halt(ehci);	ret = ehci_init(hcd);	if (ret)		return ret;	ehci_port_power(ehci, 1);	return ret;}

/* * Create the appropriate control structures to manage * a new EHCI host controller. */int ehci_hcd_init(int index, struct ehci_hccr **ret_hccr,		struct ehci_hcor **ret_hcor){	usb_brg_adrdec_setup();	struct ehci_hccr *hccr;	struct ehci_hcor *hcor;	hccr = (struct ehci_hccr *)(MVUSB0_BASE + 0x100);	hcor = (struct ehci_hcor *)((uint32_t) hccr			+ HC_LENGTH(ehci_readl(&hccr->cr_capbase)));	debug("ehci-marvell: init hccr %x and hcor %x hc_length %d/n",		(uint32_t)hccr, (uint32_t)hcor,		(uint32_t)HC_LENGTH(ehci_readl(&hccr->cr_capbase)));	*ret_hccr = hccr;	*ret_hcor = hcor;	return 0;}

static int ehci_atmel_setup(struct usb_hcd *hcd){	struct ehci_hcd *ehci = hcd_to_ehci(hcd);	int retval = 0;	/* registers start at offset 0x0 */	ehci->caps = hcd->regs;	ehci->regs = hcd->regs +<<<<<<< HEAD		HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase));=======

int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor){	u3phy_init();	mt7621_phy_init(u3phy);	reinitIP();	u2_slew_rate_calibration(u3phy);	u2_slew_rate_calibration(u3phy_p1);	*hccr = (uint32_t)XHC_IO_START;	*hcor = (struct xhci_hcor *)((uint32_t) *hccr				+ HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase)));	debug("mtk-xhci: init hccr %x and hcor %x hc_length %d/n",		(uint32_t)*hccr, (uint32_t)*hcor,		(uint32_t)HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase)));	return 0;}

/* called during probe() after chip reset completes */static int xhci_mtk_setup(struct usb_hcd *hcd){	struct xhci_hcd		*xhci;//	struct pci_dev		*pdev = to_pci_dev(hcd->self.controller);	int			retval;	u32			temp;	hcd->self.sg_tablesize = TRBS_PER_SEGMENT - 2;		/* xHCI private pointer was set in xhci_pci_probe for the second		 * registered roothub.		 */	xhci = hcd_to_xhci(hcd);	xhci->cap_regs = hcd->regs;	xhci->op_regs = hcd->regs +		HC_LENGTH(xhci_readl(xhci, &xhci->cap_regs->hc_capbase));	xhci->run_regs = hcd->regs +		(xhci_readl(xhci, &xhci->cap_regs->run_regs_off) & RTSOFF_MASK);	/* Cache read-only capability registers */	xhci->hcs_params1 = xhci_readl(xhci, &xhci->cap_regs->hcs_params1);	xhci->hcs_params2 = xhci_readl(xhci, &xhci->cap_regs->hcs_params2);	xhci->hcs_params3 = xhci_readl(xhci, &xhci->cap_regs->hcs_params3);	xhci->hcc_params = xhci_readl(xhci, &xhci->cap_regs->hc_capbase);	xhci->hci_version = HC_VERSION(xhci->hcc_params);	xhci->hcc_params = xhci_readl(xhci, &xhci->cap_regs->hcc_params);	mtktest_xhci_print_registers(xhci);	/* Make sure the HC is halted. */	retval = mtktest_xhci_halt(xhci);	if (retval)		goto error;	xhci_dbg(xhci, "Resetting HCD/n");	/* Reset the internal HC memory state and registers. */	retval = mtktest_xhci_reset(xhci);	if (retval)		goto error;	xhci_dbg(xhci, "Reset complete/n");	xhci_dbg(xhci, "Calling HCD init/n");	mtktest_setInitialReg();	/* Initialize HCD and host controller data structures. */	retval = mtktest_xhci_init(hcd);	if (retval)		goto error;	xhci_dbg(xhci, "Called HCD init/n");	return retval;error:	kfree(xhci);	return retval;}

void xhci_debugfs_init(struct xhci_hcd *xhci){	struct device		*dev = xhci_to_hcd(xhci)->self.controller;	xhci->debugfs_root = debugfs_create_dir(dev_name(dev),						xhci_debugfs_root);	INIT_LIST_HEAD(&xhci->regset_list);	xhci_debugfs_regset(xhci,			    0,			    xhci_cap_regs, ARRAY_SIZE(xhci_cap_regs),			    xhci->debugfs_root, "reg-cap");	xhci_debugfs_regset(xhci,			    HC_LENGTH(readl(&xhci->cap_regs->hc_capbase)),			    xhci_op_regs, ARRAY_SIZE(xhci_op_regs),			    xhci->debugfs_root, "reg-op");	xhci_debugfs_regset(xhci,			    readl(&xhci->cap_regs->run_regs_off) & RTSOFF_MASK,			    xhci_runtime_regs, ARRAY_SIZE(xhci_runtime_regs),			    xhci->debugfs_root, "reg-runtime");	xhci_debugfs_extcap_regset(xhci, XHCI_EXT_CAPS_LEGACY,				   xhci_extcap_legsup,				   ARRAY_SIZE(xhci_extcap_legsup),				   "reg-ext-legsup");	xhci_debugfs_extcap_regset(xhci, XHCI_EXT_CAPS_PROTOCOL,				   xhci_extcap_protocol,				   ARRAY_SIZE(xhci_extcap_protocol),				   "reg-ext-protocol");	xhci_debugfs_extcap_regset(xhci, XHCI_EXT_CAPS_DEBUG,				   xhci_extcap_dbc,				   ARRAY_SIZE(xhci_extcap_dbc),				   "reg-ext-dbc");	xhci_debugfs_create_ring_dir(xhci, &xhci->cmd_ring,				     "command-ring",				     xhci->debugfs_root);	xhci_debugfs_create_ring_dir(xhci, &xhci->event_ring,				     "event-ring",				     xhci->debugfs_root);	xhci->debugfs_slots = debugfs_create_dir("devices", xhci->debugfs_root);	xhci_debugfs_create_ports(xhci, xhci->debugfs_root);}

int ehci_hcd_init(int index, enum usb_init_type init,                  struct ehci_hccr **hccr, struct ehci_hcor **hcor){    enum usb_init_type type;#if defined(CONFIG_MX6)    u32 controller_spacing = 0x200;#elif defined(CONFIG_MX7)    u32 controller_spacing = 0x10000;#endif    struct usb_ehci *ehci = (struct usb_ehci *)(USB_BASE_ADDR +                            (controller_spacing * index));    int ret;    if (index > 3)        return -EINVAL;    enable_usboh3_clk(1);    mdelay(1);    /* Do board specific initialization */    ret = board_ehci_hcd_init(index);    if (ret)        return ret;    usb_power_config(index);    usb_oc_config(index);#if defined(CONFIG_MX6)    usb_internal_phy_clock_gate(index, 1);    usb_phy_enable(index, ehci);#endif    type = board_usb_phy_mode(index);    *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);    *hcor = (struct ehci_hcor *)((uint32_t)*hccr +                                 HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));    if ((type == init) || (type == USB_INIT_DEVICE))        board_ehci_power(index, (type == USB_INIT_DEVICE) ? 0 : 1);    if (type != init)        return -ENODEV;    if (type == USB_INIT_DEVICE)        return 0;    setbits_le32(&ehci->usbmode, CM_HOST);    writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);    setbits_le32(&ehci->portsc, USB_EN);    mdelay(10);    return 0;}

static int xhci_fsl_probe(struct udevice *dev){	struct xhci_fsl_priv *priv = dev_get_priv(dev);	struct xhci_hccr *hccr;	struct xhci_hcor *hcor;	int ret = 0;	/*	 * Get the base address for XHCI controller from the device node	 */	priv->hcd_base = devfdt_get_addr(dev);	if (priv->hcd_base == FDT_ADDR_T_NONE) {		debug("Can't get the XHCI register base address/n");		return -ENXIO;	}	priv->ctx.hcd = (struct xhci_hccr *)priv->hcd_base;	priv->ctx.dwc3_reg = (struct dwc3 *)((char *)(priv->hcd_base) +			  DWC3_REG_OFFSET);	fsl_apply_xhci_errata();	ret = fsl_xhci_core_init(&priv->ctx);	if (ret < 0) {		puts("Failed to initialize xhci/n");		return ret;	}	hccr = (struct xhci_hccr *)(priv->ctx.hcd);	hcor = (struct xhci_hcor *)((uintptr_t) hccr				+ HC_LENGTH(xhci_readl(&hccr->cr_capbase)));	debug("xhci-fsl: init hccr %lx and hcor %lx hc_length %lx/n",	      (uintptr_t)hccr, (uintptr_t)hcor,	      (uintptr_t)HC_LENGTH(xhci_readl(&hccr->cr_capbase)));	return xhci_register(dev, hccr, hcor);}

/* * Create the appropriate control structures to manage * a new EHCI host controller. */int ehci_hcd_init(void){	char *env;	int usbActive;	env = getenv("usbActive");	usbActive = simple_strtoul(env, NULL, 10);	printf("Active port:/t");	if (usbActive >= mvCtrlUsbMaxGet()) {		printf("invalid port number %d, switching to port 0/n", usbActive);		usbActive=0;	} else {		printf("%d/n", usbActive);	}	hccr = (struct ehci_hccr *)(INTER_REGS_BASE + MV_USB_REGS_OFFSET(usbActive) + 0x100);	hcor = (struct ehci_hcor *)((uint32_t) hccr + HC_LENGTH(ehci_readl(&hccr->cr_capbase)));	debug ("Marvell init hccr %x and hcor %x hc_length %d/n",		(uint32_t)hccr, (uint32_t)hcor,		(uint32_t)HC_LENGTH(ehci_readl(&hccr->cr_capbase)));	return 0;}

static void xhci_print_cap_regs(struct xhci_hcd *xhci){	u32 temp;	xhci_dbg(xhci, "xHCI capability registers at %p:/n", xhci->cap_regs);	temp = xhci_readl(xhci, &xhci->cap_regs->hc_capbase);	xhci_dbg(xhci, "CAPLENGTH AND HCIVERSION 0x%x:/n",			(unsigned int) temp);	xhci_dbg(xhci, "CAPLENGTH: 0x%x/n",			(unsigned int) HC_LENGTH(temp));	xhci_dbg(xhci, "HCIVERSION: 0x%x/n",			(unsigned int) HC_VERSION(temp));	temp = xhci_readl(xhci, &xhci->cap_regs->hcs_params1);	xhci_dbg(xhci, "HCSPARAMS 1: 0x%x/n",			(unsigned int) temp);	xhci_dbg(xhci, "  Max device slots: %u/n",			(unsigned int) HCS_MAX_SLOTS(temp));	xhci_dbg(xhci, "  Max interrupters: %u/n",			(unsigned int) HCS_MAX_INTRS(temp));	xhci_dbg(xhci, "  Max ports: %u/n",			(unsigned int) HCS_MAX_PORTS(temp));	temp = xhci_readl(xhci, &xhci->cap_regs->hcs_params2);	xhci_dbg(xhci, "HCSPARAMS 2: 0x%x/n",			(unsigned int) temp);	xhci_dbg(xhci, "  Isoc scheduling threshold: %u/n",			(unsigned int) HCS_IST(temp));	xhci_dbg(xhci, "  Maximum allowed segments in event ring: %u/n",			(unsigned int) HCS_ERST_MAX(temp));	temp = xhci_readl(xhci, &xhci->cap_regs->hcs_params3);	xhci_dbg(xhci, "HCSPARAMS 3 0x%x:/n",			(unsigned int) temp);	xhci_dbg(xhci, "  Worst case U1 device exit latency: %u/n",			(unsigned int) HCS_U1_LATENCY(temp));	xhci_dbg(xhci, "  Worst case U2 device exit latency: %u/n",			(unsigned int) HCS_U2_LATENCY(temp));	temp = xhci_readl(xhci, &xhci->cap_regs->hcc_params);	xhci_dbg(xhci, "HCC PARAMS 0x%x:/n", (unsigned int) temp);	xhci_dbg(xhci, "  HC generates %s bit addresses/n",			HCC_64BIT_ADDR(temp) ? "64" : "32");	/* FIXME */	xhci_dbg(xhci, "  FIXME: more HCCPARAMS debugging/n");	temp = xhci_readl(xhci, &xhci->cap_regs->run_regs_off);	xhci_dbg(xhci, "RTSOFF 0x%x:/n", temp & RTSOFF_MASK);}

static int ixp4xx_ehci_init(struct usb_hcd *hcd){    struct ehci_hcd *ehci = hcd_to_ehci(hcd);    int retval = 0;    ehci->big_endian_desc = 1;    ehci->big_endian_mmio = 1;    ehci->caps = hcd->regs + 0x100;    ehci->regs = hcd->regs + 0x100                 <<<<<<< HEAD                 + HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase));    =======        + HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase));

static int msm_ehci_reset(struct usb_hcd *hcd){	struct ehci_hcd *ehci = hcd_to_ehci(hcd);	struct msm_hcd *mhcd = hcd_to_mhcd(hcd);	struct msm_usb_host_platform_data *pdata;	int retval;	ehci->caps = USB_CAPLENGTH;	ehci->regs = USB_CAPLENGTH +		HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase));	dbg_hcs_params(ehci, "reset");	dbg_hcc_params(ehci, "reset");	/* cache the data to minimize the chip reads*/	ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);	hcd->has_tt = 1;	ehci->sbrn = HCD_USB2;	retval = ehci_halt(ehci);	if (retval)		return retval;	/* data structure init */	retval = ehci_init(hcd);	if (retval)		return retval;	retval = ehci_reset(ehci);	if (retval)		return retval;	/* bursts of unspecified length. */	writel_relaxed(0, USB_AHBBURST);	/* Use the AHB transactor */	writel_relaxed(0x08, USB_AHBMODE);	/* Disable streaming mode and select host mode */	writel_relaxed(0x13, USB_USBMODE);	pdata = mhcd->dev->platform_data;	if (pdata && pdata->use_sec_phy)		writel_relaxed(readl_relaxed(USB_PHY_CTRL2) | (1<<16),								USB_PHY_CTRL2);	if (pdata && pdata->sw_fpr_ctrl)		writel_relaxed(readl(USB_GENCONFIG2) | (1<<17), USB_GENCONFIG2);			ehci_port_power(ehci, 1);	return 0;}

int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor){	struct exynos_xhci *ctx = &exynos;	int ret;#ifdef CONFIG_OF_CONTROL	exynos_usb3_parse_dt(gd->fdt_blob, ctx);#else	ctx->usb3_phy = (struct exynos_usb3_phy *)samsung_get_base_usb3_phy();	ctx->hcd = (struct xhci_hccr *)samsung_get_base_usb_xhci();#endif	ctx->dwc3_reg = (struct dwc3 *)((char *)(ctx->hcd) + DWC3_REG_OFFSET);#ifdef CONFIG_OF_CONTROL	/* setup the Vbus gpio here */	if (fdt_gpio_isvalid(&ctx->vbus_gpio) &&	    !fdtdec_setup_gpio(&ctx->vbus_gpio))		gpio_direction_output(ctx->vbus_gpio.gpio, 1);#endif	ret = exynos_xhci_core_init(ctx);	if (ret) {		puts("XHCI: failed to initialize controller/n");		return -EINVAL;	}	*hccr = (ctx->hcd);	*hcor = (struct xhci_hcor *)((uint32_t) *hccr				+ HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase)));	debug("Exynos5-xhci: init hccr %x and hcor %x hc_length %d/n",		(uint32_t)*hccr, (uint32_t)*hcor,		(uint32_t)HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase)));	return 0;}

static void xhci_pci_init(struct udevice *dev, struct xhci_hccr **ret_hccr,			  struct xhci_hcor **ret_hcor){	struct xhci_hccr *hccr;	struct xhci_hcor *hcor;	u32 cmd;	hccr = (struct xhci_hccr *)dm_pci_map_bar(dev,			PCI_BASE_ADDRESS_0, PCI_REGION_MEM);	hcor = (struct xhci_hcor *)((uintptr_t) hccr +			HC_LENGTH(xhci_readl(&hccr->cr_capbase)));	debug("XHCI-PCI init hccr 0x%x and hcor 0x%x hc_length %d/n",	      (u32)hccr, (u32)hcor,	      (u32)HC_LENGTH(xhci_readl(&hccr->cr_capbase)));	*ret_hccr = hccr;	*ret_hcor = hcor;	/* enable busmaster */	dm_pci_read_config32(dev, PCI_COMMAND, &cmd);	cmd |= PCI_COMMAND_MASTER;	dm_pci_write_config32(dev, PCI_COMMAND, cmd);}

static void ehci_pci_common_init(pci_dev_t pdev, struct ehci_hccr **ret_hccr,				 struct ehci_hcor **ret_hcor){	struct ehci_hccr *hccr;	struct ehci_hcor *hcor;	uint32_t cmd;	hccr = (struct ehci_hccr *)pci_map_bar(pdev,			PCI_BASE_ADDRESS_0, PCI_REGION_MEM);	hcor = (struct ehci_hcor *)((uint32_t) hccr +			HC_LENGTH(ehci_readl(&hccr->cr_capbase)));	debug("EHCI-PCI init hccr 0x%x and hcor 0x%x hc_length %d/n",	      (uint32_t)hccr, (uint32_t)hcor,	      (uint32_t)HC_LENGTH(ehci_readl(&hccr->cr_capbase)));	*ret_hccr = hccr;	*ret_hcor = hcor;	/* enable busmaster */	pci_read_config_dword(pdev, PCI_COMMAND, &cmd);	cmd |= PCI_COMMAND_MASTER;	pci_write_config_dword(pdev, PCI_COMMAND, cmd);}

int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor){	struct ipq_xhci *ctx = &ipq;	unsigned int ipq_base;	int ret = 0;	if ( index == 0 )		ipq_base = IPQ_XHCI_BASE_1;	else		ipq_base = IPQ_XHCI_BASE_2;	ctx->hcd = (struct xhci_hccr *)ipq_base;	ctx->dwc3_reg = (struct dwc3 *)((char *)(ctx->hcd) + DWC3_REG_OFFSET);	ret = board_usb_init(index, USB_INIT_HOST);	if (ret != 0) {		puts("Failed to initialize board for USB/n");		return ret;	}	ret = ipq_xhci_core_init(ctx, ipq_base);	if (ret < 0) {		puts("Failed to initialize xhci/n");		return ret;	}	*hccr = (struct xhci_hccr *)(ipq_base);	*hcor = (struct xhci_hcor *)((uint32_t) *hccr				+ HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase)));	debug("omap-xhci: init hccr %x and hcor %x hc_length %d/n",	      (uint32_t)*hccr, (uint32_t)*hcor,	      (uint32_t)HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase)));	return ret;}

/* * EHCI-initialization * Create the appropriate control structures to manage * a new EHCI host controller. */int ehci_hcd_init(int index, enum usb_init_type init,		struct ehci_hccr **hccr, struct ehci_hcor **hcor){	struct exynos_ehci *ctx = &exynos;#ifdef CONFIG_OF_CONTROL	if (exynos_usb_parse_dt(gd->fdt_blob, ctx)) {		debug("Unable to parse device tree for ehci-exynos/n");		return -ENODEV;	}#else	ctx->usb = (struct exynos_usb_phy *)samsung_get_base_usb_phy();	ctx->hcd = (struct ehci_hccr *)samsung_get_base_usb_ehci();#endif#ifdef CONFIG_OF_CONTROL	/* setup the Vbus gpio here */	if (fdt_gpio_isvalid(&ctx->vbus_gpio) &&	    !fdtdec_setup_gpio(&ctx->vbus_gpio))		gpio_direction_output(ctx->vbus_gpio.gpio, 1);#endif	setup_usb_phy(ctx->usb);	board_usb_init(index, init);	*hccr = ctx->hcd;	*hcor = (struct ehci_hcor *)((uint32_t) *hccr				+ HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));	debug("Exynos5-ehci: init hccr %x and hcor %x hc_length %d/n",		(uint32_t)*hccr, (uint32_t)*hcor,		(uint32_t)HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));	return 0;}

/* * Create the appropriate control structures to manage * a new EHCI host controller. */int ehci_hcd_init(int index, enum usb_init_type init, struct ehci_hccr **hccr,		  struct ehci_hcor **hcor){	struct ehci_hccr *cr;	struct ehci_hcor *or;	uniphier_ehci_reset(index, 0);	cr = (struct ehci_hccr *)(uniphier_ehci_platdata[index].base);	or = (void *)cr + HC_LENGTH(ehci_readl(&cr->cr_capbase));	*hccr = cr;	*hcor = or;	return 0;}

int ehci_hcd_init(int index, enum usb_init_type init,		struct ehci_hccr **hccr, struct ehci_hcor **hcor){	/* Enable UTMI PLL */	if (at91_upll_clk_enable())		return -1;	/* Enable USB Host clock */	at91_periph_clk_enable(ATMEL_ID_UHPHS);	*hccr = (struct ehci_hccr *)ATMEL_BASE_EHCI;	*hcor = (struct ehci_hcor *)((uint32_t)*hccr +			HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));	return 0;}

int ehci_hcd_init(int index, struct ehci_hccr **ret_hccr,		struct ehci_hcor **ret_hcor){	int ret;	uint32_t usb_base, cap_base;	struct mx28_register *digctl_ctrl =		(struct mx28_register *)HW_DIGCTL_CTRL;	struct mx28_clkctrl_regs *clkctrl_regs =		(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;	ret = mxs_ehci_get_port(&ehci_mxs, CONFIG_EHCI_MXS_PORT);	if (ret)		return ret;	/* Reset the PHY block */	writel(USBPHY_CTRL_SFTRST, &ehci_mxs.phy_regs->hw_usbphy_ctrl_set);	udelay(10);	writel(USBPHY_CTRL_SFTRST | USBPHY_CTRL_CLKGATE,		&ehci_mxs.phy_regs->hw_usbphy_ctrl_clr);	/* Enable USB clock */	writel(CLKCTRL_PLL0CTRL0_EN_USB_CLKS | CLKCTRL_PLL0CTRL0_POWER,			&clkctrl_regs->hw_clkctrl_pll0ctrl0_set);	writel(CLKCTRL_PLL1CTRL0_EN_USB_CLKS | CLKCTRL_PLL1CTRL0_POWER,			&clkctrl_regs->hw_clkctrl_pll1ctrl0_set);	writel(HW_DIGCTL_CTRL_USB0_CLKGATE | HW_DIGCTL_CTRL_USB1_CLKGATE,		&digctl_ctrl->reg_clr);	/* Start USB PHY */	writel(0, &ehci_mxs.phy_regs->hw_usbphy_pwd);	/* Enable UTMI+ Level 2 and Level 3 compatibility */	writel(USBPHY_CTRL_ENUTMILEVEL3 | USBPHY_CTRL_ENUTMILEVEL2 | 1,		&ehci_mxs.phy_regs->hw_usbphy_ctrl_set);	usb_base = ((uint32_t)ehci_mxs.usb_regs) + 0x100;	*ret_hccr = (struct ehci_hccr *)usb_base;	cap_base = ehci_readl(&hccr->cr_capbase);	*ret_hcor = (struct ehci_hcor *)(usb_base + HC_LENGTH(cap_base));	return 0;}

/* * Create the appropriate control structures to manage * a new EHCI host controller. */int ehci_hcd_init(void){#if defined(RT3352_ASIC_BOARD) || defined(RT3883_ASIC_BOARD) || defined(RT5350_ASIC_BOARD)	leave_power_saving();	mdelay(100);	rt_set_host();	mdelay(100);	hccr = (struct ehci_hccr *)(0xb01c0000);	hcor = (struct ehci_hcor *)((uint32_t) hccr + HC_LENGTH(ehci_readl(&hccr->cr_capbase)));	printf("Mediatek/Ralink USB EHCI host init hccr %x and hcor %x hc_length %d/n", (uint32_t)hccr, (uint32_t)hcor, (uint32_t)HC_LENGTH(ehci_readl(&hccr->cr_capbase)));	return 0;#else	return -1;#endif}

/* * Create the appropriate control structures to manage * a new EHCI host controller. */int ehci_hcd_init(void){	pci_dev_t pdev;	uint32_t addr;	pdev = pci_find_devices(ehci_pci_ids, CONFIG_PCI_EHCI_DEVICE);	if (pdev == -1) {		printf("EHCI host controller not found/n");		return -1;	}	pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, &addr);	hccr = (struct ehci_hccr *)addr;	hcor = (struct ehci_hcor *)((uint32_t) hccr +			HC_LENGTH(ehci_readl(&hccr->cr_capbase)));	return 0;}

static int ehci_usb_probe(struct udevice *dev){	struct msm_ehci_priv *p = dev_get_priv(dev);	struct usb_ehci *ehci = p->ehci;	struct ehci_hccr *hccr;	struct ehci_hcor *hcor;	int ret;	hccr = (struct ehci_hccr *)((phys_addr_t)&ehci->caplength);	hcor = (struct ehci_hcor *)((phys_addr_t)hccr +			HC_LENGTH(ehci_readl(&(hccr)->cr_capbase)));	ret = board_prepare_usb(USB_INIT_HOST);	if (ret < 0)		return ret;	return ehci_register(dev, hccr, hcor, &msm_ehci_ops, 0, USB_INIT_HOST);}

/* called during probe() after chip reset completes */static int xhci_pci_setup(struct usb_hcd *hcd){	struct xhci_hcd		*xhci = hcd_to_xhci(hcd);	struct pci_dev		*pdev = to_pci_dev(hcd->self.controller);	int			retval;	xhci->cap_regs = hcd->regs;	xhci->op_regs = hcd->regs +		HC_LENGTH(xhci_readl(xhci, &xhci->cap_regs->hc_capbase));	xhci->run_regs = hcd->regs +		(xhci_readl(xhci, &xhci->cap_regs->run_regs_off) & RTSOFF_MASK);	/* Cache read-only capability registers */	xhci->hcs_params1 = xhci_readl(xhci, &xhci->cap_regs->hcs_params1);	xhci->hcs_params2 = xhci_readl(xhci, &xhci->cap_regs->hcs_params2);	xhci->hcs_params3 = xhci_readl(xhci, &xhci->cap_regs->hcs_params3);	xhci->hcc_params = xhci_readl(xhci, &xhci->cap_regs->hcc_params);	xhci_print_registers(xhci);	/* Make sure the HC is halted. */	retval = xhci_halt(xhci);	if (retval)		return retval;	xhci_dbg(xhci, "Resetting HCD/n");	/* Reset the internal HC memory state and registers. */	retval = xhci_reset(xhci);	if (retval)		return retval;	xhci_dbg(xhci, "Reset complete/n");	xhci_dbg(xhci, "Calling HCD init/n");	/* Initialize HCD and host controller data structures. */	retval = xhci_init(hcd);	if (retval)		return retval;	xhci_dbg(xhci, "Called HCD init/n");	pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);	xhci_dbg(xhci, "Got SBRN %u/n", (unsigned int) xhci->sbrn);	/* Find any debug ports */	return xhci_pci_reinit(xhci, pdev);}

/* * Initialize SOC FSL EHCI Controller * * This code is derived from EHCI FSL USB Linux driver for MPC5121 * */int ehci_hcd_init(int index, struct ehci_hccr **ret_hccr,		struct ehci_hcor **ret_hcor){	volatile struct usb_ehci *ehci;	struct ehci_hccr *hccr;	struct ehci_hcor *hcor;	/* Hook the memory mapped registers for EHCI-Controller */	ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB_ADDR;	hccr = (struct ehci_hccr *)((uint32_t)&(ehci->caplength));	hcor = (struct ehci_hcor *)((uint32_t) hccr +				HC_LENGTH(ehci_readl(&hccr->cr_capbase)));	/* configure interface for UTMI_WIDE */	usb_platform_dr_init(ehci);	/* Init Phy USB0 to UTMI+ */	fsl_setup_phy(hcor);	/* Set to host mode */	fsl_platform_set_host_mode(ehci);	/*	 * Setting the burst size seems to be required to prevent the	 * USB from hanging when communicating with certain USB Mass	 * storage devices. This was determined by analysing the	 * EHCI registers under Linux vs U-Boot and burstsize was the	 * major non-interrupt related difference between the two	 * implementations.	 *	 * Some USB sticks behave better than others. In particular,	 * the following USB stick is especially problematic:	 * 0930:6545 Toshiba Corp	 *	 * The burstsize is set here to match the Linux implementation.	 */	out_be32(&ehci->burstsize, FSL_EHCI_TXPBURST(8) |				   FSL_EHCI_RXPBURST(8));	*ret_hccr = hccr;	*ret_hcor = hcor;	return 0;}

int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor){	int ret;	struct xhci_hccr *cr;	struct xhci_hcor *or;	ret = get_uniphier_xhci_base(index, &cr);	if (ret < 0)		return ret;	uniphier_xhci_reset(cr, 0);	or = (void *)cr + HC_LENGTH(xhci_readl(&cr->cr_capbase));	*hccr = cr;	*hcor = or;	return 0;}

static int str9100_ehci_setup(struct usb_hcd *hcd){	struct ehci_hcd		*ehci = hcd_to_ehci(hcd);	int			retval;	ehci->caps = hcd->regs;	ehci->regs = hcd->regs + HC_LENGTH(readl(&ehci->caps->hc_capbase));	dbg_hcs_params(ehci, "reset");	dbg_hcc_params(ehci, "reset");	/* cache this readonly data; minimize chip reads */	ehci->hcs_params = readl(&ehci->caps->hcs_params);	retval = ehci_halt(ehci);	if (retval)		return retval;	return ehci_init(hcd);}