自学教程：C++ I915_READ函数代码示例

void hsw_fdi_link_train(struct drm_crtc *crtc){	struct drm_device *dev = crtc->dev;	struct drm_i915_private *dev_priv = dev->dev_private;	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);	int pipe = intel_crtc->pipe;	u32 reg, temp, i;	/* Configure CPU PLL, wait for warmup */	I915_WRITE(SPLL_CTL,			SPLL_PLL_ENABLE |			SPLL_PLL_FREQ_1350MHz |			SPLL_PLL_SCC);	/* Use SPLL to drive the output when in FDI mode */	I915_WRITE(PORT_CLK_SEL(PORT_E),			PORT_CLK_SEL_SPLL);	I915_WRITE(PIPE_CLK_SEL(pipe),			PIPE_CLK_SEL_PORT(PORT_E));	DELAY(20);	/* Start the training iterating through available voltages and emphasis */	for (i=0; i < DRM_ARRAY_SIZE(hsw_ddi_buf_ctl_values); i++) {		/* Configure DP_TP_CTL with auto-training */		I915_WRITE(DP_TP_CTL(PORT_E),					DP_TP_CTL_FDI_AUTOTRAIN |					DP_TP_CTL_ENHANCED_FRAME_ENABLE |					DP_TP_CTL_LINK_TRAIN_PAT1 |					DP_TP_CTL_ENABLE);		/* Configure and enable DDI_BUF_CTL for DDI E with next voltage */		temp = I915_READ(DDI_BUF_CTL(PORT_E));		temp = (temp & ~DDI_BUF_EMP_MASK);		I915_WRITE(DDI_BUF_CTL(PORT_E),				temp |				DDI_BUF_CTL_ENABLE |				DDI_PORT_WIDTH_X2 |				hsw_ddi_buf_ctl_values[i]);		DELAY(600);		/* Enable CPU FDI Receiver with auto-training */		reg = FDI_RX_CTL(pipe);		I915_WRITE(reg,				I915_READ(reg) |					FDI_LINK_TRAIN_AUTO |					FDI_RX_ENABLE |					FDI_LINK_TRAIN_PATTERN_1_CPT |					FDI_RX_ENHANCE_FRAME_ENABLE |					FDI_PORT_WIDTH_2X_LPT |					FDI_RX_PLL_ENABLE);		POSTING_READ(reg);		DELAY(100);		temp = I915_READ(DP_TP_STATUS(PORT_E));		if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {			DRM_DEBUG_DRIVER("BUF_CTL training done on %d step/n", i);			/* Enable normal pixel sending for FDI */			I915_WRITE(DP_TP_CTL(PORT_E),						DP_TP_CTL_FDI_AUTOTRAIN |						DP_TP_CTL_LINK_TRAIN_NORMAL |						DP_TP_CTL_ENHANCED_FRAME_ENABLE |						DP_TP_CTL_ENABLE);			/* Enable PIPE_DDI_FUNC_CTL for the pipe to work in FDI mode */			temp = I915_READ(DDI_FUNC_CTL(pipe));			temp &= ~PIPE_DDI_PORT_MASK;			temp |= PIPE_DDI_SELECT_PORT(PORT_E) |					PIPE_DDI_MODE_SELECT_FDI |					PIPE_DDI_FUNC_ENABLE |					PIPE_DDI_PORT_WIDTH_X2;			I915_WRITE(DDI_FUNC_CTL(pipe),					temp);			break;		} else {			DRM_ERROR("Error training BUF_CTL %d/n", i);			/* Disable DP_TP_CTL and FDI_RX_CTL) and retry */			I915_WRITE(DP_TP_CTL(PORT_E),					I915_READ(DP_TP_CTL(PORT_E)) &						~DP_TP_CTL_ENABLE);			I915_WRITE(FDI_RX_CTL(pipe),					I915_READ(FDI_RX_CTL(pipe)) &						~FDI_RX_PLL_ENABLE);			continue;		}	}	DRM_DEBUG_KMS("FDI train done./n");}

static void i915_save_vga(struct drm_device *dev){	struct drm_i915_private *dev_priv = dev->dev_private;	int i;	u16 cr_index, cr_data, st01;	/* VGA state */	dev_priv->regfile.saveVGA0 = I915_READ(VGA0);	dev_priv->regfile.saveVGA1 = I915_READ(VGA1);	dev_priv->regfile.saveVGA_PD = I915_READ(VGA_PD);	dev_priv->regfile.saveVGACNTRL = I915_READ(i915_vgacntrl_reg(dev));	/* VGA color palette registers */	dev_priv->regfile.saveDACMASK = I915_READ8(VGA_DACMASK);	/* MSR bits */	dev_priv->regfile.saveMSR = I915_READ8(VGA_MSR_READ);	if (dev_priv->regfile.saveMSR & VGA_MSR_CGA_MODE) {		cr_index = VGA_CR_INDEX_CGA;		cr_data = VGA_CR_DATA_CGA;		st01 = VGA_ST01_CGA;	} else {		cr_index = VGA_CR_INDEX_MDA;		cr_data = VGA_CR_DATA_MDA;		st01 = VGA_ST01_MDA;	}	/* CRT controller regs */	i915_write_indexed(dev, cr_index, cr_data, 0x11,			   i915_read_indexed(dev, cr_index, cr_data, 0x11) &			   (~0x80));	for (i = 0; i <= 0x24; i++)		dev_priv->regfile.saveCR[i] =			i915_read_indexed(dev, cr_index, cr_data, i);	/* Make sure we don't turn off CR group 0 writes */	dev_priv->regfile.saveCR[0x11] &= ~0x80;	/* Attribute controller registers */	I915_READ8(st01);	dev_priv->regfile.saveAR_INDEX = I915_READ8(VGA_AR_INDEX);	for (i = 0; i <= 0x14; i++)		dev_priv->regfile.saveAR[i] = i915_read_ar(dev, st01, i, 0);	I915_READ8(st01);	I915_WRITE8(VGA_AR_INDEX, dev_priv->regfile.saveAR_INDEX);	I915_READ8(st01);	/* Graphics controller registers */	for (i = 0; i < 9; i++)		dev_priv->regfile.saveGR[i] =			i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, i);	dev_priv->regfile.saveGR[0x10] =		i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x10);	dev_priv->regfile.saveGR[0x11] =		i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x11);	dev_priv->regfile.saveGR[0x18] =		i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x18);	/* Sequencer registers */	for (i = 0; i < 8; i++)		dev_priv->regfile.saveSR[i] =			i915_read_indexed(dev, VGA_SR_INDEX, VGA_SR_DATA, i);}

int i915_restore_state(struct drm_device *dev){	struct drm_i915_private *dev_priv = dev->dev_private;	int i;	pci_write_config_byte(dev->pdev, LBB, dev_priv->saveLBB);	I915_WRITE(DSPARB, dev_priv->saveDSPARB);	/* Pipe & plane A info */	/* Prime the clock */	if (dev_priv->saveDPLL_A & DPLL_VCO_ENABLE) {		I915_WRITE(DPLL_A, dev_priv->saveDPLL_A &			   ~DPLL_VCO_ENABLE);		DRM_UDELAY(150);	}	I915_WRITE(FPA0, dev_priv->saveFPA0);	I915_WRITE(FPA1, dev_priv->saveFPA1);	/* Actually enable it */	I915_WRITE(DPLL_A, dev_priv->saveDPLL_A);	DRM_UDELAY(150);	if (IS_I965G(dev))		I915_WRITE(DPLL_A_MD, dev_priv->saveDPLL_A_MD);	DRM_UDELAY(150);	/* Restore mode */	I915_WRITE(HTOTAL_A, dev_priv->saveHTOTAL_A);	I915_WRITE(HBLANK_A, dev_priv->saveHBLANK_A);	I915_WRITE(HSYNC_A, dev_priv->saveHSYNC_A);	I915_WRITE(VTOTAL_A, dev_priv->saveVTOTAL_A);	I915_WRITE(VBLANK_A, dev_priv->saveVBLANK_A);	I915_WRITE(VSYNC_A, dev_priv->saveVSYNC_A);	I915_WRITE(BCLRPAT_A, dev_priv->saveBCLRPAT_A);	/* Restore plane info */	I915_WRITE(DSPASIZE, dev_priv->saveDSPASIZE);	I915_WRITE(DSPAPOS, dev_priv->saveDSPAPOS);	I915_WRITE(PIPEASRC, dev_priv->savePIPEASRC);	I915_WRITE(DSPAADDR, dev_priv->saveDSPAADDR);	I915_WRITE(DSPASTRIDE, dev_priv->saveDSPASTRIDE);	if (IS_I965G(dev)) {		I915_WRITE(DSPASURF, dev_priv->saveDSPASURF);		I915_WRITE(DSPATILEOFF, dev_priv->saveDSPATILEOFF);	}	I915_WRITE(PIPEACONF, dev_priv->savePIPEACONF);	i915_restore_palette(dev, PIPE_A);	/* Enable the plane */	I915_WRITE(DSPACNTR, dev_priv->saveDSPACNTR);	I915_WRITE(DSPAADDR, I915_READ(DSPAADDR));	/* Pipe & plane B info */	if (dev_priv->saveDPLL_B & DPLL_VCO_ENABLE) {		I915_WRITE(DPLL_B, dev_priv->saveDPLL_B &			   ~DPLL_VCO_ENABLE);		DRM_UDELAY(150);	}	I915_WRITE(FPB0, dev_priv->saveFPB0);	I915_WRITE(FPB1, dev_priv->saveFPB1);	/* Actually enable it */	I915_WRITE(DPLL_B, dev_priv->saveDPLL_B);	DRM_UDELAY(150);	if (IS_I965G(dev))		I915_WRITE(DPLL_B_MD, dev_priv->saveDPLL_B_MD);	DRM_UDELAY(150);	/* Restore mode */	I915_WRITE(HTOTAL_B, dev_priv->saveHTOTAL_B);	I915_WRITE(HBLANK_B, dev_priv->saveHBLANK_B);	I915_WRITE(HSYNC_B, dev_priv->saveHSYNC_B);	I915_WRITE(VTOTAL_B, dev_priv->saveVTOTAL_B);	I915_WRITE(VBLANK_B, dev_priv->saveVBLANK_B);	I915_WRITE(VSYNC_B, dev_priv->saveVSYNC_B);	I915_WRITE(BCLRPAT_B, dev_priv->saveBCLRPAT_B);	/* Restore plane info */	I915_WRITE(DSPBSIZE, dev_priv->saveDSPBSIZE);	I915_WRITE(DSPBPOS, dev_priv->saveDSPBPOS);	I915_WRITE(PIPEBSRC, dev_priv->savePIPEBSRC);	I915_WRITE(DSPBADDR, dev_priv->saveDSPBADDR);	I915_WRITE(DSPBSTRIDE, dev_priv->saveDSPBSTRIDE);	if (IS_I965G(dev)) {		I915_WRITE(DSPBSURF, dev_priv->saveDSPBSURF);		I915_WRITE(DSPBTILEOFF, dev_priv->saveDSPBTILEOFF);	}	I915_WRITE(PIPEBCONF, dev_priv->savePIPEBCONF);	i915_restore_palette(dev, PIPE_B);	/* Enable the plane */	I915_WRITE(DSPBCNTR, dev_priv->saveDSPBCNTR);	I915_WRITE(DSPBADDR, I915_READ(DSPBADDR));	/* CRT state */	I915_WRITE(ADPA, dev_priv->saveADPA);	/* LVDS state */	if (IS_I965G(dev))		I915_WRITE(BLC_PWM_CTL2, dev_priv->saveBLC_PWM_CTL2);//.........这里部分代码省略.........

/** * Detects bit 6 swizzling of address lookup between IGD access and CPU * access through main memory. */voidi915_gem_detect_bit_6_swizzle(struct drm_device *dev){	drm_i915_private_t *dev_priv = dev->dev_private;	uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;	uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;	if (IS_VALLEYVIEW(dev)) {		swizzle_x = I915_BIT_6_SWIZZLE_NONE;		swizzle_y = I915_BIT_6_SWIZZLE_NONE;	} else if (INTEL_INFO(dev)->gen >= 6) {		uint32_t dimm_c0, dimm_c1;		dimm_c0 = I915_READ(MAD_DIMM_C0);		dimm_c1 = I915_READ(MAD_DIMM_C1);		dimm_c0 &= MAD_DIMM_A_SIZE_MASK | MAD_DIMM_B_SIZE_MASK;		dimm_c1 &= MAD_DIMM_A_SIZE_MASK | MAD_DIMM_B_SIZE_MASK;		/* Enable swizzling when the channels are populated with		 * identically sized dimms. We don't need to check the 3rd		 * channel because no cpu with gpu attached ships in that		 * configuration. Also, swizzling only makes sense for 2		 * channels anyway. */		if (dimm_c0 == dimm_c1) {			swizzle_x = I915_BIT_6_SWIZZLE_9_10;			swizzle_y = I915_BIT_6_SWIZZLE_9;		} else {			swizzle_x = I915_BIT_6_SWIZZLE_NONE;			swizzle_y = I915_BIT_6_SWIZZLE_NONE;		}	} else if (IS_GEN5(dev)) {		/* On Ironlake whatever DRAM config, GPU always do		 * same swizzling setup.		 */		swizzle_x = I915_BIT_6_SWIZZLE_9_10;		swizzle_y = I915_BIT_6_SWIZZLE_9;	} else if (IS_GEN2(dev)) {		/* As far as we know, the 865 doesn't have these bit 6		 * swizzling issues.		 */		swizzle_x = I915_BIT_6_SWIZZLE_NONE;		swizzle_y = I915_BIT_6_SWIZZLE_NONE;	} else if (IS_MOBILE(dev) || (IS_GEN3(dev) && !IS_G33(dev))) {		uint32_t dcc;		/* On 9xx chipsets, channel interleave by the CPU is		 * determined by DCC.  For single-channel, neither the CPU		 * nor the GPU do swizzling.  For dual channel interleaved,		 * the GPU's interleave is bit 9 and 10 for X tiled, and bit		 * 9 for Y tiled.  The CPU's interleave is independent, and		 * can be based on either bit 11 (haven't seen this yet) or		 * bit 17 (common).		 */		dcc = I915_READ(DCC);		switch (dcc & DCC_ADDRESSING_MODE_MASK) {		case DCC_ADDRESSING_MODE_SINGLE_CHANNEL:		case DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC:			swizzle_x = I915_BIT_6_SWIZZLE_NONE;			swizzle_y = I915_BIT_6_SWIZZLE_NONE;			break;		case DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED:			if (dcc & DCC_CHANNEL_XOR_DISABLE) {				/* This is the base swizzling by the GPU for				 * tiled buffers.				 */				swizzle_x = I915_BIT_6_SWIZZLE_9_10;				swizzle_y = I915_BIT_6_SWIZZLE_9;			} else if ((dcc & DCC_CHANNEL_XOR_BIT_17) == 0) {				/* Bit 11 swizzling by the CPU in addition. */				swizzle_x = I915_BIT_6_SWIZZLE_9_10_11;				swizzle_y = I915_BIT_6_SWIZZLE_9_11;			} else {				/* Bit 17 swizzling by the CPU in addition. */				swizzle_x = I915_BIT_6_SWIZZLE_9_10_17;				swizzle_y = I915_BIT_6_SWIZZLE_9_17;			}			break;		}		if (dcc == 0xffffffff) {			DRM_ERROR("Couldn't read from MCHBAR.  "				  "Disabling tiling./n");			swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;			swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;		}	} else {		/* The 965, G33, and newer, have a very flexible memory		 * configuration.  It will enable dual-channel mode		 * (interleaving) on as much memory as it can, and the GPU		 * will additionally sometimes enable different bit 6		 * swizzling for tiled objects from the CPU.		 *		 * Here's what I found on the G965:		 *    slot fill         memory size  swizzling		 * 0A   0B   1A   1B    1-ch   2-ch		 * 512  0    0    0     512    0     O		 * 512  0    512  0     16     1008  X		 * 512  0    0    512   16     1008  X		 * 0    512  0    512   16     1008  X//.........这里部分代码省略.........

static void i915_save_display(struct drm_device *dev){	struct drm_i915_private *dev_priv = dev->dev_private;	/* Display arbitration control */	if (INTEL_INFO(dev)->gen <= 4)		dev_priv->regfile.saveDSPARB = I915_READ(DSPARB);	/* This is only meaningful in non-KMS mode */	/* Don't regfile.save them in KMS mode */	if (!drm_core_check_feature(dev, DRIVER_MODESET))		i915_save_display_reg(dev);	/* LVDS state */	if (HAS_PCH_SPLIT(dev)) {		dev_priv->regfile.savePP_CONTROL = I915_READ(PCH_PP_CONTROL);		dev_priv->regfile.saveBLC_PWM_CTL = I915_READ(BLC_PWM_PCH_CTL1);		dev_priv->regfile.saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_PCH_CTL2);		dev_priv->regfile.saveBLC_CPU_PWM_CTL = I915_READ(BLC_PWM_CPU_CTL);		dev_priv->regfile.saveBLC_CPU_PWM_CTL2 = I915_READ(BLC_PWM_CPU_CTL2);		dev_priv->regfile.saveLVDS = I915_READ(PCH_LVDS);	} else {		dev_priv->regfile.savePP_CONTROL = I915_READ(PP_CONTROL);		dev_priv->regfile.savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS);		dev_priv->regfile.saveBLC_PWM_CTL = I915_READ(BLC_PWM_CTL);		dev_priv->regfile.saveBLC_HIST_CTL = I915_READ(BLC_HIST_CTL);		if (INTEL_INFO(dev)->gen >= 4)			dev_priv->regfile.saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2);		if (IS_MOBILE(dev) && !IS_I830(dev))			dev_priv->regfile.saveLVDS = I915_READ(LVDS);	}	if (!IS_I830(dev) && !IS_845G(dev) && !HAS_PCH_SPLIT(dev))		dev_priv->regfile.savePFIT_CONTROL = I915_READ(PFIT_CONTROL);	if (HAS_PCH_SPLIT(dev)) {		dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PCH_PP_ON_DELAYS);		dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PCH_PP_OFF_DELAYS);		dev_priv->regfile.savePP_DIVISOR = I915_READ(PCH_PP_DIVISOR);	} else {		dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PP_ON_DELAYS);		dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PP_OFF_DELAYS);		dev_priv->regfile.savePP_DIVISOR = I915_READ(PP_DIVISOR);	}	/* Only regfile.save FBC state on the platform that supports FBC */	if (I915_HAS_FBC(dev)) {		if (HAS_PCH_SPLIT(dev)) {			dev_priv->regfile.saveDPFC_CB_BASE = I915_READ(ILK_DPFC_CB_BASE);		} else if (IS_GM45(dev)) {			dev_priv->regfile.saveDPFC_CB_BASE = I915_READ(DPFC_CB_BASE);		} else {			dev_priv->regfile.saveFBC_CFB_BASE = I915_READ(FBC_CFB_BASE);			dev_priv->regfile.saveFBC_LL_BASE = I915_READ(FBC_LL_BASE);			dev_priv->regfile.saveFBC_CONTROL2 = I915_READ(FBC_CONTROL2);			dev_priv->regfile.saveFBC_CONTROL = I915_READ(FBC_CONTROL);		}	}	if (!drm_core_check_feature(dev, DRIVER_MODESET))		i915_save_vga(dev);}

void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,			       struct intel_connector *intel_connector){	struct drm_connector *connector = &intel_connector->base;	struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;	struct intel_encoder *intel_encoder = &intel_dig_port->base;	struct drm_device *dev = intel_encoder->base.dev;	struct drm_i915_private *dev_priv = dev->dev_private;	enum port port = intel_dig_port->port;	drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,			   DRM_MODE_CONNECTOR_HDMIA);	drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);	connector->interlace_allowed = 1;	connector->doublescan_allowed = 0;	connector->stereo_allowed = 1;	switch (port) {	case PORT_B:		intel_hdmi->ddc_bus = GMBUS_PORT_DPB;		intel_encoder->hpd_pin = HPD_PORT_B;		break;	case PORT_C:		intel_hdmi->ddc_bus = GMBUS_PORT_DPC;		intel_encoder->hpd_pin = HPD_PORT_C;		break;	case PORT_D:		intel_hdmi->ddc_bus = GMBUS_PORT_DPD;		intel_encoder->hpd_pin = HPD_PORT_D;		break;	case PORT_A:		intel_encoder->hpd_pin = HPD_PORT_A;		/* Internal port only for eDP. */	default:		BUG();	}	if (IS_VALLEYVIEW(dev)) {		intel_hdmi->write_infoframe = vlv_write_infoframe;		intel_hdmi->set_infoframes = vlv_set_infoframes;	} else if (!HAS_PCH_SPLIT(dev)) {		intel_hdmi->write_infoframe = g4x_write_infoframe;		intel_hdmi->set_infoframes = g4x_set_infoframes;	} else if (HAS_DDI(dev)) {		intel_hdmi->write_infoframe = hsw_write_infoframe;		intel_hdmi->set_infoframes = hsw_set_infoframes;	} else if (HAS_PCH_IBX(dev)) {		intel_hdmi->write_infoframe = ibx_write_infoframe;		intel_hdmi->set_infoframes = ibx_set_infoframes;	} else {		intel_hdmi->write_infoframe = cpt_write_infoframe;		intel_hdmi->set_infoframes = cpt_set_infoframes;	}	if (HAS_DDI(dev))		intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;	else		intel_connector->get_hw_state = intel_connector_get_hw_state;	intel_hdmi_add_properties(intel_hdmi, connector);	intel_connector_attach_encoder(intel_connector, intel_encoder);	drm_sysfs_connector_add(connector);	/* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written	 * 0xd.  Failure to do so will result in spurious interrupts being	 * generated on the port when a cable is not attached.	 */	if (IS_G4X(dev) && !IS_GM45(dev)) {		u32 temp = I915_READ(PEG_BAND_GAP_DATA);		I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);	}}

static void ibx_set_infoframes(struct drm_encoder *encoder,			       struct drm_display_mode *adjusted_mode){	struct drm_i915_private *dev_priv = encoder->dev->dev_private;	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);	struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;	u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);	u32 val = I915_READ(reg);	u32 port;	assert_hdmi_port_disabled(intel_hdmi);	/* See the big comment in g4x_set_infoframes() */	val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;	if (!intel_hdmi->has_hdmi_sink) {		if (!(val & VIDEO_DIP_ENABLE))			return;		val &= ~VIDEO_DIP_ENABLE;		I915_WRITE(reg, val);		POSTING_READ(reg);		return;	}	switch (intel_dig_port->port) {	case PORT_B:		port = VIDEO_DIP_PORT_B;		break;	case PORT_C:		port = VIDEO_DIP_PORT_C;		break;	case PORT_D:		port = VIDEO_DIP_PORT_D;		break;	default:		BUG();		return;	}	if (port != (val & VIDEO_DIP_PORT_MASK)) {		if (val & VIDEO_DIP_ENABLE) {			val &= ~VIDEO_DIP_ENABLE;			I915_WRITE(reg, val);			POSTING_READ(reg);		}		val &= ~VIDEO_DIP_PORT_MASK;		val |= port;	}	val |= VIDEO_DIP_ENABLE;	val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |		 VIDEO_DIP_ENABLE_GCP);	I915_WRITE(reg, val);	POSTING_READ(reg);	intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);	intel_hdmi_set_spd_infoframe(encoder);	intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);}

static voidilk_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb,		 struct drm_i915_gem_object *obj, int crtc_x, int crtc_y,		 unsigned int crtc_w, unsigned int crtc_h,		 uint32_t x, uint32_t y,		 uint32_t src_w, uint32_t src_h){	struct drm_device *dev = plane->dev;	struct drm_i915_private *dev_priv = dev->dev_private;	struct intel_plane *intel_plane = to_intel_plane(plane);	int pipe = intel_plane->pipe;	unsigned long dvssurf_offset, linear_offset;	u32 dvscntr, dvsscale;	int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);	dvscntr = I915_READ(DVSCNTR(pipe));	/* Mask out pixel format bits in case we change it */	dvscntr &= ~DVS_PIXFORMAT_MASK;	dvscntr &= ~DVS_RGB_ORDER_XBGR;	dvscntr &= ~DVS_YUV_BYTE_ORDER_MASK;	dvscntr &= ~DVS_TILED;	switch (fb->pixel_format) {	case DRM_FORMAT_XBGR8888:		dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR;		break;	case DRM_FORMAT_XRGB8888:		dvscntr |= DVS_FORMAT_RGBX888;		break;	case DRM_FORMAT_YUYV:		dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV;		break;	case DRM_FORMAT_YVYU:		dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU;		break;	case DRM_FORMAT_UYVY:		dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY;		break;	case DRM_FORMAT_VYUY:		dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY;		break;	default:		BUG();	}	if (obj->tiling_mode != I915_TILING_NONE)		dvscntr |= DVS_TILED;	if (IS_GEN6(dev))		dvscntr |= DVS_TRICKLE_FEED_DISABLE; /* must disable */	dvscntr |= DVS_ENABLE;	/* Sizes are 0 based */	src_w--;	src_h--;	crtc_w--;	crtc_h--;	intel_update_sprite_watermarks(dev, pipe, crtc_w, pixel_size);	dvsscale = 0;	if (IS_GEN5(dev) || crtc_w != src_w || crtc_h != src_h)		dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;	I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]);	I915_WRITE(DVSPOS(pipe), (crtc_y << 16) | crtc_x);	linear_offset = y * fb->pitches[0] + x * pixel_size;	dvssurf_offset =		intel_gen4_compute_offset_xtiled(&x, &y,						 pixel_size, fb->pitches[0]);	linear_offset -= dvssurf_offset;	if (obj->tiling_mode != I915_TILING_NONE)		I915_WRITE(DVSTILEOFF(pipe), (y << 16) | x);	else		I915_WRITE(DVSLINOFF(pipe), linear_offset);	I915_WRITE(DVSSIZE(pipe), (crtc_h << 16) | crtc_w);	I915_WRITE(DVSSCALE(pipe), dvsscale);	I915_WRITE(DVSCNTR(pipe), dvscntr);	I915_MODIFY_DISPBASE(DVSSURF(pipe), obj->gtt_offset + dvssurf_offset);	POSTING_READ(DVSSURF(pipe));}

static voidivb_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb,		 struct drm_i915_gem_object *obj, int crtc_x, int crtc_y,		 unsigned int crtc_w, unsigned int crtc_h,		 uint32_t x, uint32_t y,		 uint32_t src_w, uint32_t src_h){	struct drm_device *dev = plane->dev;	struct drm_i915_private *dev_priv = dev->dev_private;	struct intel_plane *intel_plane = to_intel_plane(plane);	int pipe = intel_plane->pipe;	u32 sprctl, sprscale = 0;	unsigned long sprsurf_offset, linear_offset;	int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);	sprctl = I915_READ(SPRCTL(pipe));	/* Mask out pixel format bits in case we change it */	sprctl &= ~SPRITE_PIXFORMAT_MASK;	sprctl &= ~SPRITE_RGB_ORDER_RGBX;	sprctl &= ~SPRITE_YUV_BYTE_ORDER_MASK;	sprctl &= ~SPRITE_TILED;	switch (fb->pixel_format) {	case DRM_FORMAT_XBGR8888:		sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX;		break;	case DRM_FORMAT_XRGB8888:		sprctl |= SPRITE_FORMAT_RGBX888;		break;	case DRM_FORMAT_YUYV:		sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV;		break;	case DRM_FORMAT_YVYU:		sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU;		break;	case DRM_FORMAT_UYVY:		sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY;		break;	case DRM_FORMAT_VYUY:		sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY;		break;	default:		BUG();	}	if (obj->tiling_mode != I915_TILING_NONE)		sprctl |= SPRITE_TILED;	/* must disable */	sprctl |= SPRITE_TRICKLE_FEED_DISABLE;	sprctl |= SPRITE_ENABLE;	/* Sizes are 0 based */	src_w--;	src_h--;	crtc_w--;	crtc_h--;	intel_update_sprite_watermarks(dev, pipe, crtc_w, pixel_size);	/*	 * IVB workaround: must disable low power watermarks for at least	 * one frame before enabling scaling.  LP watermarks can be re-enabled	 * when scaling is disabled.	 */	if (crtc_w != src_w || crtc_h != src_h) {		if (!dev_priv->sprite_scaling_enabled) {			dev_priv->sprite_scaling_enabled = true;			intel_update_watermarks(dev);			intel_wait_for_vblank(dev, pipe);		}		sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;	} else {		if (dev_priv->sprite_scaling_enabled) {			dev_priv->sprite_scaling_enabled = false;			/* potentially re-enable LP watermarks */			intel_update_watermarks(dev);		}	}	I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]);	I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x);	linear_offset = y * fb->pitches[0] + x * pixel_size;	sprsurf_offset =		intel_gen4_compute_offset_xtiled(&x, &y,						 pixel_size, fb->pitches[0]);	linear_offset -= sprsurf_offset;	/* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET	 * register */	if (IS_HASWELL(dev))		I915_WRITE(SPROFFSET(pipe), (y << 16) | x);	else if (obj->tiling_mode != I915_TILING_NONE)		I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x);	else		I915_WRITE(SPRLINOFF(pipe), linear_offset);	I915_WRITE(SPRSIZE(pipe), (crtc_h << 16) | crtc_w);//.........这里部分代码省略.........

static void i915_save_display(struct drm_device *dev){	struct drm_i915_private *dev_priv = dev->dev_private;	/* Display arbitration control */	if (INTEL_INFO(dev)->gen <= 4)		dev_priv->regfile.saveDSPARB = I915_READ(DSPARB);	/* This is only meaningful in non-KMS mode */	/* Don't regfile.save them in KMS mode */	if (!drm_core_check_feature(dev, DRIVER_MODESET))		i915_save_display_reg(dev);	/* LVDS state */	if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))		dev_priv->regfile.saveLVDS = I915_READ(PCH_LVDS);	else if (INTEL_INFO(dev)->gen <= 4 && IS_MOBILE(dev) && !IS_I830(dev))		dev_priv->regfile.saveLVDS = I915_READ(LVDS);	/* Panel power sequencer */	if (HAS_PCH_SPLIT(dev)) {		dev_priv->regfile.savePP_CONTROL = I915_READ(PCH_PP_CONTROL);		dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PCH_PP_ON_DELAYS);		dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PCH_PP_OFF_DELAYS);		dev_priv->regfile.savePP_DIVISOR = I915_READ(PCH_PP_DIVISOR);	} else if (!IS_VALLEYVIEW(dev)) {		dev_priv->regfile.savePP_CONTROL = I915_READ(PP_CONTROL);		dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PP_ON_DELAYS);		dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PP_OFF_DELAYS);		dev_priv->regfile.savePP_DIVISOR = I915_READ(PP_DIVISOR);	}	/* save FBC interval */	if (HAS_FBC(dev) && INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev))		dev_priv->regfile.saveFBC_CONTROL = I915_READ(FBC_CONTROL);	if (!drm_core_check_feature(dev, DRIVER_MODESET))		i915_save_vga(dev);}

void intel_ddi_mode_set(struct drm_encoder *encoder,				struct drm_display_mode *mode,				struct drm_display_mode *adjusted_mode){	struct drm_device *dev = encoder->dev;	struct drm_i915_private *dev_priv = dev->dev_private;	struct drm_crtc *crtc = encoder->crtc;	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);	int port = intel_hdmi->ddi_port;	int pipe = intel_crtc->pipe;	int p, n2, r2, valid=0;	u32 temp, i;	/* On Haswell, we need to enable the clocks and prepare DDI function to	 * work in HDMI mode for this pipe.	 */	DRM_DEBUG_KMS("Preparing HDMI DDI mode for Haswell on port %c, pipe %c/n", port_name(port), pipe_name(pipe));	for (i=0; i < DRM_ARRAY_SIZE(wrpll_tmds_clock_table); i++) {		if (crtc->mode.clock == wrpll_tmds_clock_table[i].clock) {			p = wrpll_tmds_clock_table[i].p;			n2 = wrpll_tmds_clock_table[i].n2;			r2 = wrpll_tmds_clock_table[i].r2;			DRM_DEBUG_KMS("WR PLL clock: found settings for %dKHz refresh rate: p=%d, n2=%d, r2=%d/n",					crtc->mode.clock,					p, n2, r2);			valid = 1;			break;		}	}	if (!valid) {		DRM_ERROR("Unable to find WR PLL clock settings for %dKHz refresh rate/n",				crtc->mode.clock);		return;	}	/* Enable LCPLL if disabled */	temp = I915_READ(LCPLL_CTL);	if (temp & LCPLL_PLL_DISABLE)		I915_WRITE(LCPLL_CTL,				temp & ~LCPLL_PLL_DISABLE);	/* Configure WR PLL 1, program the correct divider values for	 * the desired frequency and wait for warmup */	I915_WRITE(WRPLL_CTL1,			WRPLL_PLL_ENABLE |			WRPLL_PLL_SELECT_LCPLL_2700 |			WRPLL_DIVIDER_REFERENCE(r2) |			WRPLL_DIVIDER_FEEDBACK(n2) |			WRPLL_DIVIDER_POST(p));	DELAY(20);	/* Use WRPLL1 clock to drive the output to the port, and tell the pipe to use	 * this port for connection.	 */	I915_WRITE(PORT_CLK_SEL(port),			PORT_CLK_SEL_WRPLL1);	I915_WRITE(PIPE_CLK_SEL(pipe),			PIPE_CLK_SEL_PORT(port));	DELAY(20);	if (intel_hdmi->has_audio) {		/* Proper support for digital audio needs a new logic and a new set		 * of registers, so we leave it for future patch bombing.		 */		DRM_DEBUG_DRIVER("HDMI audio on pipe %c not yet supported on DDI/n",				 pipe_name(intel_crtc->pipe));	}	/* Enable PIPE_DDI_FUNC_CTL for the pipe to work in HDMI mode */	temp = I915_READ(DDI_FUNC_CTL(pipe));	temp &= ~PIPE_DDI_PORT_MASK;	temp &= ~PIPE_DDI_BPC_12;	temp |= PIPE_DDI_SELECT_PORT(port) |			PIPE_DDI_MODE_SELECT_HDMI |			((intel_crtc->bpp > 24) ?				PIPE_DDI_BPC_12 :				PIPE_DDI_BPC_8) |			PIPE_DDI_FUNC_ENABLE;	I915_WRITE(DDI_FUNC_CTL(pipe), temp);	intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);	intel_hdmi_set_spd_infoframe(encoder);}

static bool i8xx_fbc_enabled(struct drm_i915_private *dev_priv){	return I915_READ(FBC_CONTROL) & FBC_CTL_EN;}

static void i915_save_modeset_reg(struct drm_device *dev){	struct drm_i915_private *dev_priv = dev->dev_private;	int i;	if (drm_core_check_feature(dev, DRIVER_MODESET))		return;	/* Cursor state */	dev_priv->saveCURACNTR = I915_READ(_CURACNTR);	dev_priv->saveCURAPOS = I915_READ(_CURAPOS);	dev_priv->saveCURABASE = I915_READ(_CURABASE);	dev_priv->saveCURBCNTR = I915_READ(_CURBCNTR);	dev_priv->saveCURBPOS = I915_READ(_CURBPOS);	dev_priv->saveCURBBASE = I915_READ(_CURBBASE);	if (IS_GEN2(dev))		dev_priv->saveCURSIZE = I915_READ(CURSIZE);	if (HAS_PCH_SPLIT(dev)) {		dev_priv->savePCH_DREF_CONTROL = I915_READ(PCH_DREF_CONTROL);		dev_priv->saveDISP_ARB_CTL = I915_READ(DISP_ARB_CTL);	}	/* Pipe & plane A info */	dev_priv->savePIPEACONF = I915_READ(_PIPEACONF);	dev_priv->savePIPEASRC = I915_READ(_PIPEASRC);	if (HAS_PCH_SPLIT(dev)) {		dev_priv->saveFPA0 = I915_READ(_PCH_FPA0);		dev_priv->saveFPA1 = I915_READ(_PCH_FPA1);		dev_priv->saveDPLL_A = I915_READ(_PCH_DPLL_A);	} else {		dev_priv->saveFPA0 = I915_READ(_FPA0);		dev_priv->saveFPA1 = I915_READ(_FPA1);		dev_priv->saveDPLL_A = I915_READ(_DPLL_A);	}	if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))		dev_priv->saveDPLL_A_MD = I915_READ(_DPLL_A_MD);	dev_priv->saveHTOTAL_A = I915_READ(_HTOTAL_A);	dev_priv->saveHBLANK_A = I915_READ(_HBLANK_A);	dev_priv->saveHSYNC_A = I915_READ(_HSYNC_A);	dev_priv->saveVTOTAL_A = I915_READ(_VTOTAL_A);	dev_priv->saveVBLANK_A = I915_READ(_VBLANK_A);	dev_priv->saveVSYNC_A = I915_READ(_VSYNC_A);	if (!HAS_PCH_SPLIT(dev))		dev_priv->saveBCLRPAT_A = I915_READ(_BCLRPAT_A);	if (HAS_PCH_SPLIT(dev)) {		dev_priv->savePIPEA_DATA_M1 = I915_READ(_PIPEA_DATA_M1);		dev_priv->savePIPEA_DATA_N1 = I915_READ(_PIPEA_DATA_N1);		dev_priv->savePIPEA_LINK_M1 = I915_READ(_PIPEA_LINK_M1);		dev_priv->savePIPEA_LINK_N1 = I915_READ(_PIPEA_LINK_N1);		dev_priv->saveFDI_TXA_CTL = I915_READ(_FDI_TXA_CTL);		dev_priv->saveFDI_RXA_CTL = I915_READ(_FDI_RXA_CTL);		dev_priv->savePFA_CTL_1 = I915_READ(_PFA_CTL_1);		dev_priv->savePFA_WIN_SZ = I915_READ(_PFA_WIN_SZ);		dev_priv->savePFA_WIN_POS = I915_READ(_PFA_WIN_POS);		dev_priv->saveTRANSACONF = I915_READ(_TRANSACONF);		dev_priv->saveTRANS_HTOTAL_A = I915_READ(_TRANS_HTOTAL_A);		dev_priv->saveTRANS_HBLANK_A = I915_READ(_TRANS_HBLANK_A);		dev_priv->saveTRANS_HSYNC_A = I915_READ(_TRANS_HSYNC_A);		dev_priv->saveTRANS_VTOTAL_A = I915_READ(_TRANS_VTOTAL_A);		dev_priv->saveTRANS_VBLANK_A = I915_READ(_TRANS_VBLANK_A);		dev_priv->saveTRANS_VSYNC_A = I915_READ(_TRANS_VSYNC_A);	}	dev_priv->saveDSPACNTR = I915_READ(_DSPACNTR);	dev_priv->saveDSPASTRIDE = I915_READ(_DSPASTRIDE);	dev_priv->saveDSPASIZE = I915_READ(_DSPASIZE);	dev_priv->saveDSPAPOS = I915_READ(_DSPAPOS);	dev_priv->saveDSPAADDR = I915_READ(_DSPAADDR);	if (INTEL_INFO(dev)->gen >= 4) {		dev_priv->saveDSPASURF = I915_READ(_DSPASURF);		dev_priv->saveDSPATILEOFF = I915_READ(_DSPATILEOFF);	}	i915_save_palette(dev, PIPE_A);	dev_priv->savePIPEASTAT = I915_READ(_PIPEASTAT);	/* Pipe & plane B info */	dev_priv->savePIPEBCONF = I915_READ(_PIPEBCONF);	dev_priv->savePIPEBSRC = I915_READ(_PIPEBSRC);	if (HAS_PCH_SPLIT(dev)) {		dev_priv->saveFPB0 = I915_READ(_PCH_FPB0);		dev_priv->saveFPB1 = I915_READ(_PCH_FPB1);		dev_priv->saveDPLL_B = I915_READ(_PCH_DPLL_B);	} else {		dev_priv->saveFPB0 = I915_READ(_FPB0);		dev_priv->saveFPB1 = I915_READ(_FPB1);		dev_priv->saveDPLL_B = I915_READ(_DPLL_B);	}	if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))		dev_priv->saveDPLL_B_MD = I915_READ(_DPLL_B_MD);	dev_priv->saveHTOTAL_B = I915_READ(_HTOTAL_B);	dev_priv->saveHBLANK_B = I915_READ(_HBLANK_B);	dev_priv->saveHSYNC_B = I915_READ(_HSYNC_B);	dev_priv->saveVTOTAL_B = I915_READ(_VTOTAL_B);	dev_priv->saveVBLANK_B = I915_READ(_VBLANK_B);	dev_priv->saveVSYNC_B = I915_READ(_VSYNC_B);//.........这里部分代码省略.........

static bool ilk_fbc_enabled(struct drm_i915_private *dev_priv){	return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;}

//.........这里部分代码省略.........		I915_WRITE(_FDI_RXA_CTL, dev_priv->saveFDI_RXA_CTL);		I915_WRITE(_FDI_TXA_CTL, dev_priv->saveFDI_TXA_CTL);		I915_WRITE(_PFA_CTL_1, dev_priv->savePFA_CTL_1);		I915_WRITE(_PFA_WIN_SZ, dev_priv->savePFA_WIN_SZ);		I915_WRITE(_PFA_WIN_POS, dev_priv->savePFA_WIN_POS);		I915_WRITE(_TRANSACONF, dev_priv->saveTRANSACONF);		I915_WRITE(_TRANS_HTOTAL_A, dev_priv->saveTRANS_HTOTAL_A);		I915_WRITE(_TRANS_HBLANK_A, dev_priv->saveTRANS_HBLANK_A);		I915_WRITE(_TRANS_HSYNC_A, dev_priv->saveTRANS_HSYNC_A);		I915_WRITE(_TRANS_VTOTAL_A, dev_priv->saveTRANS_VTOTAL_A);		I915_WRITE(_TRANS_VBLANK_A, dev_priv->saveTRANS_VBLANK_A);		I915_WRITE(_TRANS_VSYNC_A, dev_priv->saveTRANS_VSYNC_A);	}	/* Restore plane info */	I915_WRITE(_DSPASIZE, dev_priv->saveDSPASIZE);	I915_WRITE(_DSPAPOS, dev_priv->saveDSPAPOS);	I915_WRITE(_PIPEASRC, dev_priv->savePIPEASRC);	I915_WRITE(_DSPAADDR, dev_priv->saveDSPAADDR);	I915_WRITE(_DSPASTRIDE, dev_priv->saveDSPASTRIDE);	if (INTEL_INFO(dev)->gen >= 4) {		I915_WRITE(_DSPASURF, dev_priv->saveDSPASURF);		I915_WRITE(_DSPATILEOFF, dev_priv->saveDSPATILEOFF);	}	I915_WRITE(_PIPEACONF, dev_priv->savePIPEACONF);	i915_restore_palette(dev, PIPE_A);	/* Enable the plane */	I915_WRITE(_DSPACNTR, dev_priv->saveDSPACNTR);	I915_WRITE(_DSPAADDR, I915_READ(_DSPAADDR));	/* Pipe & plane B info */	if (dev_priv->saveDPLL_B & DPLL_VCO_ENABLE) {		I915_WRITE(dpll_b_reg, dev_priv->saveDPLL_B &			   ~DPLL_VCO_ENABLE);		POSTING_READ(dpll_b_reg);		udelay(150);	}	I915_WRITE(fpb0_reg, dev_priv->saveFPB0);	I915_WRITE(fpb1_reg, dev_priv->saveFPB1);	/* Actually enable it */	I915_WRITE(dpll_b_reg, dev_priv->saveDPLL_B);	POSTING_READ(dpll_b_reg);	udelay(150);	if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {		I915_WRITE(_DPLL_B_MD, dev_priv->saveDPLL_B_MD);		POSTING_READ(_DPLL_B_MD);	}	udelay(150);	/* Restore mode */	I915_WRITE(_HTOTAL_B, dev_priv->saveHTOTAL_B);	I915_WRITE(_HBLANK_B, dev_priv->saveHBLANK_B);	I915_WRITE(_HSYNC_B, dev_priv->saveHSYNC_B);	I915_WRITE(_VTOTAL_B, dev_priv->saveVTOTAL_B);	I915_WRITE(_VBLANK_B, dev_priv->saveVBLANK_B);	I915_WRITE(_VSYNC_B, dev_priv->saveVSYNC_B);	if (!HAS_PCH_SPLIT(dev))		I915_WRITE(_BCLRPAT_B, dev_priv->saveBCLRPAT_B);	if (HAS_PCH_SPLIT(dev)) {		I915_WRITE(_PIPEB_DATA_M1, dev_priv->savePIPEB_DATA_M1);

static void g4x_set_infoframes(struct drm_encoder *encoder,			       struct drm_display_mode *adjusted_mode){	struct drm_i915_private *dev_priv = encoder->dev->dev_private;	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);	struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;	u32 reg = VIDEO_DIP_CTL;	u32 val = I915_READ(reg);	u32 port;	assert_hdmi_port_disabled(intel_hdmi);	/* If the registers were not initialized yet, they might be zeroes,	 * which means we're selecting the AVI DIP and we're setting its	 * frequency to once. This seems to really confuse the HW and make	 * things stop working (the register spec says the AVI always needs to	 * be sent every VSync). So here we avoid writing to the register more	 * than we need and also explicitly select the AVI DIP and explicitly	 * set its frequency to every VSync. Avoiding to write it twice seems to	 * be enough to solve the problem, but being defensive shouldn't hurt us	 * either. */	val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;	if (!intel_hdmi->has_hdmi_sink) {		if (!(val & VIDEO_DIP_ENABLE))			return;		val &= ~VIDEO_DIP_ENABLE;		I915_WRITE(reg, val);		POSTING_READ(reg);		return;	}	switch (intel_dig_port->port) {	case PORT_B:		port = VIDEO_DIP_PORT_B;		break;	case PORT_C:		port = VIDEO_DIP_PORT_C;		break;	default:		BUG();		return;	}	if (port != (val & VIDEO_DIP_PORT_MASK)) {		if (val & VIDEO_DIP_ENABLE) {			val &= ~VIDEO_DIP_ENABLE;			I915_WRITE(reg, val);			POSTING_READ(reg);		}		val &= ~VIDEO_DIP_PORT_MASK;		val |= port;	}	val |= VIDEO_DIP_ENABLE;	val &= ~VIDEO_DIP_ENABLE_VENDOR;	I915_WRITE(reg, val);	POSTING_READ(reg);	intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);	intel_hdmi_set_spd_infoframe(encoder);	intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);}

static void i915_save_display(struct drm_device *dev){	struct drm_i915_private *dev_priv = dev->dev_private;	/* Display arbitration control */	dev_priv->saveDSPARB = I915_READ(DSPARB);	/* This is only meaningful in non-KMS mode */	/* Don't save them in KMS mode */	i915_save_modeset_reg(dev);	/* CRT state */	if (HAS_PCH_SPLIT(dev)) {		dev_priv->saveADPA = I915_READ(PCH_ADPA);	} else {		dev_priv->saveADPA = I915_READ(ADPA);	}	/* LVDS state */	if (HAS_PCH_SPLIT(dev)) {		dev_priv->savePP_CONTROL = I915_READ(PCH_PP_CONTROL);		dev_priv->saveBLC_PWM_CTL = I915_READ(BLC_PWM_PCH_CTL1);		dev_priv->saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_PCH_CTL2);		dev_priv->saveBLC_CPU_PWM_CTL = I915_READ(BLC_PWM_CPU_CTL);		dev_priv->saveBLC_CPU_PWM_CTL2 = I915_READ(BLC_PWM_CPU_CTL2);		dev_priv->saveLVDS = I915_READ(PCH_LVDS);	} else {		dev_priv->savePP_CONTROL = I915_READ(PP_CONTROL);		dev_priv->savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS);		dev_priv->saveBLC_PWM_CTL = I915_READ(BLC_PWM_CTL);		dev_priv->saveBLC_HIST_CTL = I915_READ(BLC_HIST_CTL);		if (INTEL_INFO(dev)->gen >= 4)			dev_priv->saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2);		if (IS_MOBILE(dev) && !IS_I830(dev))			dev_priv->saveLVDS = I915_READ(LVDS);	}	if (!IS_I830(dev) && !IS_845G(dev) && !HAS_PCH_SPLIT(dev))		dev_priv->savePFIT_CONTROL = I915_READ(PFIT_CONTROL);	if (HAS_PCH_SPLIT(dev)) {		dev_priv->savePP_ON_DELAYS = I915_READ(PCH_PP_ON_DELAYS);		dev_priv->savePP_OFF_DELAYS = I915_READ(PCH_PP_OFF_DELAYS);		dev_priv->savePP_DIVISOR = I915_READ(PCH_PP_DIVISOR);	} else {		dev_priv->savePP_ON_DELAYS = I915_READ(PP_ON_DELAYS);		dev_priv->savePP_OFF_DELAYS = I915_READ(PP_OFF_DELAYS);		dev_priv->savePP_DIVISOR = I915_READ(PP_DIVISOR);	}	/* Display Port state */	if (SUPPORTS_INTEGRATED_DP(dev)) {		dev_priv->saveDP_B = I915_READ(DP_B);		dev_priv->saveDP_C = I915_READ(DP_C);		dev_priv->saveDP_D = I915_READ(DP_D);		dev_priv->savePIPEA_GMCH_DATA_M = I915_READ(_PIPEA_GMCH_DATA_M);		dev_priv->savePIPEB_GMCH_DATA_M = I915_READ(_PIPEB_GMCH_DATA_M);		dev_priv->savePIPEA_GMCH_DATA_N = I915_READ(_PIPEA_GMCH_DATA_N);		dev_priv->savePIPEB_GMCH_DATA_N = I915_READ(_PIPEB_GMCH_DATA_N);		dev_priv->savePIPEA_DP_LINK_M = I915_READ(_PIPEA_DP_LINK_M);		dev_priv->savePIPEB_DP_LINK_M = I915_READ(_PIPEB_DP_LINK_M);		dev_priv->savePIPEA_DP_LINK_N = I915_READ(_PIPEA_DP_LINK_N);		dev_priv->savePIPEB_DP_LINK_N = I915_READ(_PIPEB_DP_LINK_N);	}	/* FIXME: save TV & SDVO state */	/* Only save FBC state on the platform that supports FBC */	if (I915_HAS_FBC(dev)) {		if (HAS_PCH_SPLIT(dev)) {			dev_priv->saveDPFC_CB_BASE = I915_READ(ILK_DPFC_CB_BASE);		} else if (IS_GM45(dev)) {			dev_priv->saveDPFC_CB_BASE = I915_READ(DPFC_CB_BASE);		} else {			dev_priv->saveFBC_CFB_BASE = I915_READ(FBC_CFB_BASE);			dev_priv->saveFBC_LL_BASE = I915_READ(FBC_LL_BASE);			dev_priv->saveFBC_CONTROL2 = I915_READ(FBC_CONTROL2);			dev_priv->saveFBC_CONTROL = I915_READ(FBC_CONTROL);		}	}	/* VGA state */	dev_priv->saveVGA0 = I915_READ(VGA0);	dev_priv->saveVGA1 = I915_READ(VGA1);	dev_priv->saveVGA_PD = I915_READ(VGA_PD);	if (HAS_PCH_SPLIT(dev))		dev_priv->saveVGACNTRL = I915_READ(CPU_VGACNTRL);	else		dev_priv->saveVGACNTRL = I915_READ(VGACNTRL);	i915_save_vga(dev);}

int i915_save_state(struct drm_device *dev){	struct drm_i915_private *dev_priv = dev->dev_private;	int i;	pci_read_config_byte(dev->pdev, LBB, &dev_priv->saveLBB);	mutex_lock(&dev->struct_mutex);	/* Hardware status page */	dev_priv->saveHWS = I915_READ(HWS_PGA);	i915_save_display(dev);	/* Interrupt state */	if (HAS_PCH_SPLIT(dev)) {		dev_priv->saveDEIER = I915_READ(DEIER);		dev_priv->saveDEIMR = I915_READ(DEIMR);		dev_priv->saveGTIER = I915_READ(GTIER);		dev_priv->saveGTIMR = I915_READ(GTIMR);		dev_priv->saveFDI_RXA_IMR = I915_READ(_FDI_RXA_IMR);		dev_priv->saveFDI_RXB_IMR = I915_READ(_FDI_RXB_IMR);		dev_priv->saveMCHBAR_RENDER_STANDBY =			I915_READ(RSTDBYCTL);		dev_priv->savePCH_PORT_HOTPLUG = I915_READ(PCH_PORT_HOTPLUG);	} else {		dev_priv->saveIER = I915_READ(IER);		dev_priv->saveIMR = I915_READ(IMR);	}	if (IS_IRONLAKE_M(dev))		ironlake_disable_drps(dev);	if (IS_GEN6(dev))		gen6_disable_rps(dev);	/* Cache mode state */	dev_priv->saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);	/* Memory Arbitration state */	dev_priv->saveMI_ARB_STATE = I915_READ(MI_ARB_STATE);	/* Scratch space */	for (i = 0; i < 16; i++) {		dev_priv->saveSWF0[i] = I915_READ(SWF00 + (i << 2));		dev_priv->saveSWF1[i] = I915_READ(SWF10 + (i << 2));	}	for (i = 0; i < 3; i++)		dev_priv->saveSWF2[i] = I915_READ(SWF30 + (i << 2));	mutex_unlock(&dev->struct_mutex);	return 0;}

static voidsnb_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb,		 struct drm_i915_gem_object *obj, int crtc_x, int crtc_y,		 unsigned int crtc_w, unsigned int crtc_h,		 uint32_t x, uint32_t y,		 uint32_t src_w, uint32_t src_h){	struct drm_device *dev = plane->dev;	struct drm_i915_private *dev_priv = dev->dev_private;	struct intel_plane *intel_plane = to_intel_plane(plane);	int pipe = intel_plane->pipe, pixel_size;	u32 dvscntr, dvsscale = 0;	dvscntr = I915_READ(DVSCNTR(pipe));	/* Mask out pixel format bits in case we change it */	dvscntr &= ~DVS_PIXFORMAT_MASK;	dvscntr &= ~DVS_RGB_ORDER_XBGR;	dvscntr &= ~DVS_YUV_BYTE_ORDER_MASK;	switch (fb->pixel_format) {	case DRM_FORMAT_XBGR8888:		dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR;		pixel_size = 4;		break;	case DRM_FORMAT_XRGB8888:		dvscntr |= DVS_FORMAT_RGBX888;		pixel_size = 4;		break;	case DRM_FORMAT_YUYV:		dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV;		pixel_size = 2;		break;	case DRM_FORMAT_YVYU:		dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU;		pixel_size = 2;		break;	case DRM_FORMAT_UYVY:		dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY;		pixel_size = 2;		break;	case DRM_FORMAT_VYUY:		dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY;		pixel_size = 2;		break;	default:		DRM_DEBUG_DRIVER("bad pixel format, assuming RGBX888/n");		dvscntr |= DVS_FORMAT_RGBX888;		pixel_size = 4;		break;	}	if (obj->tiling_mode != I915_TILING_NONE)		dvscntr |= DVS_TILED;	/* must disable */	dvscntr |= DVS_TRICKLE_FEED_DISABLE;	dvscntr |= DVS_ENABLE;	/* Sizes are 0 based */	src_w--;	src_h--;	crtc_w--;	crtc_h--;	intel_update_sprite_watermarks(dev, pipe, crtc_w, pixel_size);	if (crtc_w != src_w || crtc_h != src_h)		dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;	I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]);	I915_WRITE(DVSPOS(pipe), (crtc_y << 16) | crtc_x);	if (obj->tiling_mode != I915_TILING_NONE) {		I915_WRITE(DVSTILEOFF(pipe), (y << 16) | x);	} else {		unsigned long offset;		offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);		I915_WRITE(DVSLINOFF(pipe), offset);	}	I915_WRITE(DVSSIZE(pipe), (crtc_h << 16) | crtc_w);	I915_WRITE(DVSSCALE(pipe), dvsscale);	I915_WRITE(DVSCNTR(pipe), dvscntr);	I915_WRITE(DVSSURF(pipe), obj->gtt_offset);	POSTING_READ(DVSSURF(pipe));}

int i915_save_state(struct drm_device *dev){	struct drm_i915_private *dev_priv = dev->dev_private;	int i;	pci_read_config_byte(dev->pdev, LBB, &dev_priv->regfile.saveLBB);	mutex_lock(&dev->struct_mutex);	i915_save_display(dev);	if (!drm_core_check_feature(dev, DRIVER_MODESET)) {		/* Interrupt state */		if (HAS_PCH_SPLIT(dev)) {			dev_priv->regfile.saveDEIER = I915_READ(DEIER);			dev_priv->regfile.saveDEIMR = I915_READ(DEIMR);			dev_priv->regfile.saveGTIER = I915_READ(GTIER);			dev_priv->regfile.saveGTIMR = I915_READ(GTIMR);			dev_priv->regfile.saveFDI_RXA_IMR = I915_READ(_FDI_RXA_IMR);			dev_priv->regfile.saveFDI_RXB_IMR = I915_READ(_FDI_RXB_IMR);			dev_priv->regfile.saveMCHBAR_RENDER_STANDBY =				I915_READ(RSTDBYCTL);			dev_priv->regfile.savePCH_PORT_HOTPLUG = I915_READ(PCH_PORT_HOTPLUG);		} else {			dev_priv->regfile.saveIER = I915_READ(IER);			dev_priv->regfile.saveIMR = I915_READ(IMR);		}	}	intel_disable_gt_powersave(dev);	/* Cache mode state */	dev_priv->regfile.saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);	/* Memory Arbitration state */	dev_priv->regfile.saveMI_ARB_STATE = I915_READ(MI_ARB_STATE);	/* Scratch space */	for (i = 0; i < 16; i++) {		dev_priv->regfile.saveSWF0[i] = I915_READ(SWF00 + (i << 2));		dev_priv->regfile.saveSWF1[i] = I915_READ(SWF10 + (i << 2));	}	for (i = 0; i < 3; i++)		dev_priv->regfile.saveSWF2[i] = I915_READ(SWF30 + (i << 2));	mutex_unlock(&dev->struct_mutex);	return 0;}

static intintel_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,		   struct drm_framebuffer *fb, int crtc_x, int crtc_y,		   unsigned int crtc_w, unsigned int crtc_h,		   uint32_t src_x, uint32_t src_y,		   uint32_t src_w, uint32_t src_h){	struct drm_device *dev = plane->dev;	struct drm_i915_private *dev_priv = dev->dev_private;	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);	struct intel_plane *intel_plane = to_intel_plane(plane);	struct intel_framebuffer *intel_fb;	struct drm_i915_gem_object *obj, *old_obj;	int pipe = intel_plane->pipe;	int ret = 0;	int x = src_x >> 16, y = src_y >> 16;	int primary_w = crtc->mode.hdisplay, primary_h = crtc->mode.vdisplay;	bool disable_primary = false;	intel_fb = to_intel_framebuffer(fb);	obj = intel_fb->obj;	old_obj = intel_plane->obj;	src_w = src_w >> 16;	src_h = src_h >> 16;	/* Pipe must be running... */	if (!(I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE))		return -EINVAL;	if (crtc_x >= primary_w || crtc_y >= primary_h)		return -EINVAL;	/* Don't modify another pipe's plane */	if (intel_plane->pipe != intel_crtc->pipe)		return -EINVAL;	/*	 * Clamp the width & height into the visible area.  Note we don't	 * try to scale the source if part of the visible region is offscreen.	 * The caller must handle that by adjusting source offset and size.	 */	if ((crtc_x < 0) && ((crtc_x + crtc_w) > 0)) {		crtc_w += crtc_x;		crtc_x = 0;	}	if ((crtc_x + crtc_w) <= 0) /* Nothing to display */		goto out;	if ((crtc_x + crtc_w) > primary_w)		crtc_w = primary_w - crtc_x;	if ((crtc_y < 0) && ((crtc_y + crtc_h) > 0)) {		crtc_h += crtc_y;		crtc_y = 0;	}	if ((crtc_y + crtc_h) <= 0) /* Nothing to display */		goto out;	if (crtc_y + crtc_h > primary_h)		crtc_h = primary_h - crtc_y;	if (!crtc_w || !crtc_h) /* Again, nothing to display */		goto out;	/*	 * We can take a larger source and scale it down, but	 * only so much...  16x is the max on SNB.	 */	if (((src_w * src_h) / (crtc_w * crtc_h)) > intel_plane->max_downscale)		return -EINVAL;	/*	 * If the sprite is completely covering the primary plane,	 * we can disable the primary and save power.	 */	if ((crtc_x == 0) && (crtc_y == 0) &&	    (crtc_w == primary_w) && (crtc_h == primary_h))		disable_primary = true;	DRM_LOCK(dev);	ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);	if (ret)		goto out_unlock;	intel_plane->obj = obj;	/*	 * Be sure to re-enable the primary before the sprite is no longer	 * covering it fully.	 */	if (!disable_primary && intel_plane->primary_disabled) {		intel_enable_primary(crtc);		intel_plane->primary_disabled = false;	}	intel_plane->update_plane(plane, fb, obj, crtc_x, crtc_y,				  crtc_w, crtc_h, x, y, src_w, src_h);	if (disable_primary) {//.........这里部分代码省略.........

int i915_save_state(struct drm_device *dev){	struct drm_i915_private *dev_priv = dev->dev_private;	int i;	pci_read_config_byte(dev->pdev, LBB, &dev_priv->saveLBB);	/* Display arbitration control */	dev_priv->saveDSPARB = I915_READ(DSPARB);	/* Pipe & plane A info */	dev_priv->savePIPEACONF = I915_READ(PIPEACONF);	dev_priv->savePIPEASRC = I915_READ(PIPEASRC);	dev_priv->saveFPA0 = I915_READ(FPA0);	dev_priv->saveFPA1 = I915_READ(FPA1);	dev_priv->saveDPLL_A = I915_READ(DPLL_A);	if (IS_I965G(dev))		dev_priv->saveDPLL_A_MD = I915_READ(DPLL_A_MD);	dev_priv->saveHTOTAL_A = I915_READ(HTOTAL_A);	dev_priv->saveHBLANK_A = I915_READ(HBLANK_A);	dev_priv->saveHSYNC_A = I915_READ(HSYNC_A);	dev_priv->saveVTOTAL_A = I915_READ(VTOTAL_A);	dev_priv->saveVBLANK_A = I915_READ(VBLANK_A);	dev_priv->saveVSYNC_A = I915_READ(VSYNC_A);	dev_priv->saveBCLRPAT_A = I915_READ(BCLRPAT_A);	dev_priv->saveDSPACNTR = I915_READ(DSPACNTR);	dev_priv->saveDSPASTRIDE = I915_READ(DSPASTRIDE);	dev_priv->saveDSPASIZE = I915_READ(DSPASIZE);	dev_priv->saveDSPAPOS = I915_READ(DSPAPOS);	dev_priv->saveDSPAADDR = I915_READ(DSPAADDR);	if (IS_I965G(dev)) {		dev_priv->saveDSPASURF = I915_READ(DSPASURF);		dev_priv->saveDSPATILEOFF = I915_READ(DSPATILEOFF);	}	i915_save_palette(dev, PIPE_A);	dev_priv->savePIPEASTAT = I915_READ(PIPEASTAT);	/* Pipe & plane B info */	dev_priv->savePIPEBCONF = I915_READ(PIPEBCONF);	dev_priv->savePIPEBSRC = I915_READ(PIPEBSRC);	dev_priv->saveFPB0 = I915_READ(FPB0);	dev_priv->saveFPB1 = I915_READ(FPB1);	dev_priv->saveDPLL_B = I915_READ(DPLL_B);	if (IS_I965G(dev))		dev_priv->saveDPLL_B_MD = I915_READ(DPLL_B_MD);	dev_priv->saveHTOTAL_B = I915_READ(HTOTAL_B);	dev_priv->saveHBLANK_B = I915_READ(HBLANK_B);	dev_priv->saveHSYNC_B = I915_READ(HSYNC_B);	dev_priv->saveVTOTAL_B = I915_READ(VTOTAL_B);	dev_priv->saveVBLANK_B = I915_READ(VBLANK_B);	dev_priv->saveVSYNC_B = I915_READ(VSYNC_B);	dev_priv->saveBCLRPAT_A = I915_READ(BCLRPAT_A);	dev_priv->saveDSPBCNTR = I915_READ(DSPBCNTR);	dev_priv->saveDSPBSTRIDE = I915_READ(DSPBSTRIDE);	dev_priv->saveDSPBSIZE = I915_READ(DSPBSIZE);	dev_priv->saveDSPBPOS = I915_READ(DSPBPOS);	dev_priv->saveDSPBADDR = I915_READ(DSPBADDR);	if (IS_I965GM(dev) || IS_GM45(dev)) {		dev_priv->saveDSPBSURF = I915_READ(DSPBSURF);		dev_priv->saveDSPBTILEOFF = I915_READ(DSPBTILEOFF);	}	i915_save_palette(dev, PIPE_B);	dev_priv->savePIPEBSTAT = I915_READ(PIPEBSTAT);	/* CRT state */	dev_priv->saveADPA = I915_READ(ADPA);	/* LVDS state */	dev_priv->savePP_CONTROL = I915_READ(PP_CONTROL);	dev_priv->savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS);	dev_priv->saveBLC_PWM_CTL = I915_READ(BLC_PWM_CTL);	if (IS_I965G(dev))		dev_priv->saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2);	if (IS_MOBILE(dev) && !IS_I830(dev))		dev_priv->saveLVDS = I915_READ(LVDS);	if (!IS_I830(dev) && !IS_845G(dev))		dev_priv->savePFIT_CONTROL = I915_READ(PFIT_CONTROL);	dev_priv->savePP_ON_DELAYS = I915_READ(PP_ON_DELAYS);	dev_priv->savePP_OFF_DELAYS = I915_READ(PP_OFF_DELAYS);	dev_priv->savePP_DIVISOR = I915_READ(PP_DIVISOR);	/* FIXME: save TV & SDVO state */	/* FBC state */	dev_priv->saveFBC_CFB_BASE = I915_READ(FBC_CFB_BASE);	dev_priv->saveFBC_LL_BASE = I915_READ(FBC_LL_BASE);	dev_priv->saveFBC_CONTROL2 = I915_READ(FBC_CONTROL2);	dev_priv->saveFBC_CONTROL = I915_READ(FBC_CONTROL);	/* Interrupt state */	dev_priv->saveIIR = I915_READ(IIR);	dev_priv->saveIER = I915_READ(IER);	dev_priv->saveIMR = I915_READ(IMR);	/* VGA state */	dev_priv->saveVGA0 = I915_READ(VGA0);	dev_priv->saveVGA1 = I915_READ(VGA1);	dev_priv->saveVGA_PD = I915_READ(VGA_PD);//.........这里部分代码省略.........

static voidivb_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb,		 struct drm_i915_gem_object *obj, int crtc_x, int crtc_y,		 unsigned int crtc_w, unsigned int crtc_h,		 uint32_t x, uint32_t y,		 uint32_t src_w, uint32_t src_h){	struct drm_device *dev = plane->dev;	struct drm_i915_private *dev_priv = dev->dev_private;	struct intel_plane *intel_plane = to_intel_plane(plane);	int pipe = intel_plane->pipe;	u32 sprctl, sprscale = 0;	int pixel_size;	sprctl = I915_READ(SPRCTL(pipe));	/* Mask out pixel format bits in case we change it */	sprctl &= ~SPRITE_PIXFORMAT_MASK;	sprctl &= ~SPRITE_RGB_ORDER_RGBX;	sprctl &= ~SPRITE_YUV_BYTE_ORDER_MASK;	switch (fb->pixel_format) {	case DRM_FORMAT_XBGR8888:		sprctl |= SPRITE_FORMAT_RGBX888;		pixel_size = 4;		break;	case DRM_FORMAT_XRGB8888:		sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX;		pixel_size = 4;		break;	case DRM_FORMAT_YUYV:		sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV;		pixel_size = 2;		break;	case DRM_FORMAT_YVYU:		sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU;		pixel_size = 2;		break;	case DRM_FORMAT_UYVY:		sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY;		pixel_size = 2;		break;	case DRM_FORMAT_VYUY:		sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY;		pixel_size = 2;		break;	default:		DRM_DEBUG_DRIVER("bad pixel format, assuming RGBX888/n");		sprctl |= DVS_FORMAT_RGBX888;		pixel_size = 4;		break;	}	if (obj->tiling_mode != I915_TILING_NONE)		sprctl |= SPRITE_TILED;	/* must disable */	sprctl |= SPRITE_TRICKLE_FEED_DISABLE;	sprctl |= SPRITE_ENABLE;	/* Sizes are 0 based */	src_w--;	src_h--;	crtc_w--;	crtc_h--;	intel_update_sprite_watermarks(dev, pipe, crtc_w, pixel_size);	/*	 * IVB workaround: must disable low power watermarks for at least	 * one frame before enabling scaling.  LP watermarks can be re-enabled	 * when scaling is disabled.	 */	if (crtc_w != src_w || crtc_h != src_h) {		dev_priv->sprite_scaling_enabled = true;		sandybridge_update_wm(dev);		intel_wait_for_vblank(dev, pipe);		sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;	} else {		dev_priv->sprite_scaling_enabled = false;		/* potentially re-enable LP watermarks */		sandybridge_update_wm(dev);	}	I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]);	I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x);	if (obj->tiling_mode != I915_TILING_NONE) {		I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x);	} else {		unsigned long offset;		offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);		I915_WRITE(SPRLINOFF(pipe), offset);	}	I915_WRITE(SPRSIZE(pipe), (crtc_h << 16) | crtc_w);	I915_WRITE(SPRSCALE(pipe), sprscale);	I915_WRITE(SPRCTL(pipe), sprctl);	I915_WRITE(SPRSURF(pipe), obj->gtt_offset);	POSTING_READ(SPRSURF(pipe));}

int i915_save_state(struct drm_device *dev){	struct drm_i915_private *dev_priv = dev->dev_private;	int i;	pci_read_config_byte(dev->pdev, LBB, &dev_priv->saveLBB);	/* Hardware status page */	dev_priv->saveHWS = I915_READ(HWS_PGA);	i915_save_display(dev);	/* Interrupt state */	if (IS_IRONLAKE(dev)) {		dev_priv->saveDEIER = I915_READ(DEIER);		dev_priv->saveDEIMR = I915_READ(DEIMR);		dev_priv->saveGTIER = I915_READ(GTIER);		dev_priv->saveGTIMR = I915_READ(GTIMR);		dev_priv->saveFDI_RXA_IMR = I915_READ(FDI_RXA_IMR);		dev_priv->saveFDI_RXB_IMR = I915_READ(FDI_RXB_IMR);		dev_priv->saveMCHBAR_RENDER_STANDBY =			I915_READ(MCHBAR_RENDER_STANDBY);	} else {		dev_priv->saveIER = I915_READ(IER);		dev_priv->saveIMR = I915_READ(IMR);	}	if (IS_IRONLAKE_M(dev))		ironlake_disable_drps(dev);	/* Cache mode state */	dev_priv->saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);	/* Memory Arbitration state */	dev_priv->saveMI_ARB_STATE = I915_READ(MI_ARB_STATE);	/* Scratch space */	for (i = 0; i < 16; i++) {		dev_priv->saveSWF0[i] = I915_READ(SWF00 + (i << 2));		dev_priv->saveSWF1[i] = I915_READ(SWF10 + (i << 2));	}	for (i = 0; i < 3; i++)		dev_priv->saveSWF2[i] = I915_READ(SWF30 + (i << 2));	/* Fences */	if (IS_I965G(dev)) {		for (i = 0; i < 16; i++)			dev_priv->saveFENCE[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));	} else {		for (i = 0; i < 8; i++)			dev_priv->saveFENCE[i] = I915_READ(FENCE_REG_830_0 + (i * 4));		if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))			for (i = 0; i < 8; i++)				dev_priv->saveFENCE[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));	}	return 0;}