自学教程：C++ IDS_OPTION_HOOK函数代码示例

/** * *  Find the common supported voltage on all nodes, taken into account of the *  user option for performance and power saving. * *     @param[in,out]   *MemMainPtr   - Pointer to the MEM_MAIN_DATA_BLOCK * *     @return          TRUE -  No fatal error occurs. *     @return          FALSE - Fatal error occurs. */BOOLEANMemMLvDdr3PerformanceEnhPre (  IN OUT   MEM_MAIN_DATA_BLOCK *MemMainPtr  ){  UINT8 Node;  BOOLEAN RetVal;  DIMM_VOLTAGE VDDIO;  MEM_NB_BLOCK *NBPtr;  MEM_PARAMETER_STRUCT *ParameterPtr;  MEM_SHARED_DATA *mmSharedPtr;  PLATFORM_POWER_POLICY PowerPolicy;  NBPtr = MemMainPtr->NBPtr;  mmSharedPtr = MemMainPtr->mmSharedPtr;  ParameterPtr = MemMainPtr->MemPtr->ParameterListPtr;  PowerPolicy = MemMainPtr->MemPtr->PlatFormConfig->PlatformProfile.PlatformPowerPolicy;  IDS_OPTION_HOOK (IDS_MEMORY_POWER_POLICY, &PowerPolicy, &NBPtr->MemPtr->StdHeader);  IDS_HDT_CONSOLE (MEM_FLOW, (PowerPolicy == Performance) ? "/nMaximize Performance/n" : "/nMaximize Battery Life/n");  if (ParameterPtr->DDR3Voltage != VOLT_INITIAL) {    mmSharedPtr->VoltageMap = VDDIO_DETERMINED;    PutEventLog (AGESA_WARNING, MEM_WARNING_INITIAL_DDR3VOLT_NONZERO, 0, 0, 0, 0, &(NBPtr[BSP_DIE].MemPtr->StdHeader));    SetMemError (AGESA_WARNING, NBPtr[BSP_DIE].MCTPtr);    IDS_HDT_CONSOLE (MEM_FLOW, "Warning: Initial Value for VDDIO has been changed./n");    RetVal = TRUE;  } else {    RetVal = MemMLvDdr3 (MemMainPtr);    VDDIO = ParameterPtr->DDR3Voltage;    if (NBPtr->IsSupported[PerformanceOnly] || ((PowerPolicy == Performance) && (mmSharedPtr->VoltageMap != 0))) {      // When there is no commonly supported voltage, do not optimize performance      // For cases where we can maximize performance, do the following      // When VDDIO is enforced, DDR3Voltage will be overriden by specific VDDIO      // So cases with DDR3Voltage left to be VOLT_UNSUPPORTED will be open to maximizing performance.      ParameterPtr->DDR3Voltage = VOLT_UNSUPPORTED;    }    IDS_OPTION_HOOK (IDS_ENFORCE_VDDIO, &(ParameterPtr->DDR3Voltage), &NBPtr->MemPtr->StdHeader);    if (ParameterPtr->DDR3Voltage != VOLT_UNSUPPORTED) {      // When Voltage is already determined, do not have further process to choose maximum frequency to optimize performance      mmSharedPtr->VoltageMap = VDDIO_DETERMINED;      IDS_HDT_CONSOLE (MEM_FLOW, "VDDIO is determined. No further optimization will be done./n");    } else {      for (Node = 0; Node < MemMainPtr->DieCount; Node++) {        NBPtr[Node].MaxFreqVDDIO[VOLT1_5_ENCODED_VAL] = UNSUPPORTED_DDR_FREQUENCY;        NBPtr[Node].MaxFreqVDDIO[VOLT1_35_ENCODED_VAL] = UNSUPPORTED_DDR_FREQUENCY;        NBPtr[Node].MaxFreqVDDIO[VOLT1_25_ENCODED_VAL] = UNSUPPORTED_DDR_FREQUENCY;      }      // Reprogram the leveling result as temporal candidate      ParameterPtr->DDR3Voltage = VDDIO;    }  }  ASSERT (ParameterPtr->DDR3Voltage != VOLT_UNSUPPORTED);  return RetVal;}

/** * Main entry point for the AMD_S3LATE_RESTORE function. * * This entry point is responsible for restoring saved registers and preparing the * silicon components for OS restart. * * @param[in,out] S3LateParams   Required input parameters for the AMD_S3LATE_RESTORE *                                  entry point. * * @return        Aggregated status across all internal AMD S3 late restore calls invoked. * */AGESA_STATUSAmdS3LateRestore (  IN OUT   AMD_S3LATE_PARAMS *S3LateParams  ){  UINT8  *BufferPointer;  VOID   *OrMaskPtr;  VOID   *LateContextPtr;  AGESA_STATUS ReturnStatus;  AGESA_STATUS CalledStatus;  AGESA_TESTPOINT (TpIfAmdS3LateRestoreEntry, &S3LateParams->StdHeader);  IDS_HDT_CONSOLE (MAIN_FLOW, "AmdS3LateRestore: Start/n/n");  ReturnStatus = AGESA_SUCCESS;  ASSERT (S3LateParams != NULL);  BufferPointer = (UINT8 *) S3LateParams->S3DataBlock.VolatileStorage;  S3LateParams->StdHeader.HeapBasePtr = &BufferPointer[((S3_VOLATILE_STORAGE_HEADER *) S3LateParams->S3DataBlock.VolatileStorage)->HeapOffset];  ASSERT (S3LateParams->StdHeader.HeapBasePtr != NULL);  IDS_OPTION_HOOK (IDS_PLATFORMCFG_OVERRIDE, &S3LateParams->PlatformConfig, &S3LateParams->StdHeader);  IDS_OPTION_HOOK (IDS_BEFORE_S3_RESTORE, S3LateParams, &(S3LateParams->StdHeader));  if (((S3_VOLATILE_STORAGE_HEADER *) S3LateParams->S3DataBlock.VolatileStorage)->RegisterDataSize != 0) {    LateContextPtr = &BufferPointer[((S3_VOLATILE_STORAGE_HEADER *) S3LateParams->S3DataBlock.VolatileStorage)->RegisterDataOffset];    // Restore registers before exiting self refresh    RestorePreESRContext (&OrMaskPtr,                          LateContextPtr,                          S3_LATE_RESTORE,                          &S3LateParams->StdHeader);    // Restore registers after exiting self refresh    RestorePostESRContext (OrMaskPtr,                           LateContextPtr,                           S3_LATE_RESTORE,                           &S3LateParams->StdHeader);  }  // Dispatch any features needing to run at this time point  IDS_HDT_CONSOLE (CPU_TRACE, "  Dispatch CPU features at S3 late restore end/n");  CalledStatus = DispatchCpuFeatures (CPU_FEAT_S3_LATE_RESTORE_END,                                      &S3LateParams->PlatformConfig,                                      &S3LateParams->StdHeader);  if (CalledStatus > ReturnStatus) {    ReturnStatus = CalledStatus;  }  CalledStatus = S3ScriptRestore (&S3LateParams->StdHeader);  if (CalledStatus > ReturnStatus) {    ReturnStatus = CalledStatus;  }  IDS_OPTION_HOOK (IDS_AFTER_S3_RESTORE, S3LateParams, &S3LateParams->StdHeader);  AGESA_TESTPOINT (TpIfAmdS3LateRestoreExit, &S3LateParams->StdHeader);  IDS_HDT_CONSOLE (MAIN_FLOW, "/nAmdS3LateRestore: End/n/n");  IDS_HDT_CONSOLE_S3_EXIT (&S3LateParams->StdHeader);  return  ReturnStatus;}

/** * Main entry point for the AMD_INIT_ENV function. * * This entry point is responsible for copying the heap contents from the * temp RAM area to main memory. * * @param[in,out] EnvParams         Required input parameters for the AMD_INIT_ENV *                                  entry point. * * @return        Aggregated status across all internal AMD env calls invoked. * */AGESA_STATUSAmdInitEnv (  IN OUT   AMD_ENV_PARAMS  *EnvParams  ){  AGESA_STATUS  AgesaStatus;  AGESA_STATUS  AmdInitEnvStatus;  AGESA_TESTPOINT (TpIfAmdInitEnvEntry, &EnvParams->StdHeader);  ASSERT (EnvParams != NULL);  AmdInitEnvStatus = AGESA_SUCCESS;  //Copy Temp Ram heap content to Main Ram  AgesaStatus = CopyHeapToMainRamAtPost (&(EnvParams->StdHeader));  if (AgesaStatus > AmdInitEnvStatus) {    AmdInitEnvStatus = AgesaStatus;  }  EnvParams->StdHeader.HeapStatus = HEAP_SYSTEM_MEM;  EnvParams->StdHeader.HeapBasePtr = HeapGetBaseAddress (&EnvParams->StdHeader);  // Any heap allocate/deallocate/locate buffer should be used after heap is rebuilt from here.  // After persistent heaps are transferred and rebuilt, HeapLocateBuffer can start to be used in IDS hook.  //Heap have been relocated, so Debug Print need be init again to get new address  IDS_PERF_TIMESTAMP (TP_BEGINPROCAMDINITENV, &EnvParams->StdHeader);  IDS_HDT_CONSOLE_INIT (&EnvParams->StdHeader);  IDS_HDT_CONSOLE (MAIN_FLOW, "Heap transfer End/n");  IDS_HDT_CONSOLE (MAIN_FLOW, "AmdInitEnv: Start/n/n");  IDS_OPTION_HOOK (IDS_PLATFORMCFG_OVERRIDE, &EnvParams->PlatformConfig, &(EnvParams->StdHeader));  IDS_OPTION_HOOK (IDS_BEFORE_PCI_INIT, EnvParams, &(EnvParams->StdHeader));  AgesaStatus = S3ScriptInit (&EnvParams->StdHeader);  if (AgesaStatus > AmdInitEnvStatus) {    AmdInitEnvStatus = AgesaStatus;  }  IDS_PERF_TIMESTAMP (TP_BEGININITENV, &EnvParams->StdHeader);  AgesaStatus = BldoptFchFunction.InitEnv (EnvParams);  AmdInitEnvStatus = (AgesaStatus > AmdInitEnvStatus) ? AgesaStatus : AmdInitEnvStatus;  IDS_PERF_TIMESTAMP (TP_ENDINITENV, &EnvParams->StdHeader);  IDS_PERF_TIMESTAMP (TP_BEGINGNBINITATENV, &EnvParams->StdHeader);  AgesaStatus = GnbInitAtEnv (EnvParams);  if (AgesaStatus > AmdInitEnvStatus) {    AmdInitEnvStatus = AgesaStatus;  }  IDS_PERF_TIMESTAMP (TP_ENDGNBINITATENV, &EnvParams->StdHeader);  AGESA_TESTPOINT (TpIfAmdInitEnvExit, &EnvParams->StdHeader);  IDS_HDT_CONSOLE (MAIN_FLOW, "/nAmdInitEnv: End/n");  IDS_PERF_TIMESTAMP (TP_ENDPROCAMDINITENV, &EnvParams->StdHeader);  IDS_HDT_CONSOLE_FLUSH_BUFFER (&EnvParams->StdHeader);  return  AmdInitEnvStatus;}

/** * *  Find the common supported voltage on all nodes, taken into account of the *  user option for performance and power saving. * *     @param[in,out]   *MemMainPtr   - Pointer to the MEM_MAIN_DATA_BLOCK * *     @return          TRUE -  No fatal error occurs. *     @return          FALSE - Fatal error occurs. */BOOLEANMemMLvDdr3PerformanceEnhPre (  IN OUT   MEM_MAIN_DATA_BLOCK *MemMainPtr  ){  UINT8 Node;  BOOLEAN RetVal;  DIMM_VOLTAGE VDDIO;  MEM_NB_BLOCK *NBPtr;  MEM_PARAMETER_STRUCT *ParameterPtr;  MEM_SHARED_DATA *mmSharedPtr;  PLATFORM_POWER_POLICY PowerPolicy;  NBPtr = MemMainPtr->NBPtr;  mmSharedPtr = MemMainPtr->mmSharedPtr;  ParameterPtr = MemMainPtr->MemPtr->ParameterListPtr;  PowerPolicy = MemMainPtr->MemPtr->PlatFormConfig->PlatformProfile.PlatformPowerPolicy;  IDS_OPTION_HOOK (IDS_SKIP_PERFORMANCE_OPT, &PowerPolicy, &NBPtr->MemPtr->StdHeader);  IDS_HDT_CONSOLE (MEM_STATUS, (PowerPolicy == Performance) ? "Maximize Performance/n" : "Maximize Battery Life/n");  RetVal = MemMLvDdr3 (MemMainPtr);  VDDIO = ParameterPtr->DDR3Voltage;  ParameterPtr->DDR3Voltage = VOLT_UNSUPPORTED;  if (mmSharedPtr->VoltageMap == 0) {    // When there is no commonly supported voltage, do not optimize performance    mmSharedPtr->VoltageMap = VDDIO_DETERMINED;  } else if (PowerPolicy == BatteryLife) {    ParameterPtr->DDR3Voltage = VDDIO;  }  IDS_OPTION_HOOK (IDS_ENFORCE_VDDIO, &(ParameterPtr->DDR3Voltage), &NBPtr->MemPtr->StdHeader);  if (ParameterPtr->DDR3Voltage != VOLT_UNSUPPORTED) {    // When Voltage is already determined, do not have further process to choose maximum frequency to optimize performance    mmSharedPtr->VoltageMap = VDDIO_DETERMINED;    IDS_HDT_CONSOLE (MEM_STATUS, "VDDIO is determined. No further optimization will be done./n");  } else {    for (Node = 0; Node < MemMainPtr->DieCount; Node++) {      NBPtr[Node].MaxFreqVDDIO[VOLT1_5] = UNSUPPORTED_DDR_FREQUENCY;      NBPtr[Node].MaxFreqVDDIO[VOLT1_35] = UNSUPPORTED_DDR_FREQUENCY;      NBPtr[Node].MaxFreqVDDIO[VOLT1_25] = UNSUPPORTED_DDR_FREQUENCY;    }  }  // Reprogram the leveling result  ParameterPtr->DDR3Voltage = VDDIO;  return RetVal;}

/** * Entry point for enabling Hardware Thermal Control * * This function must be run after all P-State routines have been executed * * @param[in]  HtcServices             The current CPU's family services. * @param[in]  EntryPoint              Timepoint designator. * @param[in]  PlatformConfig          Platform profile/build option config structure. * @param[in]  StdHeader               Config handle for library and services. * * @retval     AGESA_SUCCESS           Always succeeds. * */AGESA_STATUSSTATICF15KvInitializeHtc (  IN       HTC_FAMILY_SERVICES    *HtcServices,  IN       UINT64                  EntryPoint,  IN       PLATFORM_CONFIGURATION *PlatformConfig,  IN       AMD_CONFIG_PARAMS      *StdHeader  ){  UINT32    LocalPciRegister;  PCI_ADDR  PciAddress;  if ((EntryPoint & (CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC)) != 0) {    PciAddress.AddressValue = NB_CAPS_PCI_ADDR;    LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);    if (((NB_CAPS_REGISTER *) &LocalPciRegister)->HtcCapable == 1) {      // Enable HTC      PciAddress.Address.Register = HTC_REG;      LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);      if (((HTC_REGISTER *) &LocalPciRegister)->HtcTmpLmt != 0) {        // Enable HTC        ((HTC_REGISTER *) &LocalPciRegister)->HtcEn = 1;      } else {        // Disable HTC        ((HTC_REGISTER *) &LocalPciRegister)->HtcEn = 0;      }      IDS_OPTION_HOOK (IDS_HTC_CTRL, &LocalPciRegister, StdHeader);      LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);    }  }  return AGESA_SUCCESS;}

/** * BSC entry point for for enabling Core Performance Boost. * * Set up D18F4x15C[BoostSrc] and start the PDMs according to the BKDG. * * @param[in]  CpbServices             The current CPU's family services. * @param[in]  PlatformConfig          Contains the runtime modifiable feature input data. * @param[in]  EntryPoint              Current CPU feature dispatch point. * @param[in]  Socket                  Zero based socket number to check. * @param[in]  StdHeader               Config handle for library and services. * * @retval     AGESA_SUCCESS           Always succeeds. * */AGESA_STATUSSTATICF12InitializeCpb (  IN       CPB_FAMILY_SERVICES    *CpbServices,  IN       PLATFORM_CONFIGURATION *PlatformConfig,  IN       UINT64                 EntryPoint,  IN       UINT32                 Socket,  IN       AMD_CONFIG_PARAMS      *StdHeader  ){  PCI_ADDR             PciAddress;  D18F4x15C_STRUCT     CpbControl;  SMUx0B_x8580_STRUCT  SMUx0Bx8580;  if ((EntryPoint & CPU_FEAT_BEFORE_PM_INIT) != 0) {//    F12EarlySampleCpbSupport.F12CpbInitHook (StdHeader);    PciAddress.AddressValue = CPB_CTRL_PCI_ADDR;    LibAmdPciRead (AccessWidth32, PciAddress, &CpbControl.Value, StdHeader);    CpbControl.Field.BoostSrc = 1;    IDS_OPTION_HOOK (IDS_CPB_CTRL, &CpbControl.Value, StdHeader);    LibAmdPciWrite (AccessWidth32, PciAddress, &CpbControl.Value, StdHeader);  } else if ((EntryPoint & CPU_FEAT_INIT_LATE_END) != 0) {    // Ensure that the recommended settings have been programmed into SMUx0B_x8580, then    // interrupt the SMU with service index 12h.    SMUx0Bx8580.Value = 0;    SMUx0Bx8580.Field.PdmPeriod = 0x1388;    SMUx0Bx8580.Field.PdmUnit = 1;    SMUx0Bx8580.Field.PdmCacEn = 1;    SMUx0Bx8580.Field.PdmEn = 1;    NbSmuRcuRegisterWrite (SMUx0B_x8580_ADDRESS, &SMUx0Bx8580.Value, 1, TRUE, StdHeader);    NbSmuServiceRequest (0x12, TRUE, StdHeader);  }  return AGESA_SUCCESS;}

/** *    Enable DA-C Cpu Cache Flush On Halt Function * *    @param[in]       FamilySpecificServices   The current Family Specific Services. *    @param[in]       EntryPoint               Timepoint designator. *    @param[in]       PlatformConfig           Contains the runtime modifiable feature input data. *    @param[in]       StdHeader                Config Handle for library, services. */VOIDSetF10DaCacheFlushOnHaltRegister (  IN       CPU_CFOH_FAMILY_SERVICES     *FamilySpecificServices,  IN       UINT64                       EntryPoint,  IN       PLATFORM_CONFIGURATION       *PlatformConfig,  IN       AMD_CONFIG_PARAMS            *StdHeader  ){  UINT32       CoreCount;  UINT32       AndMask;  UINT32       OrMask;  PCI_ADDR     PciAddress;  CPU_LOGICAL_ID LogicalId;  if ((EntryPoint & CPU_FEAT_AFTER_POST_MTRR_SYNC) != 0) {    // F3xDC[25:19] = 04h    // F3xDC[18:16] = 111b    PciAddress.Address.Function = FUNC_3;    PciAddress.Address.Register = CLOCK_POWER_TIMING_CTRL2_REG;    AndMask = 0xFC00FFFF;    OrMask = 0x00270000;    GetLogicalIdOfCurrentCore (&LogicalId, StdHeader);    if (LogicalId.Revision == AMD_F10_DA_C2) {      //For DA_C2 single Core, F3xDC[18:16] = 0      GetActiveCoresInCurrentSocket (&CoreCount, StdHeader);      if (CoreCount == 1) {        OrMask = 0x00200000;      }    }    IDS_OPTION_HOOK (IDS_CACHE_FLUSH_HLT, &OrMask, StdHeader);    OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F3xDC  }}

/** *  Should Low Power P-state be enabled *  If all processors support Low Power P-state, reture TRUE, otherwise reture FALSE * * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data. * @param[in]    StdHeader          Config Handle for library, services. * * @retval       TRUE               Low Power P-state is supported. * @retval       FALSE              Low Power P-state cannot be enabled. * */BOOLEANSTATICIsLowPwrPstateFeatureSupported (  IN       PLATFORM_CONFIGURATION *PlatformConfig,  IN       AMD_CONFIG_PARAMS      *StdHeader  ){  UINT32              Socket;  BOOLEAN             IsSupported;  LOW_PWR_PSTATE_FAMILY_SERVICES *FamilyServices;  IsSupported = FALSE;  for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {    if (IsProcessorPresent (Socket, StdHeader)) {      GetFeatureServicesOfSocket (&LowPwrPstateFamilyServiceTable, Socket, (const VOID **)&FamilyServices, StdHeader);      if (FamilyServices != NULL) {        if (FamilyServices->IsLowPwrPstateSupported (FamilyServices, PlatformConfig, Socket, StdHeader)) {          IsSupported = TRUE;        } else {          IsSupported = FALSE;          break;        }      } else {        IsSupported = FALSE;        break;      }    }  }  IDS_OPTION_HOOK (IDS_LOW_POWER_PSTATE, &IsSupported, StdHeader);  return IsSupported;}

VOIDNbInitClockGating (  IN      GNB_PLATFORM_CONFIG *Gnb  ){  NB_CLK_GATING_CTRL NbClkGatingCtrl;  //Init the default value of control structure.  NbClkGatingCtrl.Smu_Sclk_Gating = GnbBuildOptions.SmuSclkClockGatingEnable;  NbClkGatingCtrl.Smu_Lclk_Gating = TRUE;  NbClkGatingCtrl.Orb_Sclk_Gating = TRUE;  NbClkGatingCtrl.Orb_Lclk_Gating = TRUE;  NbClkGatingCtrl.Ioc_Sclk_Gating = TRUE;  NbClkGatingCtrl.Ioc_Lclk_Gating = TRUE;  NbClkGatingCtrl.Bif_Sclk_Gating = TRUE;  NbClkGatingCtrl.Gmc_Sclk_Gating = TRUE;  NbClkGatingCtrl.Dce_Sclk_Gating = TRUE;  NbClkGatingCtrl.Dce_Dispclk_Gating = TRUE;  NbFmNbClockGating (&NbClkGatingCtrl, Gnb->StdHeader);  IDS_OPTION_HOOK (IDS_GNB_CLOCK_GATING, &NbClkGatingCtrl, Gnb->StdHeader);  IDS_HDT_CONSOLE (GNB_TRACE, "NbInitClockGating Enter/n");//SMU SCLK/LCLK clock gating  NbInitSmuClockGating (&NbClkGatingCtrl, Gnb);// ORB clock gating  NbInitOrbClockGating (&NbClkGatingCtrl, Gnb);//IOC clock gating  NbInitIocClockGating (&NbClkGatingCtrl, Gnb);//BIF Clock Gating  NbInitBifClockGating (&NbClkGatingCtrl, Gnb);//GMC Clock Gating  NbInitGmcClockGating (&NbClkGatingCtrl, Gnb);//DCE Sclk clock gating  NbInitDceSclkClockGating (&NbClkGatingCtrl, Gnb);//DCE Display clock gating  NbInitDceDisplayClockGating (&NbClkGatingCtrl, Gnb);  GNB_DEBUG_CODE (    {      FCRxFF30_01F4_STRUCT  FCRxFF30_01F4;      FCRxFF30_01F5_STRUCT  FCRxFF30_01F5;      FCRxFF30_1512_STRUCT  FCRxFF30_1512;      NbSmuSrbmRegisterRead (FCRxFF30_01F4_ADDRESS, &FCRxFF30_01F4.Value, Gnb->StdHeader);      NbSmuSrbmRegisterRead (FCRxFF30_01F5_ADDRESS, &FCRxFF30_01F5.Value, Gnb->StdHeader);      NbSmuSrbmRegisterRead (FCRxFF30_1512_ADDRESS, &FCRxFF30_1512.Value, Gnb->StdHeader);      IDS_HDT_CONSOLE (NB_MISC, "   Clock Gating FCRxFF30_01F4 - 0x%x/n", FCRxFF30_01F4.Value);      IDS_HDT_CONSOLE (NB_MISC, "   Clock Gating FCRxFF30_01F5 - 0x%x/n", FCRxFF30_01F5.Value);      IDS_HDT_CONSOLE (NB_MISC, "   Clock Gating FCRxFF30_1512 - 0x%x/n", FCRxFF30_1512.Value);    }    );

/** *    Enable Cpu Cache Flush On Halt Function * *    @param[in]       FamilySpecificServices   The current Family Specific Services. *    @param[in]       EntryPoint               Timepoint designator. *    @param[in]       PlatformConfig           Contains the runtime modifiable feature input data. *    @param[in]       StdHeader                Config Handle for library, services. */VOIDSetF16KbCacheFlushOnHaltRegister (  IN       CPU_CFOH_FAMILY_SERVICES     *FamilySpecificServices,  IN       UINT64                       EntryPoint,  IN       PLATFORM_CONFIGURATION       *PlatformConfig,  IN       AMD_CONFIG_PARAMS            *StdHeader  ){  PCI_ADDR                              PciAddress;  CSTATE_CTRL1_REGISTER                 CstateCtrl1;  if ((EntryPoint & (CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC)) != 0) {    // Set F4x118    PciAddress.AddressValue = CSTATE_CTRL1_PCI_ADDR;    LibAmdPciRead (AccessWidth32, PciAddress, &CstateCtrl1, StdHeader);    // Set C-state Action Field 0    // bits[11]      NbClkGate0          = 0x1    // bits[12]      SelfRefr0           = 0x1    CstateCtrl1.NbClkGate0 = 1;    CstateCtrl1.SelfRefr0 = 1;    // Set C-state Action Field 1    // bits[27]      NbClkGate1          = 0x1    // bits[28]      SelfRefr1           = 0x1    CstateCtrl1.NbClkGate1 = 1;    CstateCtrl1.SelfRefr1 = 1;    LibAmdPciWrite (AccessWidth32, PciAddress, &CstateCtrl1, StdHeader);    //Override the default setting    IDS_OPTION_HOOK (IDS_CACHE_FLUSH_HLT, NULL, StdHeader);  }}

/** * Dispatches all features needing to perform some initialization at * this time point. * * This routine searches the feature table for features needing to * run at this time point, and invokes them. * * @param[in]      EntryPoint     Timepoint designator * @param[in]      PlatformConfig Contains the runtime modifiable feature input data. * @param[in]      StdHeader      Standard AMD configuration parameters. * * @return         The most severe status of any called service. */AGESA_STATUSDispatchCpuFeatures (  IN       UINT64                 EntryPoint,  IN       PLATFORM_CONFIGURATION *PlatformConfig,  IN       AMD_CONFIG_PARAMS      *StdHeader  ){  UINTN i;  AGESA_STATUS AgesaStatus;  AGESA_STATUS CalledStatus;  AGESA_STATUS IgnoredStatus;  AgesaStatus = AGESA_SUCCESS;  IDS_OPTION_HOOK (IDS_PLATFORMCFG_OVERRIDE, PlatformConfig, StdHeader);  if (IsBsp (StdHeader, &IgnoredStatus)) {    for (i = 0; SupportedCpuFeatureList[i] != NULL; i++) {      if ((SupportedCpuFeatureList[i]->EntryPoint & EntryPoint) != 0) {        if (SupportedCpuFeatureList[i]->IsEnabled (PlatformConfig, StdHeader)) {          CalledStatus = SupportedCpuFeatureList[i]->InitializeFeature (EntryPoint, PlatformConfig, StdHeader);          if (CalledStatus > AgesaStatus) {            AgesaStatus = CalledStatus;          }        }      }    }  }  return AgesaStatus;}

/** * PCIe Post Init * * * * @param[in]  StdHeader  Standard configuration header * @retval     AGESA_STATUS */AGESA_STATUSPciePostEarlyInterfaceML (  IN      AMD_CONFIG_PARAMS               *StdHeader  ){  AGESA_STATUS          AgesaStatus;  AGESA_STATUS          Status;  PCIe_PLATFORM_CONFIG  *Pcie;  IDS_HDT_CONSOLE (GNB_TRACE, "PciePostEarlyInterfaceML Enter/n");  AgesaStatus = AGESA_SUCCESS;  Status = PcieLocateConfigurationData (StdHeader, &Pcie);  IDS_OPTION_HOOK (IDS_BEFORE_GPP_TRAINING, Pcie, StdHeader);  AGESA_STATUS_UPDATE (Status, AgesaStatus);  if (Status == AGESA_SUCCESS) {    PciePortsVisibilityControlV5 (UnhidePorts, Pcie);    Status = PciePostEarlyPortInitML (Pcie);    AGESA_STATUS_UPDATE (Status, AgesaStatus);    ASSERT (Status == AGESA_SUCCESS);    Status = PcieTrainingV2 (Pcie);    AGESA_STATUS_UPDATE (Status, AgesaStatus);    ASSERT (Status == AGESA_SUCCESS);    PciePortsVisibilityControlV5 (HidePorts, Pcie);  }  IDS_HDT_CONSOLE (GNB_TRACE, "PciePostEarlyInterfaceML Exit [0x%x]/n", AgesaStatus);  return  AgesaStatus;}

/** * * *   Initiates/synchronizes memory clear on all nodes with Dram on it. * *     @param[in,out]   *MemMainPtr   - Pointer to the MEM_MAIN_DATA_BLOCK * *     @return          TRUE -  No fatal error occurs. *     @return          FALSE - Fatal error occurs. */BOOLEANMemMMctMemClr (  IN OUT   MEM_MAIN_DATA_BLOCK *MemMainPtr  ){  UINT8   Node;  UINT8   NodeCnt;  BOOLEAN RetVal;  MEM_NB_BLOCK  *NBPtr;  NBPtr = MemMainPtr->NBPtr;  NodeCnt = MemMainPtr->DieCount;  RetVal = TRUE;  IDS_OPTION_HOOK (IDS_BEFORE_MEMCLR, NULL, &NBPtr->MemPtr->StdHeader);  for (Node = 0; Node < NodeCnt; Node++) {    NBPtr->FamilySpecificHook[DisableMemHoleMapping] (&NBPtr[Node], NULL);  }  for (Node = 0; Node < NodeCnt; Node++) {    MemFMctMemClr_Init (&NBPtr[Node]);  }  for (Node = 0; Node < NodeCnt; Node++) {    MemFMctMemClr_Sync (&NBPtr[Node]);    RetVal &= (BOOLEAN) (NBPtr[Node].MCTPtr->ErrCode < AGESA_FATAL);  }  for (Node = 0; Node < NodeCnt; Node++) {    NBPtr->FamilySpecificHook[RestoreMemHoleMapping] (&NBPtr[Node], NULL);  }  return RetVal;}

AGESA_STATUSGnbSmuFirmwareLoadV4 (  IN       PCI_ADDR                 GnbPciAddress,  IN       FIRMWARE_HEADER_V4       *Firmware,  IN       AMD_CONFIG_PARAMS        *StdHeader  ){  UINT32                     Index;  D0F0xBC_xE00030A4_STRUCT  D0F0xBC_xE00030A4;  D0F0xBC_xE0000004_STRUCT  D0F0xBC_xE0000004;  D0F0xBC_xE0003088_STRUCT  D0F0xBC_xE0003088;  D0F0xBC_x80010000_STRUCT  D0F0xBC_x80010000;  D0F0xBC_x1F380_STRUCT      D0F0xBC_x1F380;  IDS_HDT_CONSOLE (GNB_TRACE, "GnbSmuFirmwareLoadV4 Enter/n");  IDS_HDT_CONSOLE (NB_MISC, "  Firmware version 0x%x/n", Firmware->Version);  IDS_OPTION_HOOK (IDS_REPORT_SMU_FW_VERSION, &(Firmware->Version), StdHeader);  // Step 2, 10, make sure Rom firmware sequence is done  do {    GnbLibPciIndirectRead (GnbPciAddress.AddressValue | D0F0xB8_ADDRESS, D0F0xBC_xE0000004_ADDRESS, AccessWidth32, &D0F0xBC_xE0000004.Value, StdHeader);  } while (D0F0xBC_xE0000004.Field.boot_seq_done == 0);  // Step 1, check if firmware running in protected mode  GnbLibPciIndirectRead (GnbPciAddress.AddressValue | D0F0xB8_ADDRESS, D0F0xBC_xE00030A4_ADDRESS, AccessWidth32, &D0F0xBC_xE00030A4.Value, StdHeader);  if (D0F0xBC_xE00030A4.Field.SmuProtectedMode == 0) {    // Step3, Clear firmware interrupt flags    GnbLibPciIndirectRMW (      GnbPciAddress.AddressValue | D0F0xB8_ADDRESS,      D0F0xBC_x1F380_ADDRESS,      AccessWidth32,      0x0,      0x0,      StdHeader      );  }  //Step 4, 11, Assert LM32 reset  GnbLibPciIndirectRMW (    GnbPciAddress.AddressValue | D0F0xB8_ADDRESS,    D0F0xBC_x80000000_ADDRESS,    AccessWidth32,    (UINT32) ~(D0F0xBC_x80000000_lm32_rst_reg_MASK),    1 << D0F0xBC_x80000000_lm32_rst_reg_OFFSET,    StdHeader    );  // Step5, 12, Load firmware  for (Index = 0; Index < (Firmware->FirmwareLength + Firmware->HeaderLength); Index++) {    GnbLibPciIndirectWrite (GnbPciAddress.AddressValue | D0F0xB8_ADDRESS, SMC_RAM_START_ADDR + (Index * 4), AccessWidth32, &((UINT32 *) Firmware)[Index], StdHeader);  }  if (D0F0xBC_xE00030A4.Field.SmuProtectedMode == 0) {    //Step 6, Write jmp to RAM firmware    GnbLibPciIndirectRMW (      GnbPciAddress.AddressValue | D0F0xB8_ADDRESS,      0x0,      AccessWidth32,      0x0,      0xE0000000 + ((SMC_RAM_START_ADDR + Firmware->HeaderLength * 4) >> 2),      StdHeader      );  } else {

/** *    Main entry point for initializing the Thermal Control *    safety net feature. * *    This must be run by all Family 16h Kabini core 0s in the system. * * @param[in]  HtcServices             The current CPU's family services. * @param[in]  EntryPoint              Timepoint designator. * @param[in]  PlatformConfig          Platform profile/build option config structure. * @param[in]  StdHeader               Config handle for library and services. * * @retval     AGESA_SUCCESS           Always succeeds. * */AGESA_STATUSSTATICF16KbInitializeHtc (  IN       HTC_FAMILY_SERVICES    *HtcServices,  IN       UINT64                  EntryPoint,  IN       PLATFORM_CONFIGURATION *PlatformConfig,  IN       AMD_CONFIG_PARAMS      *StdHeader  ){  UINT32                         HtcTempLimit;  NB_CAPS_REGISTER               NbCaps;  HTC_REGISTER                   HtcReg;  CLK_PWR_TIMING_CTRL2_REGISTER  Cptc2;  POPUP_PSTATE_REGISTER          PopUpPstate;  PCI_ADDR                       PciAddress;  UINT32                         D0F0xBC_xC0107097;  if ((EntryPoint & (CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC)) != 0) {    PciAddress.AddressValue = NB_CAPS_PCI_ADDR;    LibAmdPciRead (AccessWidth32, PciAddress, &NbCaps, StdHeader);    if (NbCaps.HtcCapable == 1) {      // Enable HTC      PciAddress.Address.Register = HTC_REG;      LibAmdPciRead (AccessWidth32, PciAddress, &HtcReg, StdHeader);      GnbRegisterReadKB (GnbGetHandle (StdHeader), 0x4, 0xC0107097, &D0F0xBC_xC0107097, 0, StdHeader);      HtcReg.HtcTmpLmt = (D0F0xBC_xC0107097 >> 3) & 0x7F;      if (HtcReg.HtcTmpLmt != 0) {        // Enable HTC        HtcReg.HtcEn = 1;        PciAddress.Address.Register = CPTC2_REG;        LibAmdPciRead (AccessWidth32, PciAddress, &Cptc2, StdHeader);        if (HtcReg.HtcPstateLimit > Cptc2.HwPstateMaxVal) {          // F3xDC[HwPstateMaxVal] = F3x64[HtcPstateLimit]          Cptc2.HwPstateMaxVal = HtcReg.HtcPstateLimit;          LibAmdPciWrite (AccessWidth32, PciAddress, &Cptc2, StdHeader);          // F3xA8[PopDownPstate] = F3xDC[HwPstateMaxVal]          PciAddress.Address.Register = POPUP_PSTATE_REG;          LibAmdPciRead (AccessWidth32, PciAddress, &PopUpPstate, StdHeader);          PopUpPstate.PopDownPstate = Cptc2.HwPstateMaxVal;          LibAmdPciWrite (AccessWidth32, PciAddress, &PopUpPstate, StdHeader);        }        if ((PlatformConfig->HtcTemperatureLimit >= 520) && (PlatformConfig->LhtcTemperatureLimit != 0)) {          HtcTempLimit = ((PlatformConfig->HtcTemperatureLimit - 520) / 5);          if (HtcTempLimit < HtcReg.HtcTmpLmt) {            HtcReg.HtcTmpLmt = HtcTempLimit;          }        }      } else {        // Disable HTC        HtcReg.HtcEn = 0;      }      PciAddress.Address.Register = HTC_REG;      IDS_OPTION_HOOK (IDS_HTC_CTRL, &HtcReg, StdHeader);      LibAmdPciWrite (AccessWidth32, PciAddress, &HtcReg, StdHeader);    }

/** * *  InitializeCacheFlushOnHaltFeature * *    CPU feature leveling. Enable Cpu Cache Flush On Halt Function * *    @param[in]       EntryPoint       Timepoint designator. *    @param[in]       PlatformConfig   Contains the runtime modifiable feature input data. *    @param[in,out]   StdHeader        Pointer to AMD_CONFIG_PARAMS struct. * *    @return          The most severe status of any family specific service. */STATIC AGESA_STATUSInitializeCacheFlushOnHaltFeature (  IN       UINT64                 EntryPoint,  IN       PLATFORM_CONFIGURATION *PlatformConfig,  IN OUT   AMD_CONFIG_PARAMS      *StdHeader  ){  UINT32 Socket;  UINT32 Module;  UINT32 AndMask;  UINT32 OrMask;  UINT32 PciRegister;  PCI_ADDR PciAddress;  PCI_ADDR CfohPciAddress;  AGESA_STATUS AgesaStatus;  CPU_CFOH_FAMILY_SERVICES *FamilySpecificServices;  ASSERT (IsBsp (StdHeader, &AgesaStatus));  FamilySpecificServices = NULL;  AndMask = 0xFFFFFFFF;  OrMask = 0x00000000;  PciRegister = 0;  AgesaStatus = AGESA_SUCCESS;  for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {    if (IsProcessorPresent (Socket, StdHeader)) {      // Get services for the socket      GetFeatureServicesOfSocket (&CacheFlushOnHaltFamilyServiceTable, Socket, (CONST VOID **)&FamilySpecificServices, StdHeader);      if (FamilySpecificServices != NULL) {        FamilySpecificServices->GetCacheFlushOnHaltRegister (FamilySpecificServices, &CfohPciAddress, &AndMask, &OrMask, StdHeader);        // Get the Or Mask value from IDS        IDS_OPTION_HOOK (IDS_CACHE_FLUSH_HLT, &OrMask, StdHeader);        // Set Cache Flush On Halt register        for (Module = 0; Module < (UINT8)GetPlatformNumberOfModules (); Module++) {          if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &AgesaStatus)) {            PciAddress.Address.Function = CfohPciAddress.Address.Function;            PciAddress.Address.Register = CfohPciAddress.Address.Register;            LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);            PciRegister &= AndMask;            PciRegister |= OrMask;            LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);          }        }      }    }  }  return AgesaStatus;}

BOOLEANMemNDQSTiming3Nb (  IN OUT   MEM_NB_BLOCK *NBPtr  ){  MEM_TECH_BLOCK *TechPtr;  TechPtr = NBPtr->TechPtr;  if (TechPtr->NBPtr->MCTPtr->NodeMemSize) {    AGESA_TESTPOINT (TpProcMemBeforeAgesaHookBeforeDQSTraining, &NBPtr->MemPtr->StdHeader);    if (AgesaHookBeforeDQSTraining (0, TechPtr->NBPtr->MemPtr) == AGESA_SUCCESS) {      // Right now we do not have anything to do if the callout is implemented    }    AGESA_TESTPOINT (TpProcMemAfterAgesaHookBeforeDQSTraining, &NBPtr->MemPtr->StdHeader);    //Execute Technology specific training features    if (memTechTrainingFeatDDR3.EnterHardwareTraining (TechPtr)) {      if (memTechTrainingFeatDDR3.SwWLTraining (TechPtr)) {        MemFInitTableDrive (NBPtr, MTAfterSwWLTrn);        if (memTechTrainingFeatDDR3.HwBasedWLTrainingPart1 (TechPtr)) {          MemFInitTableDrive (NBPtr, MTAfterHwWLTrnP1);          if (memTechTrainingFeatDDR3.HwBasedDQSReceiverEnableTrainingPart1 (TechPtr)) {            MemFInitTableDrive (NBPtr, MTAfterHwRxEnTrnP1);            // If target speed is higher than start-up speed, do frequency change and second pass of WL            if (MemTHwWlPart2 (TechPtr)) {              if (memTechTrainingFeatDDR3.TrainExitHwTrn (TechPtr)) {                IDS_OPTION_HOOK (IDS_PHY_DLL_STANDBY_CNTRL, NBPtr, &(NBPtr->MemPtr->StdHeader));                if (memTechTrainingFeatDDR3.NonOptimizedSWDQSRecEnTrainingPart1 (TechPtr)) {                  if (memTechTrainingFeatDDR3.OptimizedSwDqsRecEnTrainingPart1 (TechPtr)) {                    MemFInitTableDrive (NBPtr, MTAfterSwRxEnTrn);                    if (memTechTrainingFeatDDR3.NonOptimizedSRdWrPosTraining (TechPtr)) {                      if (memTechTrainingFeatDDR3.OptimizedSRdWrPosTraining (TechPtr)) {                        MemFInitTableDrive (NBPtr, MTAfterDqsRwPosTrn);                        do {                          if (memTechTrainingFeatDDR3.MaxRdLatencyTraining (TechPtr)) {                            MemFInitTableDrive (NBPtr, MTAfterMaxRdLatTrn);                          }                        } while (NBPtr->ChangeNbFrequency (NBPtr));                      }                    }                  }                }              }            }          }        }      }    }    MemTMarkTrainFail (TechPtr);  }  return TRUE;}

/** *    Main entry point for initializing the Thermal Control *    safety net feature. * *    This must be run by all Family 16h Mullins core 0s in the system. * * @param[in]  HtcServices             The current CPU's family services. * @param[in]  EntryPoint              Timepoint designator. * @param[in]  PlatformConfig          Platform profile/build option config structure. * @param[in]  StdHeader               Config handle for library and services. * * @retval     AGESA_SUCCESS           Always succeeds. * */AGESA_STATUSSTATICF16MlInitializeHtc (  IN       HTC_FAMILY_SERVICES    *HtcServices,  IN       UINT64                  EntryPoint,  IN       PLATFORM_CONFIGURATION *PlatformConfig,  IN       AMD_CONFIG_PARAMS      *StdHeader  ){  NB_CAPS_REGISTER               NbCaps;  HTC_REGISTER                   HtcReg;  CLK_PWR_TIMING_CTRL2_REGISTER  Cptc2;  POPUP_PSTATE_REGISTER          PopUpPstate;  PCI_ADDR                       PciAddress;  D0F0xBC_xC0107097_STRUCT       D0F0xBC_xC0107097;  if ((EntryPoint & (CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC)) != 0) {    PciAddress.AddressValue = NB_CAPS_PCI_ADDR;    LibAmdPciRead (AccessWidth32, PciAddress, &NbCaps, StdHeader);    if (NbCaps.HtcCapable == 1) {      // Enable HTC      PciAddress.Address.Register = HTC_REG;      LibAmdPciRead (AccessWidth32, PciAddress, &HtcReg, StdHeader);      GnbRegisterReadML (GnbGetHandle (StdHeader), D0F0xBC_xC0107097_TYPE, D0F0xBC_xC0107097_ADDRESS, &D0F0xBC_xC0107097, 0, StdHeader);      HtcReg.HtcTmpLmt = D0F0xBC_xC0107097.Field.HtcTmpLmt;      if (HtcReg.HtcTmpLmt != 0) {        // Enable HTC        HtcReg.HtcEn = 1;        PciAddress.Address.Register = CPTC2_REG;        LibAmdPciRead (AccessWidth32, PciAddress, &Cptc2, StdHeader);        if (HtcReg.HtcPstateLimit > Cptc2.HwPstateMaxVal) {          // F3xDC[HwPstateMaxVal] = F3x64[HtcPstateLimit]          Cptc2.HwPstateMaxVal = HtcReg.HtcPstateLimit;          LibAmdPciWrite (AccessWidth32, PciAddress, &Cptc2, StdHeader);          // F3xA8[PopDownPstate] = F3xDC[HwPstateMaxVal]          PciAddress.Address.Register = POPUP_PSTATE_REG;          LibAmdPciRead (AccessWidth32, PciAddress, &PopUpPstate, StdHeader);          PopUpPstate.PopDownPstate = Cptc2.HwPstateMaxVal;          LibAmdPciWrite (AccessWidth32, PciAddress, &PopUpPstate, StdHeader);        }      } else {        // Disable HTC        HtcReg.HtcEn = 0;      }      PciAddress.Address.Register = HTC_REG;      IDS_OPTION_HOOK (IDS_HTC_CTRL, &HtcReg, StdHeader);      LibAmdPciWrite (AccessWidth32, PciAddress, &HtcReg, StdHeader);    }  }  return AGESA_SUCCESS;}

BOOLEANMemNInitMCTNb (  IN OUT   MEM_NB_BLOCK *NBPtr  ){  MEM_TECH_BLOCK *TechPtr;  UINT8 Dct;  BOOLEAN Flag;  ID_INFO CallOutIdInfo;  TechPtr = NBPtr->TechPtr;  // Switch Tech functions for Nb  NBPtr->TechBlockSwitch (NBPtr);  // Start Memory controller initialization sequence  Flag = FALSE;  if (TechPtr->DimmPresence (TechPtr)) {    AGESA_TESTPOINT (TpProcMemPlatformSpecificInit, &(NBPtr->MemPtr->StdHeader));    if (NBPtr->MemNPlatformSpecificFormFactorInitNb (NBPtr)) {      AGESA_TESTPOINT (TpProcMemSpdTiming, &(NBPtr->MemPtr->StdHeader));      if (TechPtr->SpdCalcWidth (TechPtr)) {        AGESA_TESTPOINT (TpProcMemSpeedTclConfig, &(NBPtr->MemPtr->StdHeader));        if (TechPtr->SpdGetTargetSpeed (TechPtr)) {          for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {            NBPtr->SwitchDCT (NBPtr, Dct);            Flag |= MemNInitDCTNb (NBPtr);          }          if (Flag && !NBPtr->IsSupported[TwoStageDramInit] && (NBPtr->MCTPtr->ErrCode != AGESA_FATAL)) {            MemFInitTableDrive (NBPtr, MTBeforeDInit);            AGESA_TESTPOINT (TpProcMemBeforeAgesaHookBeforeDramInit, &(NBPtr->MemPtr->StdHeader));            IDS_PERF_TIMESTAMP (TP_BEGINAGESAHOOKBEFOREDRAMINIT, &(NBPtr->MemPtr->StdHeader));            CallOutIdInfo.IdField.SocketId = NBPtr->MCTPtr->SocketId;            CallOutIdInfo.IdField.ModuleId = NBPtr->MCTPtr->DieId;            IDS_HDT_CONSOLE (MEM_FLOW, "/nCalling out to Platform BIOS on Socket %d Module %d.../n", CallOutIdInfo.IdField.SocketId, CallOutIdInfo.IdField.ModuleId);            AgesaHookBeforeDramInit ((UINTN) CallOutIdInfo.IdInformation, NBPtr->MemPtr);            IDS_HDT_CONSOLE (MEM_FLOW, "/nVDDIO = 1.%dV/n", (NBPtr->RefPtr->DDR3Voltage == VOLT1_5) ? 5 :                                                  (NBPtr->RefPtr->DDR3Voltage == VOLT1_35) ? 35 :                                                  (NBPtr->RefPtr->DDR3Voltage == VOLT1_25) ? 25 : 999);            AGESA_TESTPOINT (TpProcMemAfterAgesaHookBeforeDramInit, &(NBPtr->MemPtr->StdHeader));            IDS_PERF_TIMESTAMP (TP_ENDAGESAHOOKBEFOREDRAMINIT, &(NBPtr->MemPtr->StdHeader));            IDS_OPTION_HOOK (IDS_BEFORE_DRAM_INIT, NBPtr, &(NBPtr->MemPtr->StdHeader));            NBPtr->StartupDCT (NBPtr);          }        }      }    }  }  return (BOOLEAN) (NBPtr->MCTPtr->ErrCode != AGESA_FATAL);}

/** *    Enable Cpu Cache Flush On Halt Function * *    @param[in]       FamilySpecificServices   The current Family Specific Services. *    @param[in]       EntryPoint               Timepoint designator. *    @param[in]       PlatformConfig           Contains the runtime modifiable feature input data. *    @param[in]       StdHeader                Config Handle for library, services. */VOIDSetF15KvCacheFlushOnHaltRegister (  IN       CPU_CFOH_FAMILY_SERVICES     *FamilySpecificServices,  IN       UINT64                       EntryPoint,  IN       PLATFORM_CONFIGURATION       *PlatformConfig,  IN       AMD_CONFIG_PARAMS            *StdHeader  ){  PCI_ADDR                              PciAddress;  F15_KV_CLK_PWR_TIMING_CTRL2_REGISTER  ClkPwrTimingCtrl2;  CSTATE_POLICY_CTRL1_REGISTER          CstatePolicyCtrl1;  CSTATE_CTRL1_REGISTER                 CstateCtrl1;  if ((EntryPoint & (CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC)) != 0) {    // Set D18F3xDC[CacheFlushOnHaltCtl] != 0    // Set D18F3xDC[CacheFlushOnHaltTmr]    PciAddress.AddressValue = CPTC2_PCI_ADDR;    LibAmdPciRead (AccessWidth32, PciAddress, &ClkPwrTimingCtrl2, StdHeader);    ClkPwrTimingCtrl2.CacheFlushOnHaltCtl = 7;    ClkPwrTimingCtrl2.CacheFlushOnHaltTmr = 0x32;    LibAmdPciWrite (AccessWidth32, PciAddress, &ClkPwrTimingCtrl2, StdHeader);    // Set D18F4x128[CacheFlushTmr, CacheFlushSucMonThreshold]    PciAddress.AddressValue = CSTATE_POLICY_CTRL1_PCI_ADDR;    LibAmdPciRead (AccessWidth32, PciAddress, &CstatePolicyCtrl1, StdHeader);    CstatePolicyCtrl1.CacheFlushTmr = 0x32;    CstatePolicyCtrl1.CacheFlushSucMonThreshold = 5;    CstatePolicyCtrl1.CacheFlushSucMonMispredictAct = 1;    CstatePolicyCtrl1.CacheFlushSucMonTmrSel = 0;    LibAmdPciWrite (AccessWidth32, PciAddress, &CstatePolicyCtrl1, StdHeader);    // Set cache flush bits in D18F4x118    PciAddress.AddressValue = CSTATE_CTRL1_PCI_ADDR;    LibAmdPciRead (AccessWidth32, PciAddress, &CstateCtrl1, StdHeader);    // Set C-state Action Field 0    CstateCtrl1.CacheFlushEnCstAct0 = 1;    CstateCtrl1.CacheFlushTmrSelCstAct0 = 2;    CstateCtrl1.ClkDivisorCstAct0 = 0;    // Set C-state Action Field 1    CstateCtrl1.CacheFlushEnCstAct1 = 1;    CstateCtrl1.CacheFlushTmrSelCstAct1 = 1;    CstateCtrl1.ClkDivisorCstAct1 = 0;    LibAmdPciWrite (AccessWidth32, PciAddress, &CstateCtrl1, StdHeader);    //Override the default setting    IDS_OPTION_HOOK (IDS_CACHE_FLUSH_HLT, NULL, StdHeader);  }}

/** * Common routine to initialize PLATFORM_CONFIGURATION. * * @param[in,out]   PlatformConfig   Platform profile/build option config structure * @param[in,out]   StdHeader        AMD standard header config param * * @retval      AGESA_SUCCESS     Always Succeeds. * */AGESA_STATUSCommonPlatformConfigInit (  IN OUT   PLATFORM_CONFIGURATION    *PlatformConfig,  IN OUT   AMD_CONFIG_PARAMS         *StdHeader  ){  UINTN i;  PlatformConfig->PlatformProfile = UserOptions.CfgPerformanceProfile;  PlatformConfig->PlatformDeemphasisList = UserOptions.CfgPlatformDeemphasisList;  PlatformConfig->CoreLevelingMode = (UINT8) UserOptions.CfgCoreLevelingMode;  PlatformConfig->C1eMode = UserOptions.CfgPlatformC1eMode;  PlatformConfig->C1ePlatformData = UserOptions.CfgPlatformC1eOpData;  PlatformConfig->C1ePlatformData1 = UserOptions.CfgPlatformC1eOpData1;  PlatformConfig->C1ePlatformData2 = UserOptions.CfgPlatformC1eOpData2;  PlatformConfig->C1ePlatformData3 = UserOptions.CfgPlatformC1eOpData3;  PlatformConfig->CStateMode = UserOptions.CfgPlatformCStateMode;  PlatformConfig->CStatePlatformData = UserOptions.CfgPlatformCStateOpData;  PlatformConfig->CStateIoBaseAddress = UserOptions.CfgPlatformCStateIoBaseAddress;  PlatformConfig->CpbMode = UserOptions.CfgPlatformCpbMode;  PlatformConfig->UserOptionDmi = UserOptions.OptionDmi;  PlatformConfig->UserOptionPState = UserOptions.OptionAcpiPstates;  PlatformConfig->UserOptionCrat = UserOptions.OptionCrat;  PlatformConfig->UserOptionCdit = UserOptions.OptionCdit;  PlatformConfig->UserOptionSrat = UserOptions.OptionSrat;  PlatformConfig->UserOptionSlit = UserOptions.OptionSlit;  PlatformConfig->UserOptionWhea = UserOptions.OptionWhea;  PlatformConfig->LowPowerPstateForProcHot = UserOptions.CfgLowPowerPstateForProcHot;  PlatformConfig->PowerCeiling = UserOptions.CfgAmdPstateCapValue;  PlatformConfig->ForcePstateIndependent = UserOptions.CfgAcpiPstateIndependent;  PlatformConfig->PStatesInHpcMode = UserOptions.OptionPStatesInHpcMode;  PlatformConfig->NumberOfIoApics = UserOptions.CfgPlatNumIoApics;  for (i = 0; i < MaxVrmType; i++) {    PlatformConfig->VrmProperties[i] = UserOptions.CfgPlatVrmCfg[i];  }  PlatformConfig->ProcessorScopeInSb = UserOptions.CfgProcessorScopeInSb;  PlatformConfig->ProcessorScopeName0 = UserOptions.CfgProcessorScopeName0;  PlatformConfig->ProcessorScopeName1 = UserOptions.CfgProcessorScopeName1;  PlatformConfig->GnbHdAudio = UserOptions.CfgGnbHdAudio;  PlatformConfig->AbmSupport = UserOptions.CfgAbmSupport;  PlatformConfig->DynamicRefreshRate = UserOptions.CfgDynamicRefreshRate;  PlatformConfig->LcdBackLightControl = UserOptions.CfgLcdBackLightControl;  if ((StdHeader->HeapStatus == HEAP_LOCAL_CACHE) ||      (StdHeader->HeapStatus == HEAP_TEMP_MEM) ||      (StdHeader->HeapStatus == HEAP_SYSTEM_MEM)) {    IDS_OPTION_HOOK (IDS_PLATFORMCFG_OVERRIDE, PlatformConfig, StdHeader);  }  return AGESA_SUCCESS;}

/** * Main entry point for the AMD_INIT_MID function. * * This entry point is responsible for performing any necessary functions needed * after PCI bus enumeration and just before control is passed to the video option ROM. * * @param[in,out] MidParams      Required input parameters for the AMD_INIT_MID *                                  entry point. * * @return        Aggregated status across all internal AMD mid calls invoked. * */AGESA_STATUSAmdInitMid (  IN OUT   AMD_MID_PARAMS *MidParams  ){  AGESA_STATUS  AgesaStatus;  AGESA_STATUS  CalledStatus;  IDS_HDT_CONSOLE (MAIN_FLOW, "AmdInitMid: Start/n/n");  AGESA_TESTPOINT (TpIfAmdInitMidEntry, &MidParams->StdHeader);  IDS_PERF_TIME_MEASURE (&MidParams->StdHeader);  AgesaStatus = AGESA_SUCCESS;  ASSERT (MidParams != NULL);  IDS_OPTION_HOOK (IDS_INIT_MID_BEFORE, MidParams, &MidParams->StdHeader);  IDS_HDT_CONSOLE (MAIN_FLOW, "DispatchCpuFeatures: MidStart/n");  CalledStatus = DispatchCpuFeatures (CPU_FEAT_INIT_MID_END, &MidParams->PlatformConfig, &MidParams->StdHeader);  IDS_HDT_CONSOLE (MAIN_FLOW, "DispatchCpuFeatures: MidEnd/n");  if (CalledStatus > AgesaStatus) {    AgesaStatus = CalledStatus;  }  CalledStatus = GnbInitAtMid (MidParams);  if (CalledStatus > AgesaStatus) {    AgesaStatus = CalledStatus;  }  IDS_OPTION_HOOK (IDS_INIT_MID_AFTER, MidParams, &MidParams->StdHeader);  IDS_PERF_TIME_MEASURE (&MidParams->StdHeader);  AGESA_TESTPOINT (TpIfAmdInitMidExit, &MidParams->StdHeader);  IDS_HDT_CONSOLE (MAIN_FLOW, "/nAmdInitMid: End/n/n");  IDS_HDT_CONSOLE_FLUSH_BUFFER (&MidParams->StdHeader);  return AgesaStatus;}

AGESA_STATUSPcieMapPortPciAddressML (  IN      PCIe_ENGINE_CONFIG     *Engine  ){  AGESA_STATUS            Status;  ML_COMPLEX_CONFIG       *ComplexConfig;  PCIe_COMPLEX_CONFIG     *Complex;  PCIe_PLATFORM_CONFIG    *Pcie;  UINT8                   DevFunc;  UINT8                   Index;  Status = AGESA_SUCCESS;  IDS_HDT_CONSOLE (GNB_TRACE, "PcieMapPortPciAddressML Enter/n");  Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Engine->Header);  Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Complex->Header);  if (Engine->Type.Port.PortData.DeviceNumber == 0 && Engine->Type.Port.PortData.FunctionNumber == 0) {    Engine->Type.Port.PortData.DeviceNumber = Engine->Type.Port.NativeDevNumber;    Engine->Type.Port.PortData.FunctionNumber = Engine->Type.Port.NativeFunNumber;  }  ComplexConfig = (ML_COMPLEX_CONFIG *) PcieConfigGetParentSilicon (Engine);  IDS_OPTION_HOOK (IDS_GNB_PCIE_PORT_REMAP, &Engine->Type.Port, GnbLibGetHeader (Pcie));  DevFunc = (Engine->Type.Port.PortData.DeviceNumber << 3) | Engine->Type.Port.PortData.FunctionNumber;  for (Index = 0; Index < sizeof (ComplexConfig->FmSilicon.PortDevMap); ++Index) {    if (ComplexConfig->FmSilicon.PortDevMap[Index] == DevFunc) {      Status = AGESA_ERROR;      break;    }  }  if (Status == AGESA_SUCCESS) {    ComplexConfig->FmSilicon.PortDevMap[Engine->Type.Port.PcieBridgeId] = DevFunc;  }  for (Index = 0; Index < sizeof (DefaultPortDevMapML); ++Index) {    if (DevFunc == DefaultPortDevMapML[Index]) {      Engine->Type.Port.LogicalBridgeId = Index;      // Get the configuration from the table or from "auto settings"      if (Engine->Type.Port.PortData.ApicDeviceInfo.GroupMap == 0x00) {        // If Group is 0, use "Auto" settings        Engine->Type.Port.PortData.ApicDeviceInfo = DefaultIoapicConfigML[Index];      }      break;    }  }  IDS_HDT_CONSOLE (GNB_TRACE, "PcieMapPortPciAddressML Exit [0x%x]/n", Status);  return  Status;}

/** * BSC entry point for enabling Core Performance Boost. * * Set up D18F4x15C[BoostSrc] and start the PDMs according to the BKDG. * * @param[in]  CpbServices             The current CPU's family services. * @param[in]  PlatformConfig          Contains the runtime modifiable feature input data. * @param[in]  EntryPoint              Current CPU feature dispatch point. * @param[in]  Socket                  Zero based socket number to check. * @param[in]  StdHeader               Config handle for library and services. * * @retval     AGESA_SUCCESS           Always succeeds. * */AGESA_STATUSSTATICF14OnInitializeCpb (  IN       CPB_FAMILY_SERVICES    *CpbServices,  IN       PLATFORM_CONFIGURATION *PlatformConfig,  IN       UINT64                 EntryPoint,  IN       UINT32                 Socket,  IN       AMD_CONFIG_PARAMS      *StdHeader  ){  PCI_ADDR             PciAddress;  CPB_CTRL_REGISTER    CpbControl;  LPMV_SCALAR2_REGISTER  LpmvScalar2;  SMUx0B_x8580_STRUCT  SMUx0Bx8580;  if ((EntryPoint & CPU_FEAT_BEFORE_PM_INIT) != 0) {    // F4x14C [25:24] ApmCstExtPol = 1    PciAddress.AddressValue = LPMV_SCALAR2_PCI_ADDR;    LibAmdPciRead (AccessWidth32, PciAddress, &LpmvScalar2, StdHeader);    LpmvScalar2.ApmCstExtPol = 1;    LibAmdPciWrite (AccessWidth32, PciAddress, &LpmvScalar2, StdHeader);    // F4x15C [1:0] BoostSrc = 1    // F4x15C [29] BoostEnAllCores = 1    PciAddress.AddressValue = CPB_CTRL_PCI_ADDR;    LibAmdPciRead (AccessWidth32, PciAddress, &CpbControl, StdHeader);    CpbControl.BoostSrc = 1;    CpbControl.BoostEnAllCores = 1;    IDS_OPTION_HOOK (IDS_CPB_CTRL, &CpbControl, StdHeader);    LibAmdPciWrite (AccessWidth32, PciAddress, &CpbControl, StdHeader);  } else if ((EntryPoint & CPU_FEAT_INIT_LATE_END) != 0) {    // Ensure that the recommended settings have been programmed into SMUx0B_x8580, then    // interrupt the SMU with service index 12h.    NbSmuRcuRegisterRead (SMUx0B_x8580_ADDRESS, &SMUx0Bx8580.Value, 1, StdHeader);    SMUx0Bx8580.Field.PdmPeriod = 0x1388;    SMUx0Bx8580.Field.PdmParamLoc = 0;    SMUx0Bx8580.Field.PdmCacEn = 1;    SMUx0Bx8580.Field.PdmUnit = 1;    SMUx0Bx8580.Field.PdmEn = 1;    NbSmuRcuRegisterWrite (SMUx0B_x8580_ADDRESS, &SMUx0Bx8580.Value, 1, TRUE, StdHeader);    NbSmuServiceRequest (0x12, TRUE, StdHeader);  }  return AGESA_SUCCESS;}

/** *    Enable BL-C Cpu Cache Flush On Halt Function * *    @param[in]       FamilySpecificServices   The current Family Specific Services. *    @param[in]       EntryPoint               Timepoint designator. *    @param[in]       PlatformConfig           Contains the runtime modifiable feature input data. *    @param[in]       StdHeader                Config Handle for library, services. */VOIDSetF10BlCacheFlushOnHaltRegister (  IN       CPU_CFOH_FAMILY_SERVICES     *FamilySpecificServices,  IN       UINT64                       EntryPoint,  IN       PLATFORM_CONFIGURATION       *PlatformConfig,  IN       AMD_CONFIG_PARAMS            *StdHeader  ){  UINT32       AndMask;  UINT32       OrMask;  UINT32       CoreCount;  PCI_ADDR     PciAddress;  CPU_LOGICAL_ID        CpuFamilyRevision;  if ((EntryPoint & CPU_FEAT_AFTER_POST_MTRR_SYNC) != 0) {    GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader);    PciAddress.Address.Function = FUNC_3;    PciAddress.Address.Register = CLOCK_POWER_TIMING_CTRL2_REG;    if (CpuFamilyRevision.Revision == AMD_F10_BL_C3) {      // F3xDC[25:19] = 04h      // F3xDC[18:16] = 111b      AndMask = 0xFC00FFFF;      OrMask = 0x00270000;    } else {      // F3xDC[25:19] = 28h      // F3xDC[18:16] = 111b      AndMask = 0xFC00FFFF;      OrMask = 0x01470000;      //For BL_C2 single Core, F3xDC[18:16] = 0      GetActiveCoresInCurrentSocket (&CoreCount, StdHeader);      if (CoreCount == 1) {        if (CpuFamilyRevision.Revision == AMD_F10_BL_C2) {          OrMask = 0x01400000;        }      }    }    // Get the Or Mask value from IDS    IDS_OPTION_HOOK (IDS_CACHE_FLUSH_HLT, &OrMask, StdHeader);    ModifyCurrentSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F3xDC  }}

BOOLEANMemNInitMCTNb (  IN OUT   MEM_NB_BLOCK *NBPtr  ){  MEM_TECH_BLOCK *TechPtr;  UINT8 Dct;  BOOLEAN Flag;  TechPtr = NBPtr->TechPtr;  // Switch Tech functions for Nb  NBPtr->TechBlockSwitch (NBPtr);  // Start Memory controller initialization sequence  Flag = FALSE;  if (TechPtr->DimmPresence (TechPtr)) {    AGESA_TESTPOINT (TpProcMemPlatformSpecificInit, &(NBPtr->MemPtr->StdHeader));    if (NBPtr->MemNPlatformSpecificFormFactorInitNb (NBPtr)) {      AGESA_TESTPOINT (TpProcMemSpdTiming, &(NBPtr->MemPtr->StdHeader));      if (TechPtr->SpdCalcWidth (TechPtr)) {        AGESA_TESTPOINT (TpProcMemSpeedTclConfig, &(NBPtr->MemPtr->StdHeader));        if (TechPtr->SpdGetTargetSpeed (TechPtr)) {          for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {            NBPtr->SwitchDCT (NBPtr, Dct);            Flag |= MemNInitDCTNb (NBPtr);          }          if (Flag && (NBPtr->MCTPtr->ErrCode != AGESA_FATAL)) {            MemFInitTableDrive (NBPtr, MTBeforeDInit);            AGESA_TESTPOINT (TpProcMemBeforeAgesaHookBeforeDramInit, &(NBPtr->MemPtr->StdHeader));            AgesaHookBeforeDramInit (0, NBPtr->MemPtr);            AGESA_TESTPOINT (TpProcMemAfterAgesaHookBeforeDramInit, &(NBPtr->MemPtr->StdHeader));            IDS_OPTION_HOOK (IDS_BEFORE_DRAM_INIT, NBPtr, &(NBPtr->MemPtr->StdHeader));            NBPtr->StartupDCT (NBPtr);          }        }      }    }  }  return (BOOLEAN) (NBPtr->MCTPtr->ErrCode != AGESA_FATAL);}

AGESA_STATUSGnbEarlyInterfaceML (  IN      AMD_CONFIG_PARAMS               *StdHeader  ){  AGESA_STATUS     Status;  AGESA_STATUS     AgesaStatus;  GNB_HANDLE       *GnbHandle;  UINT32           Property;  GNB_BUILD_OPTIONS_ML  *GnbBuildOptionData;  AgesaStatus = AGESA_SUCCESS;  IDS_HDT_CONSOLE (GNB_TRACE, "GnbEarlyInterfaceML Enter/n");  GnbHandle = GnbGetHandle (StdHeader);  GnbBuildOptionData = GnbLocateHeapBuffer (AMD_GNB_BUILD_OPTIONS_HANDLE, StdHeader);  ASSERT (GnbBuildOptionData != NULL);  Property = TABLE_PROPERTY_DEFAULT;  Property |= UserOptions.CfgGnbSyncFloodPinAsNmi ? TABLE_PROPERTY_NMI_SYNCFLOOD : 0;  IDS_OPTION_HOOK (IDS_GNB_PROPERTY, &Property, StdHeader);  IDS_OPTION_CALLOUT (IDS_CALLOUT_GNB_PACKAGE_POWER_CONFIG, GnbHandle, StdHeader);  GnbInitSmuBiosTableML (StdHeader);  Status = GnbProcessTable (             GnbHandle,             GnbEarlyInitTableML,             Property,             0,             StdHeader             );  AGESA_STATUS_UPDATE (Status, AgesaStatus);  if (GnbBuildOptionData->CfgUseSMUServices == TRUE) {    GnbRequestVddNbPminML (GnbHandle, StdHeader);  }  Status = GfxGBifEnableML (StdHeader);  ASSERT (Status == AGESA_SUCCESS);  IDS_HDT_CONSOLE (GNB_TRACE, "GnbEarlyInterfaceML Exit [0x%x]/n", AgesaStatus);  return  AgesaStatus;}

VOIDSTATICMemNPowerDownCtlDR (  IN OUT   MEM_NB_BLOCK *NBPtr  ){  MEM_PARAMETER_STRUCT *RefPtr;  UINT8 PowerDownMode;  RefPtr = NBPtr->RefPtr;  // we can't enable powerdown mode when doing WL  if (RefPtr->EnablePowerDown) {    MemNSetBitFieldNb (NBPtr, BFPowerDownEn, 1);    PowerDownMode = (UINT8) UserOptions.CfgPowerDownMode;    IDS_OPTION_HOOK (IDS_POWERDOWN_MODE, &PowerDownMode, &(NBPtr->MemPtr->StdHeader));    if (PowerDownMode) {      MemNSetBitFieldNb (NBPtr, BFPowerDownMode, 1);    }  }}

/** * PCIe Post Init * * * * @param[in]  StdHeader  Standard configuration header * @retval     AGESA_STATUS */AGESA_STATUSPciePostInterfaceML (  IN      AMD_CONFIG_PARAMS               *StdHeader  ){  AGESA_STATUS          AgesaStatus;  AGESA_STATUS          Status;  PCIe_PLATFORM_CONFIG  *Pcie;  GNB_BUILD_OPTIONS_ML  *GnbBuildOptionData;  IDS_HDT_CONSOLE (GNB_TRACE, "PciePostInterfaceML Enter/n");  AgesaStatus = AGESA_SUCCESS;  Status = PcieLocateConfigurationData (StdHeader, &Pcie);  IDS_OPTION_HOOK (IDS_BEFORE_GEN2_INIT, Pcie, StdHeader);  AGESA_STATUS_UPDATE (Status, AgesaStatus);  GnbBuildOptionData = GnbLocateHeapBuffer (AMD_GNB_BUILD_OPTIONS_HANDLE, StdHeader);  ASSERT (GnbBuildOptionData != NULL);  if ((Status == AGESA_SUCCESS) &&      (GnbBuildOptionData->CfgUseSMUServices == TRUE)) {    PciePortsVisibilityControlV5 (UnhidePorts, Pcie);    Status = PciePostInitML (Pcie);    AGESA_STATUS_UPDATE (Status, AgesaStatus);    ASSERT (Status == AGESA_SUCCESS);    Status = PciePostPortInitML (Pcie);    AGESA_STATUS_UPDATE (Status, AgesaStatus);    ASSERT (Status == AGESA_SUCCESS);    Status = PcieTrainingV2 (Pcie);    AGESA_STATUS_UPDATE (Status, AgesaStatus);    ASSERT (Status == AGESA_SUCCESS);    IDS_OPTION_CALLOUT (IDS_CALLOUT_GNB_PCIE_PHY_CONFIG, Pcie, StdHeader);    GnbSmuBiosTableGetPcieInfoML (StdHeader, Pcie);    PciePortsVisibilityControlV5 (HidePorts, Pcie);  }  IDS_HDT_CONSOLE (GNB_TRACE, "PciePostInterfaceML Exit [0x%x]/n", AgesaStatus);  return  AgesaStatus;}

AGESA_STATUSPcieFmAlibBuildAcpiTable (  IN       VOID                          *AlibSsdtPtr,  IN       AMD_CONFIG_PARAMS             *StdHeader  ){  AGESA_STATUS          Status;  AGESA_STATUS          AgesaStatus;  UINT32                AmlObjName;  GFX_PLATFORM_CONFIG   *Gfx;  VOID                  *AmlObjPtr;  BOOLEAN               AltVddNbSupport;  IDS_HDT_CONSOLE (GNB_TRACE, "PcieFmAlibBuildAcpiTable Enter/n");  AgesaStatus = AGESA_SUCCESS;  AltVddNbSupport = TRUE;//  AmlObjName = 'A0DA';  AmlObjName = 0x41304441;  AmlObjPtr = GnbLibFind (AlibSsdtPtr, ((ACPI_TABLE_HEADER*) &AlibSsdt[0])->TableLength, (UINT8*) &AmlObjName, sizeof (AmlObjName));  ASSERT (AmlObjPtr != NULL);  if (AmlObjPtr != NULL) {    Status =  GfxLocateConfigData (StdHeader, &Gfx);    AGESA_STATUS_UPDATE (Status, AgesaStatus);    ASSERT (Status == AGESA_SUCCESS);    if ((Status != AGESA_SUCCESS) || (GnbBuildOptions.CfgAltVddNb == FALSE) || (Gfx->UmaInfo.MemClock > DDR1333_FREQUENCY) ||        ((Gfx->GfxDiscreteCardInfo.AmdPcieGfxCardBitmap != 0) && GfxLibIsControllerPresent (StdHeader))) {      AltVddNbSupport = FALSE;    }    // CBS/IDS can change AltVddNbSupport    IDS_OPTION_HOOK (IDS_GNB_ALTVDDNB, &AltVddNbSupport, StdHeader);    if (!AltVddNbSupport) {      IDS_HDT_CONSOLE (GNB_TRACE, " AltVddNb - Disabled/n");      *(UINT8*)((UINT8*) AmlObjPtr + 5) = 0;    }  } else {    AgesaStatus = AGESA_ERROR;  }  IDS_HDT_CONSOLE (GNB_TRACE, "PcieFmAlibBuildAcpiTable Exit[0x%x]/n", AgesaStatus);  return AgesaStatus;}