自学教程：C++ AGESA_TESTPOINT函数代码示例

AGESA_STATUSMemRecNMemInitML (  IN OUT   MEM_NB_BLOCK *NBPtr  ){  AGESA_STATUS Status;  MEM_TECH_BLOCK *TechPtr;  TechPtr = NBPtr->TechPtr;  Status = AGESA_FATAL;  if (TechPtr->DimmPresence (TechPtr)) {    if (MemRecNAutoConfigNb (NBPtr)) {      AGESA_TESTPOINT (TpProcMemPlatformSpecificConfig, &(NBPtr->MemPtr->StdHeader));      if (MemRecNPlatformSpecML (NBPtr)) {        AgesaHookBeforeDramInitRecovery (0, NBPtr->MemPtr);        AGESA_TESTPOINT (TpProcMemStartDcts, &(NBPtr->MemPtr->StdHeader));        MemRecNStartupDCTML (NBPtr);        AGESA_TESTPOINT (TpProcMemMtrrConfiguration, &(NBPtr->MemPtr->StdHeader));        MemRecNCPUMemRecTypingNb (NBPtr);        AGESA_TESTPOINT (TpProcMemDramTraining, &(NBPtr->MemPtr->StdHeader));        NBPtr->TrainingFlow (NBPtr);        Status = AGESA_SUCCESS;      }    }  }  return Status;}

/** * * *      This function returns the conditional MSR device register list according *      to the register list ID. * *      @param[in]       *Device - pointer to the CONDITIONAL_PCI_DEVICE_DESCRIPTOR *      @param[out]      **RegisterHdr - pointer to the address of the register list *      @param[in]       *StdHeader - Config handle for library and services * *      @return          AGESA_STATUS *                          - AGESA_ALERT *                          - AGESA_FATAL *                          - AGESA_SUCCESS *                          - AGESA_WARNING */AGESA_STATUSMemFS3GetCMsrDeviceRegisterList (  IN       CONDITIONAL_MSR_DEVICE_DESCRIPTOR     *Device,     OUT   CMSR_REGISTER_BLOCK_HEADER            **RegisterHdr,  IN       AMD_CONFIG_PARAMS                     *StdHeader  ){  AGESA_STATUS RetVal;  S3_MEM_NB_BLOCK *S3NBPtr;  VOID *RegisterHeader;  LOCATE_HEAP_PTR LocHeap;  AGESA_BUFFER_PARAMS LocBufferParams;  LibAmdMemCopy (&LocBufferParams.StdHeader, StdHeader, sizeof (AMD_CONFIG_PARAMS), StdHeader);  LocHeap.BufferHandle = AMD_MEM_S3_NB_HANDLE;  LocBufferParams.BufferHandle = AMD_MEM_S3_NB_HANDLE;  AGESA_TESTPOINT (TpIfBeforeLocateS3CMsrBuffer, StdHeader);  if (HeapLocateBuffer (&LocHeap, StdHeader) == AGESA_SUCCESS) {    S3NBPtr = (S3_MEM_NB_BLOCK *)LocHeap.BufferPtr;  } else {    ASSERT(FALSE) ; // No match for heap status, but could not locate "AMD_MEM_S3_NB_HANDLE" in heap for S3GetMsr    return AGESA_FATAL;  }  AGESA_TESTPOINT (TpIfAfterLocateS3CMsrBuffer, StdHeader);  // NB block has already been constructed by main block.  // No need to construct it here.  RetVal = S3NBPtr[BSP_DIE].MemS3GetDeviceRegLst (Device->RegisterListID, &RegisterHeader);  *RegisterHdr = (CMSR_REGISTER_BLOCK_HEADER *)RegisterHeader;  return RetVal;}

/** * Topology Services Initialization. * * Build the system topology data structures.  Initialize hardware values needed * for correct fabric operation, such as core count. * * @param[in]   StdHeader              Opaque handle to standard config header * @param[in]   PlatformConfiguration  The platform configuration options. * * @retval      AGESA_SUCCESS     Only information events logged. * */AGESA_STATUSAmdTopologyInitialize (  IN       AMD_CONFIG_PARAMS      *StdHeader,  IN       PLATFORM_CONFIGURATION *PlatformConfiguration  ){  STATE_DATA State;  NORTHBRIDGE Nb;  State.ConfigHandle = StdHeader;  State.PlatformConfiguration = PlatformConfiguration;  // Initialize for status and event output  State.MaxEventClass = AGESA_SUCCESS;  // Allocate permanent heap structs that are interfaces to other AGESA services.  NewNodeAndSocketTables (&State);  if (IsBootCore (&State)) {    AGESA_TESTPOINT (TpProcTopologyEntry, State.ConfigHandle);    // Create the BSP's northbridge.    NewNorthBridge (0, &State, &Nb);    State.Nb = &Nb;    CoherentInit (&State);    AGESA_TESTPOINT (TpProcTopologyDone, State.ConfigHandle);  } else {    // Do the AP Topology Init, which produces Node and Socket Maps for the AP's use.    NewNorthBridge (0, &State, &Nb);    State.Nb = &Nb;    InitApMaps (&State);  }  return State.MaxEventClass;}

VOIDAmdMemInitDataStructDef (  IN OUT   MEM_DATA_STRUCT *MemPtr,  IN OUT   PLATFORM_CONFIGURATION   *PlatFormConfig  ){  UINT8 p;  UINT8 i;  // We need a way of specifying default values for each particular northbridge  // family.  We also need to make sure that the IBV knows which parameter struct  // is for which northbridge.  //----------------------------------------------------------------------------  AGESA_TESTPOINT (TpProcMemBeforeMemDataInit, &MemPtr->StdHeader);  MemPtr->PlatFormConfig = PlatFormConfig;  memNBInstalled[0].MemNInitDefaults (MemPtr);  //----------------------------------------------------------------------------  // INITIALIZE PLATFORM SPECIFIC CONFIGURATION STRUCT  //----------------------------------------------------------------------------  AGESA_TESTPOINT (TpProcMemPlatformSpecificConfig, &MemPtr->StdHeader);  i = 0;  for (p = 0; p < MAX_PLATFORM_TYPES; p++) {    if (memPlatformTypeInstalled[i] != NULL) {      MemPtr->GetPlatformCfg[p] = memPlatformTypeInstalled[i];      i++;    } else {      MemPtr->GetPlatformCfg[p] = MemAGetPsCfgDef;    }  }  AGESA_TESTPOINT (TpProcMemAfterMemDataInit, &MemPtr->StdHeader);  MemPtr->ErrorHandling = MemErrHandle;}

/** * Application Processor perform a function as directed by the BSC. * * This is needed for an AP task that must run after AGESA has relinquished control * of the APs to the IBV. * * @param[in]     AmdApExeParams  The interface struct for any required routine. * * @return        The most severe AGESA_STATUS returned by any called service.  Note *                that this will be the return value passed back to the BSC as the *                return value for the call out. * */AGESA_STATUSAmdLateRunApTask (  IN       AP_EXE_PARAMS  *AmdApExeParams  ){  AGESA_STATUS        CalledAgesaStatus;  AGESA_STATUS        ApLateTaskStatus;  DISPATCH_TABLE      *Entry;  AGESA_TESTPOINT (TpIfAmdLateRunApTaskEntry, &AmdApExeParams->StdHeader);  ASSERT (AmdApExeParams != NULL);  ApLateTaskStatus = AGESA_SUCCESS;  CalledAgesaStatus = AGESA_UNSUPPORTED;  // Dispatch, if valid  Entry = (DISPATCH_TABLE *) ApDispatchTable;  while (Entry->FunctionId != 0) {    if (AmdApExeParams->FunctionNumber == Entry->FunctionId) {      CalledAgesaStatus = Entry->EntryPoint (AmdApExeParams);      break;    }    Entry++;  }  if (CalledAgesaStatus > ApLateTaskStatus) {    ApLateTaskStatus = CalledAgesaStatus;  }  AGESA_TESTPOINT (TpIfAmdLateRunApTaskExit, &AmdApExeParams->StdHeader);  return  ApLateTaskStatus;}

/** * Optimize Link Features. * * Based on Link capabilities, apply optimization rules to come up with the best * settings, including several external limit decision from the interface. This includes * handling of subLinks.  Finally, after the port list data is updated, set the hardware * state for all Links. * * @param[in] State our global state */VOIDSTATICLinkOptimization (  IN       STATE_DATA *State  ){  AGESA_TESTPOINT (TpProcHtOptGather, State->ConfigHandle);  State->HtFeatures->GatherLinkData (State);  AGESA_TESTPOINT (TpProcHtOptRegang, State->ConfigHandle);  State->HtFeatures->RegangLinks (State);  AGESA_TESTPOINT (TpProcHtOptLinks, State->ConfigHandle);  State->HtFeatures->SelectOptimalWidthAndFrequency (State);  // A likely cause of mixed Retry settings on coherent links is sublink ratio balancing  // so check this after doing the sublinks.  AGESA_TESTPOINT (TpProcHtOptSubLinks, State->ConfigHandle);  State->HtFeatures->SubLinkRatioFixup (State);  if (State->HtFeatures->IsCoherentRetryFixup (State)) {    // Fix sublinks again within HT1 only frequencies, as ratios may be invalid again.    State->HtFeatures->SubLinkRatioFixup (State);  }  AGESA_TESTPOINT (TpProcHtOptFinish, State->ConfigHandle);  State->HtFeatures->SetLinkData (State);}

/** * Main entry point for the AMD_S3LATE_RESTORE function. * * This entry point is responsible for restoring saved registers and preparing the * silicon components for OS restart. * * @param[in,out] S3LateParams   Required input parameters for the AMD_S3LATE_RESTORE *                                  entry point. * * @return        Aggregated status across all internal AMD S3 late restore calls invoked. * */AGESA_STATUSAmdS3LateRestore (  IN OUT   AMD_S3LATE_PARAMS *S3LateParams  ){  UINT8  *BufferPointer;  VOID   *OrMaskPtr;  VOID   *LateContextPtr;  AGESA_STATUS ReturnStatus;  AGESA_STATUS CalledStatus;  AGESA_TESTPOINT (TpIfAmdS3LateRestoreEntry, &S3LateParams->StdHeader);  IDS_HDT_CONSOLE (MAIN_FLOW, "AmdS3LateRestore: Start/n/n");  ReturnStatus = AGESA_SUCCESS;  ASSERT (S3LateParams != NULL);  BufferPointer = (UINT8 *) S3LateParams->S3DataBlock.VolatileStorage;  S3LateParams->StdHeader.HeapBasePtr = &BufferPointer[((S3_VOLATILE_STORAGE_HEADER *) S3LateParams->S3DataBlock.VolatileStorage)->HeapOffset];  ASSERT (S3LateParams->StdHeader.HeapBasePtr != NULL);  IDS_OPTION_HOOK (IDS_PLATFORMCFG_OVERRIDE, &S3LateParams->PlatformConfig, &S3LateParams->StdHeader);  IDS_OPTION_HOOK (IDS_BEFORE_S3_RESTORE, S3LateParams, &(S3LateParams->StdHeader));  if (((S3_VOLATILE_STORAGE_HEADER *) S3LateParams->S3DataBlock.VolatileStorage)->RegisterDataSize != 0) {    LateContextPtr = &BufferPointer[((S3_VOLATILE_STORAGE_HEADER *) S3LateParams->S3DataBlock.VolatileStorage)->RegisterDataOffset];    // Restore registers before exiting self refresh    RestorePreESRContext (&OrMaskPtr,                          LateContextPtr,                          S3_LATE_RESTORE,                          &S3LateParams->StdHeader);    // Restore registers after exiting self refresh    RestorePostESRContext (OrMaskPtr,                           LateContextPtr,                           S3_LATE_RESTORE,                           &S3LateParams->StdHeader);  }  // Dispatch any features needing to run at this time point  IDS_HDT_CONSOLE (CPU_TRACE, "  Dispatch CPU features at S3 late restore end/n");  CalledStatus = DispatchCpuFeatures (CPU_FEAT_S3_LATE_RESTORE_END,                                      &S3LateParams->PlatformConfig,                                      &S3LateParams->StdHeader);  if (CalledStatus > ReturnStatus) {    ReturnStatus = CalledStatus;  }  CalledStatus = S3ScriptRestore (&S3LateParams->StdHeader);  if (CalledStatus > ReturnStatus) {    ReturnStatus = CalledStatus;  }  IDS_OPTION_HOOK (IDS_AFTER_S3_RESTORE, S3LateParams, &S3LateParams->StdHeader);  AGESA_TESTPOINT (TpIfAmdS3LateRestoreExit, &S3LateParams->StdHeader);  IDS_HDT_CONSOLE (MAIN_FLOW, "/nAmdS3LateRestore: End/n/n");  IDS_HDT_CONSOLE_S3_EXIT (&S3LateParams->StdHeader);  return  ReturnStatus;}

/** * Main entry point for the AMD_INIT_ENV function. * * This entry point is responsible for copying the heap contents from the * temp RAM area to main memory. * * @param[in,out] EnvParams         Required input parameters for the AMD_INIT_ENV *                                  entry point. * * @return        Aggregated status across all internal AMD env calls invoked. * */AGESA_STATUSAmdInitEnv (  IN OUT   AMD_ENV_PARAMS  *EnvParams  ){  AGESA_STATUS  AgesaStatus;  AGESA_STATUS  AmdInitEnvStatus;  AGESA_TESTPOINT (TpIfAmdInitEnvEntry, &EnvParams->StdHeader);  ASSERT (EnvParams != NULL);  AmdInitEnvStatus = AGESA_SUCCESS;  //Copy Temp Ram heap content to Main Ram  AgesaStatus = CopyHeapToMainRamAtPost (&(EnvParams->StdHeader));  if (AgesaStatus > AmdInitEnvStatus) {    AmdInitEnvStatus = AgesaStatus;  }  EnvParams->StdHeader.HeapStatus = HEAP_SYSTEM_MEM;  EnvParams->StdHeader.HeapBasePtr = HeapGetBaseAddress (&EnvParams->StdHeader);  // Any heap allocate/deallocate/locate buffer should be used after heap is rebuilt from here.  // After persistent heaps are transferred and rebuilt, HeapLocateBuffer can start to be used in IDS hook.  //Heap have been relocated, so Debug Print need be init again to get new address  IDS_PERF_TIMESTAMP (TP_BEGINPROCAMDINITENV, &EnvParams->StdHeader);  IDS_HDT_CONSOLE_INIT (&EnvParams->StdHeader);  IDS_HDT_CONSOLE (MAIN_FLOW, "Heap transfer End/n");  IDS_HDT_CONSOLE (MAIN_FLOW, "AmdInitEnv: Start/n/n");  IDS_OPTION_HOOK (IDS_PLATFORMCFG_OVERRIDE, &EnvParams->PlatformConfig, &(EnvParams->StdHeader));  IDS_OPTION_HOOK (IDS_BEFORE_PCI_INIT, EnvParams, &(EnvParams->StdHeader));  AgesaStatus = S3ScriptInit (&EnvParams->StdHeader);  if (AgesaStatus > AmdInitEnvStatus) {    AmdInitEnvStatus = AgesaStatus;  }  IDS_PERF_TIMESTAMP (TP_BEGININITENV, &EnvParams->StdHeader);  AgesaStatus = BldoptFchFunction.InitEnv (EnvParams);  AmdInitEnvStatus = (AgesaStatus > AmdInitEnvStatus) ? AgesaStatus : AmdInitEnvStatus;  IDS_PERF_TIMESTAMP (TP_ENDINITENV, &EnvParams->StdHeader);  IDS_PERF_TIMESTAMP (TP_BEGINGNBINITATENV, &EnvParams->StdHeader);  AgesaStatus = GnbInitAtEnv (EnvParams);  if (AgesaStatus > AmdInitEnvStatus) {    AmdInitEnvStatus = AgesaStatus;  }  IDS_PERF_TIMESTAMP (TP_ENDGNBINITATENV, &EnvParams->StdHeader);  AGESA_TESTPOINT (TpIfAmdInitEnvExit, &EnvParams->StdHeader);  IDS_HDT_CONSOLE (MAIN_FLOW, "/nAmdInitEnv: End/n");  IDS_PERF_TIMESTAMP (TP_ENDPROCAMDINITENV, &EnvParams->StdHeader);  IDS_HDT_CONSOLE_FLUSH_BUFFER (&EnvParams->StdHeader);  return  AmdInitEnvStatus;}

BOOLEANMemNDQSTiming3Nb (  IN OUT   MEM_NB_BLOCK *NBPtr  ){  MEM_TECH_BLOCK *TechPtr;  TechPtr = NBPtr->TechPtr;  if (TechPtr->NBPtr->MCTPtr->NodeMemSize) {    AGESA_TESTPOINT (TpProcMemBeforeAgesaHookBeforeDQSTraining, &NBPtr->MemPtr->StdHeader);    if (AgesaHookBeforeDQSTraining (0, TechPtr->NBPtr->MemPtr) == AGESA_SUCCESS) {      // Right now we do not have anything to do if the callout is implemented    }    AGESA_TESTPOINT (TpProcMemAfterAgesaHookBeforeDQSTraining, &NBPtr->MemPtr->StdHeader);    //Execute Technology specific training features    if (memTechTrainingFeatDDR3.EnterHardwareTraining (TechPtr)) {      if (memTechTrainingFeatDDR3.SwWLTraining (TechPtr)) {        MemFInitTableDrive (NBPtr, MTAfterSwWLTrn);        if (memTechTrainingFeatDDR3.HwBasedWLTrainingPart1 (TechPtr)) {          MemFInitTableDrive (NBPtr, MTAfterHwWLTrnP1);          if (memTechTrainingFeatDDR3.HwBasedDQSReceiverEnableTrainingPart1 (TechPtr)) {            MemFInitTableDrive (NBPtr, MTAfterHwRxEnTrnP1);            // If target speed is higher than start-up speed, do frequency change and second pass of WL            if (MemTHwWlPart2 (TechPtr)) {              if (memTechTrainingFeatDDR3.TrainExitHwTrn (TechPtr)) {                IDS_OPTION_HOOK (IDS_PHY_DLL_STANDBY_CNTRL, NBPtr, &(NBPtr->MemPtr->StdHeader));                if (memTechTrainingFeatDDR3.NonOptimizedSWDQSRecEnTrainingPart1 (TechPtr)) {                  if (memTechTrainingFeatDDR3.OptimizedSwDqsRecEnTrainingPart1 (TechPtr)) {                    MemFInitTableDrive (NBPtr, MTAfterSwRxEnTrn);                    if (memTechTrainingFeatDDR3.NonOptimizedSRdWrPosTraining (TechPtr)) {                      if (memTechTrainingFeatDDR3.OptimizedSRdWrPosTraining (TechPtr)) {                        MemFInitTableDrive (NBPtr, MTAfterDqsRwPosTrn);                        do {                          if (memTechTrainingFeatDDR3.MaxRdLatencyTraining (TechPtr)) {                            MemFInitTableDrive (NBPtr, MTAfterMaxRdLatTrn);                          }                        } while (NBPtr->ChangeNbFrequency (NBPtr));                      }                    }                  }                }              }            }          }        }      }    }    MemTMarkTrainFail (TechPtr);  }  return TRUE;}

BOOLEANMemNInitMCTNb (  IN OUT   MEM_NB_BLOCK *NBPtr  ){  MEM_TECH_BLOCK *TechPtr;  UINT8 Dct;  BOOLEAN Flag;  ID_INFO CallOutIdInfo;  TechPtr = NBPtr->TechPtr;  // Switch Tech functions for Nb  NBPtr->TechBlockSwitch (NBPtr);  // Start Memory controller initialization sequence  Flag = FALSE;  if (TechPtr->DimmPresence (TechPtr)) {    AGESA_TESTPOINT (TpProcMemPlatformSpecificInit, &(NBPtr->MemPtr->StdHeader));    if (NBPtr->MemNPlatformSpecificFormFactorInitNb (NBPtr)) {      AGESA_TESTPOINT (TpProcMemSpdTiming, &(NBPtr->MemPtr->StdHeader));      if (TechPtr->SpdCalcWidth (TechPtr)) {        AGESA_TESTPOINT (TpProcMemSpeedTclConfig, &(NBPtr->MemPtr->StdHeader));        if (TechPtr->SpdGetTargetSpeed (TechPtr)) {          for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {            NBPtr->SwitchDCT (NBPtr, Dct);            Flag |= MemNInitDCTNb (NBPtr);          }          if (Flag && !NBPtr->IsSupported[TwoStageDramInit] && (NBPtr->MCTPtr->ErrCode != AGESA_FATAL)) {            MemFInitTableDrive (NBPtr, MTBeforeDInit);            AGESA_TESTPOINT (TpProcMemBeforeAgesaHookBeforeDramInit, &(NBPtr->MemPtr->StdHeader));            IDS_PERF_TIMESTAMP (TP_BEGINAGESAHOOKBEFOREDRAMINIT, &(NBPtr->MemPtr->StdHeader));            CallOutIdInfo.IdField.SocketId = NBPtr->MCTPtr->SocketId;            CallOutIdInfo.IdField.ModuleId = NBPtr->MCTPtr->DieId;            IDS_HDT_CONSOLE (MEM_FLOW, "/nCalling out to Platform BIOS on Socket %d Module %d.../n", CallOutIdInfo.IdField.SocketId, CallOutIdInfo.IdField.ModuleId);            AgesaHookBeforeDramInit ((UINTN) CallOutIdInfo.IdInformation, NBPtr->MemPtr);            IDS_HDT_CONSOLE (MEM_FLOW, "/nVDDIO = 1.%dV/n", (NBPtr->RefPtr->DDR3Voltage == VOLT1_5) ? 5 :                                                  (NBPtr->RefPtr->DDR3Voltage == VOLT1_35) ? 35 :                                                  (NBPtr->RefPtr->DDR3Voltage == VOLT1_25) ? 25 : 999);            AGESA_TESTPOINT (TpProcMemAfterAgesaHookBeforeDramInit, &(NBPtr->MemPtr->StdHeader));            IDS_PERF_TIMESTAMP (TP_ENDAGESAHOOKBEFOREDRAMINIT, &(NBPtr->MemPtr->StdHeader));            IDS_OPTION_HOOK (IDS_BEFORE_DRAM_INIT, NBPtr, &(NBPtr->MemPtr->StdHeader));            NBPtr->StartupDCT (NBPtr);          }        }      }    }  }  return (BOOLEAN) (NBPtr->MCTPtr->ErrCode != AGESA_FATAL);}

/** * *   This function initializes the default values in the MEM_DATA_STRUCT * *     @param[in,out]   *MemPtr  - Pointer to the MEM_DATA_STRUCT * *     @retval      None */VOIDMemNInitDefaultsLN (  IN OUT   MEM_DATA_STRUCT *MemPtr  ){  UINT8 Socket;  UINT8 Channel;  MEM_PARAMETER_STRUCT *RefPtr;  AGESA_TESTPOINT (TpProcMemBeforeMemDataInit, &(MemPtr->StdHeader));  ASSERT (MemPtr != NULL);  RefPtr = MemPtr->ParameterListPtr;  // Memory Map/Mgt.  // Mask Bottom IO with 0xF8 to force hole size to have granularity of 128MB  RefPtr->BottomIo = 0xE0;  RefPtr->UmaMode = UserOptions.CfgUmaMode;  RefPtr->UmaSize = UserOptions.CfgUmaSize;  RefPtr->MemHoleRemapping = TRUE;  RefPtr->LimitMemoryToBelow1Tb = UserOptions.CfgLimitMemoryToBelow1Tb;  //  // Dram Timing  RefPtr->UserTimingMode = UserOptions.CfgTimingModeSelect;  RefPtr->MemClockValue = UserOptions.CfgMemoryClockSelect;  for (Socket = 0; Socket < MAX_SOCKETS_SUPPORTED; Socket++) {    for (Channel = 0; Channel < MAX_CHANNELS_PER_SOCKET; Channel++) {      MemPtr->SocketList[Socket].ChannelPtr[Channel] = NULL;      MemPtr->SocketList[Socket].TimingsPtr[Channel] = NULL;    }  }  // Memory Clear  RefPtr->EnableMemClr = TRUE;  // TableBasedAlterations  RefPtr->TableBasedAlterations = NULL;  // Platform config table  RefPtr->PlatformMemoryConfiguration = DefaultPlatformMemoryConfiguration;  // Memory Restore  RefPtr->MemRestoreCtl = FALSE;  RefPtr->SaveMemContextCtl = FALSE;  AmdS3ParamsInitializer (&RefPtr->MemContext);  // Dram Configuration  RefPtr->EnableBankIntlv = UserOptions.CfgMemoryEnableBankInterleaving;  RefPtr->EnableNodeIntlv = FALSE;  RefPtr->EnableChannelIntlv = UserOptions.CfgMemoryChannelInterleaving;  RefPtr->EnableBankSwizzle = UserOptions.CfgBankSwizzle;  RefPtr->EnableParity = FALSE;  RefPtr->EnableOnLineSpareCtl = FALSE;  // Dram Power  RefPtr->EnablePowerDown = UserOptions.CfgMemoryPowerDown;  // ECC  RefPtr->EnableEccFeature = UserOptions.CfgEnableEccFeature;}

/** * * MemMStandardTraining * * This function implements standard memory training whereby training functions * for all nodes are run by the BSP. * * *     @param[in,out]   *mmPtr   - Pointer to the MEM_MAIN_DATA_BLOCK * *     @return          TRUE -  No fatal error occurs. *     @return          FALSE - Fatal error occurs. */BOOLEANMemMStandardTraining (  IN OUT   MEM_MAIN_DATA_BLOCK *mmPtr  ){  UINT8 Die;  //  // If training is disabled, return success.  //  if (!UserOptions.CfgDqsTrainingControl) {    return TRUE;  }  //  // Run Northbridge-specific Standard Training feature for each die.  //  IDS_HDT_CONSOLE (MEM_STATUS, "/nStart serial training/n");  for (Die = 0 ; Die < mmPtr->DieCount ; Die ++ ) {    IDS_HDT_CONSOLE (MEM_STATUS, "Node %d/n", Die);    AGESA_TESTPOINT (TpProcMemBeforeAnyTraining, &(mmPtr->MemPtr->StdHeader));    mmPtr->NBPtr[Die].BeforeDqsTraining (&mmPtr->NBPtr[Die]);    mmPtr->NBPtr[Die].Execute1dMaxRdLatTraining = TRUE;    mmPtr->NBPtr[Die].FeatPtr->Training (&mmPtr->NBPtr[Die]);    mmPtr->NBPtr[Die].TechPtr->TechnologySpecificHook[LrdimmSyncTrainedDlys] (mmPtr->NBPtr[Die].TechPtr, NULL);    mmPtr->NBPtr[Die].AfterDqsTraining (&mmPtr->NBPtr[Die]);    if (mmPtr->NBPtr[Die].MCTPtr->ErrCode == AGESA_FATAL) {      break;    }  }  return (BOOLEAN) (Die == mmPtr->DieCount);}

/** * Update microcode patch in current processor for Family15h OR. * * This function acts as a wrapper for calling the LoadMicrocodePatch * routine at AmdInitEarly. * * This particualr version implements a workaround to a potential problem caused * when upgrading the microcode on Orochi B1 processors. * *  @param[in]   FamilyServices      The current Family Specific Services. *  @param[in]   EarlyParams         Service parameters. *  @param[in]   StdHeader           Config handle for library and services. * */VOIDF15OrLoadMicrocodePatchAtEarly (  IN       CPU_SPECIFIC_SERVICES  *FamilyServices,  IN       AMD_CPU_EARLY_PARAMS   *EarlyParams,  IN       AMD_CONFIG_PARAMS      *StdHeader  ){  UINT64         MsrValue;  UINT64         BuCfg2MsrValue;  UINT64         CuCfgMsrValue;  BOOLEAN        IsPatchLoaded;  AGESA_TESTPOINT (TpProcCpuLoadUcode, StdHeader);  if (IsCorePairPrimary (FirstCoreIsComputeUnitPrimary, StdHeader)) {    F15OrEarlySampleLoadMcuPatch.F15OrESAvoidNbCyclesStart (StdHeader, &BuCfg2MsrValue);    // Erratum #655    // Set MSR C001_1023[1] = 1b, prior to writing to MSR C001_1020    LibAmdMsrRead (MSR_CU_CFG, &CuCfgMsrValue, StdHeader);    MsrValue = CuCfgMsrValue | BIT1;    LibAmdMsrWrite (MSR_CU_CFG, &MsrValue, StdHeader);    IsPatchLoaded =  F15OrEarlySampleLoadMcuPatch.F15OrUpdateMcuPatchHook (StdHeader);    // Erratum #655    // Restore MSR C001_1023[1] = previous setting    LibAmdMsrWrite (MSR_CU_CFG, &CuCfgMsrValue, StdHeader);    F15OrEarlySampleLoadMcuPatch.F15OrESAvoidNbCyclesEnd (StdHeader, &BuCfg2MsrValue);    F15OrEarlySampleLoadMcuPatch.F15OrESAfterPatchLoaded (StdHeader, IsPatchLoaded);  }}

/** * Update microcode patch in current processor for Family14h ON. * * This function acts as a wrapper for calling the LoadMicrocodePatch * routine at AmdInitEarly. * *  @param[in]   FamilyServices      The current Family Specific Services. *  @param[in]   EarlyParams         Service parameters. *  @param[in]   StdHeader           Config handle for library and services. * */VOIDF14OnLoadMicrocodePatchAtEarly (  IN       CPU_SPECIFIC_SERVICES  *FamilyServices,  IN       AMD_CPU_EARLY_PARAMS   *EarlyParams,  IN       AMD_CONFIG_PARAMS      *StdHeader  ){  UINT64 MsrValue;  AGESA_TESTPOINT (TpProcCpuLoadUcode, StdHeader);  // To load a microcode patch while using the cache as general storage,  // the following steps are followed:  // 1. Program MSRC001_102B[L2AllocDcFlushVictim]=1.  // 2. Load the microcode patch.  // 3. Program MSRC001_102B[L2AllocDcFlushVictim]=0.  LibAmdMsrRead (MSR_BU_CFG3, &MsrValue, StdHeader);  MsrValue = MsrValue | BIT7;  LibAmdMsrWrite (MSR_BU_CFG3, &MsrValue, StdHeader);  LoadMicrocodePatch (StdHeader);  LibAmdMsrRead (MSR_BU_CFG3, &MsrValue, StdHeader);  MsrValue = MsrValue & ~((UINT64)BIT7);  LibAmdMsrWrite (MSR_BU_CFG3, &MsrValue, StdHeader);}

/** * Perform initialization services required at the Early Init POST time point. * * Execution Cache, HyperTransport, and AP Init advanced services are performed. * * @param[in]     EarlyParams  The interface struct for all early services * * @return        The most severe AGESA_STATUS returned by any called service. * */AGESA_STATUSAmdInitEarly (  IN OUT   AMD_EARLY_PARAMS  *EarlyParams  ){  AGESA_STATUS  CalledAgesaStatus;  AGESA_STATUS  EarlyInitStatus;  WARM_RESET_REQUEST Request;  UINT8 PrevRequestBit;  UINT8 PrevStateBits;  IDS_PERF_TIMESTAMP (TP_BEGINPROCAMDINITEARLY, &EarlyParams->StdHeader);  AGESA_TESTPOINT (TpIfAmdInitEarlyEntry, &EarlyParams->StdHeader);  EarlyInitStatus = AGESA_SUCCESS;  // Setup ROM execution cache  IDS_HDT_CONSOLE (MAIN_FLOW, "AllocateExecutionCache: Start/n");  CalledAgesaStatus = AllocateExecutionCache (&EarlyParams->StdHeader, &EarlyParams->CacheRegion[0]);  IDS_HDT_CONSOLE (MAIN_FLOW, "AllocateExecutionCache: End/n");  if (CalledAgesaStatus > EarlyInitStatus) {    EarlyInitStatus = CalledAgesaStatus;  }  IDS_HDT_CONSOLE_DEBUG_CODE (    {      extern CHAR8 *BldOptDebugOutput[];      UINT8 i;      for (i = 0; BldOptDebugOutput[i] != NULL; i++) {        IDS_HDT_CONSOLE (MAIN_FLOW, "/t%s/n", BldOptDebugOutput[i]);      }    }  )

/** * Initialize the coherent fabric. * * Perform discovery and initialization of the coherent fabric, for builds including * support for multiple coherent nodes. * * @param[in]   State   global state */VOIDSTATICCoherentInit (  IN OUT   STATE_DATA    *State  ){  UINT8 i;  UINT8 j;  UINT8 ModuleType;  UINT8 Module;  UINT8 HardwareSocket;  COHERENT_FABRIC Fabric;  // Because Node 0, the BSP, is not discovered, initialize info about it specially here.  // Allocate Socket Die Map.  // While the BSP is always capable of being the only processor in the system, call the  // IsExceededCapable method to make sure the BSP's capability is included in the aggregate system  // capability. We don't care to check the return value.  //  State->Fabric = &Fabric;  State->NodesDiscovered = 0;  State->TotalLinks = 0;  State->SysMpCap = MAX_NODES;  State->Nb->IsExceededCapable (0, State, State->Nb);  HardwareSocket = State->Nb->GetSocket (0, 0, State->Nb);  ModuleType = 0;  Module = 0;  State->Nb->GetModuleInfo (0, &ModuleType, &Module, State->Nb);  // No predecessor info for BSP, so pass 0xFF for those parameters.  State->HtInterface->SetNodeToSocketMap (0xFF, 0xFF, 0xFF, 0, HardwareSocket, Module, State);  // Initialize system state data structures  for (i = 0; i < MAX_NODES; i++) {    State->Fabric->SysDegree[i] = 0;    for (j = 0; j < MAX_NODES; j++) {      State->Fabric->SysMatrix[i][j] = 0;    }  }  //  // Call the coherent init features  //  // Discovery  State->HtFeatures->CoherentDiscovery (State);  State->HtInterface->PostMapToAp (State);  // Topology matching and Routing  AGESA_TESTPOINT (TpProcHtTopology, State->ConfigHandle);  State->HtFeatures->LookupComputeAndLoadRoutingTables (State);  State->HtFeatures->MakeHopCountTable (State);  // UpdateCoreRanges requires the other maps to be initialized, and the node count set.  FinalizeCoherentInit (State);  UpdateCoreRanges (State);  State->Fabric = NULL;}

/** * * This function generates a complete CDIT table into a memory buffer. * After completion, this table must be set by the system BIOS into its * internal ACPI namespace, and linked into the RSDT/XSDT * *    @param[in, out]  StdHeader        Standard Head Pointer *    @param[in]       PlatformConfig   Config handle for platform specific information *    @param[out]      CditPtr          Point to Cdit Struct including buffer address and length * *    @retval          UINT32  AGESA_STATUS */AGESA_STATUSCreateAcpiCdit (  IN OUT   AMD_CONFIG_PARAMS      *StdHeader,  IN       PLATFORM_CONFIGURATION *PlatformConfig,     OUT   VOID                   **CditPtr  ){  AGESA_TESTPOINT (TpProcCpuEntryCdit, StdHeader);  return ((*(OptionCditConfiguration.CditFeature)) (StdHeader, PlatformConfig, CditPtr));}

/** *  BvmReadyToBoot * * Description *    BVM hook of event for gEfiEventReadyToBootGuid, when this event been signaled before booting OS *    It will be called. * *  @param[in,out]   StdHeader    The Pointer of AMD_CONFIG_PARAMS. * * */VOIDBvmReadyToBoot (  IN OUT   AMD_CONFIG_PARAMS *StdHeader  ){  if (StdHeader->HeapBasePtr != 0) {    IdsBvmOptionHook (BVM_PLATFORM_TP_BEFORE_INT19, NULL, StdHeader);  }  AGESA_TESTPOINT (TpReadyToBoot, StdHeader);}

/** * Perform initialization services required at the Early Init POST time point. * * Execution Cache, HyperTransport, C1e, and AP Init advanced services are performed. * * @param[in, out]     RecoveryParams  The interface struct for Recovery services * * @return        The most severe AGESA_STATUS returned by any called service. * */AGESA_STATUSAmdInitRecovery (  IN OUT   AMD_RECOVERY_PARAMS      *RecoveryParams  ){  AGESA_STATUS  AgesaStatus;  AGESA_STATUS  CalledAgesaStatus;  AGESA_TESTPOINT (TpIfAmdInitRecoveryEntry, &RecoveryParams->StdHeader);  ASSERT (RecoveryParams != NULL);  AgesaStatus = AGESA_SUCCESS;  // Setup ROM execution cache  CalledAgesaStatus = AllocateExecutionCache (&RecoveryParams->StdHeader, &RecoveryParams->CacheRegion[0]);  if (CalledAgesaStatus > AgesaStatus) {    AgesaStatus = CalledAgesaStatus;  }  CalledAgesaStatus = AmdHtInitRecovery (&RecoveryParams->StdHeader);  if (CalledAgesaStatus > AgesaStatus) {    AgesaStatus = CalledAgesaStatus;  }  CalledAgesaStatus = AmdCpuRecovery ((AMD_CPU_RECOVERY_PARAMS *) &RecoveryParams->StdHeader);  if (CalledAgesaStatus > AgesaStatus) {    AgesaStatus = CalledAgesaStatus;  }  CalledAgesaStatus = AmdMemRecovery (RecoveryParams->MemConfig.MemData);  if (CalledAgesaStatus > AgesaStatus) {    AgesaStatus = CalledAgesaStatus;  }  CalledAgesaStatus = AmdGnbRecovery (&RecoveryParams->StdHeader);  if (CalledAgesaStatus > AgesaStatus) {    AgesaStatus = CalledAgesaStatus;  }  AGESA_TESTPOINT (TpIfAmdInitRecoveryExit, &RecoveryParams->StdHeader);  return  AgesaStatus;}

/** * * It will create the ACPI table of WHEA and return the pointer to the table. * *    @param[in, out]  StdHeader        Standard Head Pointer *    @param[in, out]  WheaMcePtr       Point to Whea Hest Mce table *    @param[in, out]  WheaCmcPtr       Point to Whea Hest Cmc table * *    @retval         AGESA_STATUS */AGESA_STATUSCreateAcpiWhea (  IN OUT   AMD_CONFIG_PARAMS    *StdHeader,  IN OUT   VOID                 **WheaMcePtr,  IN OUT   VOID                 **WheaCmcPtr  ){  AGESA_TESTPOINT (TpProcCpuEntryWhea, StdHeader);  return ((*(OptionWheaConfiguration.WheaFeature)) (StdHeader, WheaMcePtr, WheaCmcPtr));}

/** *--------------------------------------------------------------------------------------- * *  PStateLeveling * *  Description: *    This function will populate the PStateBuffer, after doing the PState Leveling *    Note: This function should be called for every core in the system. * *  Parameters: *    @param[in,out]    *PStateStrucPtr *    @param[in]        *StdHeader * *    @retval          AGESA_STATUS * *--------------------------------------------------------------------------------------- **/AGESA_STATUSPStateLeveling (  IN OUT   S_CPU_AMD_PSTATE   *PStateStrucPtr,  IN       AMD_CONFIG_PARAMS  *StdHeader  ){  AGESA_TESTPOINT (TpProcCpuEntryPstateLeveling, StdHeader);  return ((*(OptionPstatePostConfiguration.PstateLeveling)) (PStateStrucPtr, StdHeader));  // Note: Split config struct into PEI/DXE halves. This one is PEI.}

/** * * Run code on every AP in the system. * * @param[in] ApParams       AP task pointer. * @param[in] StdHeader      Handle to config for library and services * * @return    The most severe AGESA_STATUS returned by an AP. * */AGESA_STATUSRunLateApTaskOnAllAPs (  IN       AP_EXE_PARAMS     *ApParams,  IN       AMD_CONFIG_PARAMS *StdHeader  ){  UINT32                  NumberOfSockets;  UINT32                  NumberOfCores;  UINT8                   Socket;  UINT8                   Core;  UINT8                   ApicId;  UINT32                  BscSocket;  UINT32                  Ignored;  UINT32                  BscCoreNum;  AGESA_STATUS            CalledStatus;  AGESA_STATUS            IgnoredStatus;  AGESA_STATUS            AgesaStatus;  ASSERT (IsBsp (StdHeader, &IgnoredStatus));  AgesaStatus = AGESA_SUCCESS;  IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCoreNum, &IgnoredStatus);  NumberOfSockets = GetPlatformNumberOfSockets ();  for (Socket = 0; Socket < NumberOfSockets; Socket++) {    if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) {      for (Core = 0; Core < NumberOfCores; Core++) {        if ((Socket != BscSocket) || (Core != BscCoreNum)) {          GetApicId (StdHeader, Socket, Core, &ApicId, &IgnoredStatus);          AGESA_TESTPOINT (TpIfBeforeRunApFromAllAps, StdHeader);          CalledStatus = AgesaRunFcnOnAp ((UINTN) ApicId, ApParams);          AGESA_TESTPOINT (TpIfAfterRunApFromAllAps, StdHeader);          if (CalledStatus > AgesaStatus) {            AgesaStatus = CalledStatus;          }        }      }    }  }  return AgesaStatus;}

/** * Handle system and performance tunings. * * Including traffic distribution, fifo and * buffer tuning that can't be placed in the register table, * and special config tunings. * * @param[in] State    Total Nodes, port list data */VOIDSTATICTuning (  IN       STATE_DATA *State  ){  UINT8 Node;  // For each Node, invoke northbridge specific buffer tunings that can not be done in reg table.  //  AGESA_TESTPOINT (TpProcHtTuning, State->ConfigHandle);  for (Node = 0; Node < (State->NodesDiscovered + 1); Node++) {    State->Nb->BufferOptimizations (Node, State, State->Nb);  }  // See if traffic distribution can be done and do it if so.  //  AGESA_TESTPOINT (TpProcHtTrafficDist, State->ConfigHandle);  State->HtFeatures->TrafficDistribution (State);}

BOOLEANMemNInitMCTNb (  IN OUT   MEM_NB_BLOCK *NBPtr  ){  MEM_TECH_BLOCK *TechPtr;  UINT8 Dct;  BOOLEAN Flag;  TechPtr = NBPtr->TechPtr;  // Switch Tech functions for Nb  NBPtr->TechBlockSwitch (NBPtr);  // Start Memory controller initialization sequence  Flag = FALSE;  if (TechPtr->DimmPresence (TechPtr)) {    AGESA_TESTPOINT (TpProcMemPlatformSpecificInit, &(NBPtr->MemPtr->StdHeader));    if (NBPtr->MemNPlatformSpecificFormFactorInitNb (NBPtr)) {      AGESA_TESTPOINT (TpProcMemSpdTiming, &(NBPtr->MemPtr->StdHeader));      if (TechPtr->SpdCalcWidth (TechPtr)) {        AGESA_TESTPOINT (TpProcMemSpeedTclConfig, &(NBPtr->MemPtr->StdHeader));        if (TechPtr->SpdGetTargetSpeed (TechPtr)) {          for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {            NBPtr->SwitchDCT (NBPtr, Dct);            Flag |= MemNInitDCTNb (NBPtr);          }          if (Flag && (NBPtr->MCTPtr->ErrCode != AGESA_FATAL)) {            MemFInitTableDrive (NBPtr, MTBeforeDInit);            AGESA_TESTPOINT (TpProcMemBeforeAgesaHookBeforeDramInit, &(NBPtr->MemPtr->StdHeader));            AgesaHookBeforeDramInit (0, NBPtr->MemPtr);            AGESA_TESTPOINT (TpProcMemAfterAgesaHookBeforeDramInit, &(NBPtr->MemPtr->StdHeader));            IDS_OPTION_HOOK (IDS_BEFORE_DRAM_INIT, NBPtr, &(NBPtr->MemPtr->StdHeader));            NBPtr->StartupDCT (NBPtr);          }        }      }    }  }  return (BOOLEAN) (NBPtr->MCTPtr->ErrCode != AGESA_FATAL);}

/** * Update microcode patch in current processor for Family16h ML. * * This function acts as a wrapper for calling the LoadMicrocodePatch * routine at AmdInitEarly. * *  @param[in]   FamilyServices      The current Family Specific Services. *  @param[in]   EarlyParams         Service parameters. *  @param[in]   StdHeader           Config handle for library and services. * */VOIDF16MlLoadMicrocodePatchAtEarly (  IN       CPU_SPECIFIC_SERVICES  *FamilyServices,  IN       AMD_CPU_EARLY_PARAMS   *EarlyParams,  IN       AMD_CONFIG_PARAMS      *StdHeader  ){  if (!IsFeatureEnabled (C6Cstate, &EarlyParams->PlatformConfig, StdHeader)) {    AGESA_TESTPOINT (TpProcCpuLoadUcode, StdHeader);    LoadMicrocodePatch (StdHeader);  }}

/** * IDS function for ap run specific task after amdinitpost * * *  @param[in]   ApicIdOfCore      apic id of specific AP *  @param[in]   ApLateTaskPtr    The Pointer of IDSAPLATETASK. *  @param[in,out]   StdHeader    The Pointer of AMD_CONFIG_PARAMS. * *  @retval AGESA_SUCCESS       Success *  @retval AGESA_ERROR         meet some error * **/AGESA_STATUSIdsAgesaRunFcnOnApLate  (  IN       UINTN               ApicIdOfCore,  IN       IDSAPLATETASK  *ApLateTaskPtr,  IN OUT   AMD_CONFIG_PARAMS *StdHeader  ){  AGESA_STATUS  Status;  AP_EXE_PARAMS LaunchApParams;//init AgesaRunFcnOnAp parameters  LaunchApParams.FunctionNumber = IDS_LATE_RUN_AP_TASK_ID;  LaunchApParams.RelatedBlockLength = SIZE_IN_DWORDS (IDSAPLATETASK);  LaunchApParams.RelatedDataBlock = ApLateTaskPtr;  LaunchApParams.StdHeader = *StdHeader;  AGESA_TESTPOINT (TpIfBeforeRunApFromIds, StdHeader);  Status = AgesaRunFcnOnAp ((UINTN) ApicIdOfCore, &LaunchApParams);  AGESA_TESTPOINT (TpIfAfterRunApFromIds, StdHeader);  return Status;}

/** * * Run code on core 0 of every socket in the system. * * @param[in] ApParams       AP task pointer. * @param[in] StdHeader      Handle to config for library and services * * @return    The most severe AGESA_STATUS returned by an AP. * */AGESA_STATUSRunLateApTaskOnAllCore0s (  IN       AP_EXE_PARAMS     *ApParams,  IN       AMD_CONFIG_PARAMS *StdHeader  ){  UINT32                  NumberOfSockets;  UINT8                   Socket;  UINT8                   ApicId;  UINT32                  BscSocket;  UINT32                  IgnoredModule;  UINT32                  IgnoredCore;  AGESA_STATUS            CalledStatus;  AGESA_STATUS            IgnoredStatus;  AGESA_STATUS            AgesaStatus;  ASSERT (IsBsp (StdHeader, &IgnoredStatus));  AgesaStatus = AGESA_SUCCESS;  IdentifyCore (StdHeader, &BscSocket, &IgnoredModule, &IgnoredCore, &IgnoredStatus);  NumberOfSockets = GetPlatformNumberOfSockets ();  for (Socket = 0; Socket < NumberOfSockets; Socket++) {    if (IsProcessorPresent (Socket, StdHeader)) {      if (Socket != BscSocket) {        GetApicId (StdHeader, Socket, 0, &ApicId, &IgnoredStatus);        AGESA_TESTPOINT (TpIfBeforeRunApFromAllCore0s, StdHeader);        CalledStatus = AgesaRunFcnOnAp ((UINTN) ApicId, ApParams);        AGESA_TESTPOINT (TpIfAfterRunApFromAllCore0s, StdHeader);        if (CalledStatus > AgesaStatus) {          AgesaStatus = CalledStatus;        }      }    }  }  return AgesaStatus;}

/** * Main entry point for the AMD_INIT_MID function. * * This entry point is responsible for performing any necessary functions needed * after PCI bus enumeration and just before control is passed to the video option ROM. * * @param[in,out] MidParams      Required input parameters for the AMD_INIT_MID *                                  entry point. * * @return        Aggregated status across all internal AMD mid calls invoked. * */AGESA_STATUSAmdInitMid (  IN OUT   AMD_MID_PARAMS *MidParams  ){  AGESA_STATUS  AgesaStatus;  AGESA_STATUS  CalledStatus;  IDS_HDT_CONSOLE (MAIN_FLOW, "AmdInitMid: Start/n/n");  AGESA_TESTPOINT (TpIfAmdInitMidEntry, &MidParams->StdHeader);  IDS_PERF_TIME_MEASURE (&MidParams->StdHeader);  AgesaStatus = AGESA_SUCCESS;  ASSERT (MidParams != NULL);  IDS_OPTION_HOOK (IDS_INIT_MID_BEFORE, MidParams, &MidParams->StdHeader);  IDS_HDT_CONSOLE (MAIN_FLOW, "DispatchCpuFeatures: MidStart/n");  CalledStatus = DispatchCpuFeatures (CPU_FEAT_INIT_MID_END, &MidParams->PlatformConfig, &MidParams->StdHeader);  IDS_HDT_CONSOLE (MAIN_FLOW, "DispatchCpuFeatures: MidEnd/n");  if (CalledStatus > AgesaStatus) {    AgesaStatus = CalledStatus;  }  CalledStatus = GnbInitAtMid (MidParams);  if (CalledStatus > AgesaStatus) {    AgesaStatus = CalledStatus;  }  IDS_OPTION_HOOK (IDS_INIT_MID_AFTER, MidParams, &MidParams->StdHeader);  IDS_PERF_TIME_MEASURE (&MidParams->StdHeader);  AGESA_TESTPOINT (TpIfAmdInitMidExit, &MidParams->StdHeader);  IDS_HDT_CONSOLE (MAIN_FLOW, "/nAmdInitMid: End/n/n");  IDS_HDT_CONSOLE_FLUSH_BUFFER (&MidParams->StdHeader);  return AgesaStatus;}

/** * External AGESA interface to read an Event from the Event Log. * * This is the implementation of the external AGESA interface entry, as a thin wrapper * around the internal log services. * * @param[in]  Event           The event class, id, and any associated data. * * @retval     AGESA_SUCCESS   Always Succeeds. */AGESA_STATUSAmdReadEventLog (  IN       EVENT_PARAMS *Event  ){  AGESA_EVENT  LogEvent;  AGESA_STATUS Status;  AGESA_TESTPOINT (TpIfAmdReadEventLogEntry, &Event->StdHeader);  ASSERT (Event != NULL);  Event->StdHeader.HeapBasePtr = HeapGetBaseAddress (&Event->StdHeader);  Status = GetEventLog (&LogEvent, &Event->StdHeader);  Event->EventClass = LogEvent.EventClass;  Event->EventInfo = LogEvent.EventInfo;  Event->DataParam1 = LogEvent.DataParam1;  Event->DataParam2 = LogEvent.DataParam2;  Event->DataParam3 = LogEvent.DataParam3;  Event->DataParam4 = LogEvent.DataParam4;  AGESA_TESTPOINT (TpIfAmdReadEventLogExit, &Event->StdHeader);  return Status;}

/** * * * * *     @param[in,out]   *mmPtr   - Pointer to the MEM_MAIN_DATA_BLOCK * *     @return          TRUE -  No fatal error occurs. *     @return          FALSE - Fatal error occurs. */BOOLEANMemMEcc (  IN OUT   MEM_MAIN_DATA_BLOCK *mmPtr  ){  UINT8 Die;  DIE_STRUCT *MCTPtr;  MEM_SHARED_DATA *SharedPtr;  MEM_PARAMETER_STRUCT *RefPtr;  BOOLEAN RetVal;  RetVal = TRUE;  RefPtr = mmPtr->MemPtr->ParameterListPtr;  SharedPtr = mmPtr->mmSharedPtr;  MCTPtr = mmPtr->NBPtr->MCTPtr;  //  // Run Northbridge-specific ECC initialization feature for each die.  //  SharedPtr->AllECC = FALSE;  if (MCTPtr->Status[SbEccDimms] && RefPtr->EnableEccFeature) {    SharedPtr->AllECC = TRUE;    AGESA_TESTPOINT (TpProcMemEccInitialization, &(mmPtr->MemPtr->StdHeader));    for (Die = 0 ; Die < mmPtr->DieCount ; Die ++ ) {      mmPtr->NBPtr[Die].FeatPtr->CheckEcc (&(mmPtr->NBPtr[Die]));      RetVal &= (BOOLEAN) (mmPtr->NBPtr[Die].MCTPtr->ErrCode < AGESA_FATAL);    }    if (SharedPtr->AllECC == TRUE) {      RefPtr->GStatus[GsbAllECCDimms] = TRUE;      // Sync mem clear before setting scrub rate.      for (Die = 0; Die < mmPtr->DieCount; Die++) {        MemFMctMemClr_Sync (&(mmPtr->NBPtr[Die]));      }    }  }  // Scrubber control  for (Die = 0 ; Die < mmPtr->DieCount ; Die ++ ) {    mmPtr->NBPtr[Die].FeatPtr->InitEcc (&(mmPtr->NBPtr[Die]));  }  return RetVal;}