自学教程：C++ AT91_SMC_TDF_函数代码示例

static void afeb9260_nand_hw_init(void){	unsigned long csa;	/* Enable CS3 */	csa = at91_sys_read(AT91_MATRIX_EBICSA);	at91_sys_write(AT91_MATRIX_EBICSA,		       csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);	/* Configure SMC CS3 for NAND/SmartMedia */	at91_sys_write(AT91_SMC_SETUP(3),		       AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) |		       AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));	at91_sys_write(AT91_SMC_PULSE(3),		       AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |		       AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));	at91_sys_write(AT91_SMC_CYCLE(3),		       AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));	at91_sys_write(AT91_SMC_MODE(3),		       AT91_SMC_READMODE | AT91_SMC_WRITEMODE |		       AT91_SMC_EXNWMODE_DISABLE |		       AT91_SMC_DBW_8 |		       AT91_SMC_TDF_(2));	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOC);	/* Configure RDY/BSY */	at91_set_gpio_input(AT91_PIN_PC13, 1);	/* Enable NandFlash */	at91_set_gpio_output(AT91_PIN_PC14, 1);}

static void __init sam9_smc_cs_configure(void __iomem *base, struct sam9_smc_config* config){	/* Setup register */	__raw_writel(AT91_SMC_NWESETUP_(config->nwe_setup)		   | AT91_SMC_NCS_WRSETUP_(config->ncs_write_setup)		   | AT91_SMC_NRDSETUP_(config->nrd_setup)		   | AT91_SMC_NCS_RDSETUP_(config->ncs_read_setup),		   base + AT91_SMC_SETUP);	/* Pulse register */	__raw_writel(AT91_SMC_NWEPULSE_(config->nwe_pulse)		   | AT91_SMC_NCS_WRPULSE_(config->ncs_write_pulse)		   | AT91_SMC_NRDPULSE_(config->nrd_pulse)		   | AT91_SMC_NCS_RDPULSE_(config->ncs_read_pulse),		   base + AT91_SMC_PULSE);	/* Cycle register */	__raw_writel(AT91_SMC_NWECYCLE_(config->write_cycle)		   | AT91_SMC_NRDCYCLE_(config->read_cycle),		   base + AT91_SMC_CYCLE);	/* Mode register */	__raw_writel(config->mode		   | AT91_SMC_TDF_(config->tdf_cycles),		   base + AT91_SMC_MODE);}

static void set_smc_timings(const u8 chipselect, const u16 cycle,			    const u16 setup, const u16 pulse,			    const u16 data_float, int use_iordy){	unsigned long mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE |			     AT91_SMC_BAT_SELECT;	/* disable or enable waiting for IORDY signal */	if (use_iordy)		mode |= AT91_SMC_EXNWMODE_READY;	/* add data float cycles if needed */	if (data_float)		mode |= AT91_SMC_TDF_(data_float);	at91_sys_write(AT91_SMC_MODE(chipselect), mode);	/* setup timings in SMC */	at91_sys_write(AT91_SMC_SETUP(chipselect), AT91_SMC_NWESETUP_(setup) |						   AT91_SMC_NCS_WRSETUP_(0) |						   AT91_SMC_NRDSETUP_(setup) |						   AT91_SMC_NCS_RDSETUP_(0));	at91_sys_write(AT91_SMC_PULSE(chipselect), AT91_SMC_NWEPULSE_(pulse) |						   AT91_SMC_NCS_WRPULSE_(cycle) |						   AT91_SMC_NRDPULSE_(pulse) |						   AT91_SMC_NCS_RDPULSE_(cycle));	at91_sys_write(AT91_SMC_CYCLE(chipselect), AT91_SMC_NWECYCLE_(cycle) |						   AT91_SMC_NRDCYCLE_(cycle));}

static void __init eco920_board_init(void){	/* DBGU on ttyS0. (Rx & Tx only */	at91_register_uart(0, 0, 0);	at91_add_device_serial();	at91_add_device_eth(&eco920_eth_data);	at91_add_device_usbh(&eco920_usbh_data);	at91_add_device_udc(&eco920_udc_data);	at91_add_device_mci(0, &eco920_mci0_data);	platform_device_register(&eco920_flash);	at91_ramc_write(0, AT91_SMC_CSR(7),	AT91_SMC_RWHOLD_(1)				| AT91_SMC_RWSETUP_(1)				| AT91_SMC_DBW_8				| AT91_SMC_WSEN				| AT91_SMC_NWS_(15));	at91_set_A_periph(AT91_PIN_PC6, 1);	at91_set_gpio_input(AT91_PIN_PA23, 0);	at91_set_deglitch(AT91_PIN_PA23, 1);/* Initialization of the Static Memory Controller for Chip Select 3 */	at91_ramc_write(0, AT91_SMC_CSR(3),		AT91_SMC_DBW_16  |	/* 16 bit */		AT91_SMC_WSEN    |		AT91_SMC_NWS_(5) |	/* wait states */		AT91_SMC_TDF_(1)	/* float time */	);	at91_add_device_spi(eco920_spi_devices, ARRAY_SIZE(eco920_spi_devices));	/* LEDs */	at91_gpio_leds(eco920_leds, ARRAY_SIZE(eco920_leds));}

static void yl9200_init_video(void){	/* NWAIT Signal */	at91_set_A_periph(AT91_PIN_PC6, 0);	/* Initialization of the Static Memory Controller for Chip Select 2 */	at91_ramc_write(0, AT91_SMC_CSR(2), AT91_SMC_DBW_16		/* 16 bit */			| AT91_SMC_WSEN | AT91_SMC_NWS_(0x4)	/* wait states */			| AT91_SMC_TDF_(0x100)			/* float time */	);}

static void __init ek_init_video(void){	/* NWAIT Signal */	at91_set_A_periph(AT91_PIN_PC6, 0);	/* Initialization of the Static Memory Controller for Chip Select 3 */	at91_sys_write(AT91_SMC_CSR(3), AT91_SMC_DBW_16			/* 16 bit */				| AT91_SMC_WSEN | AT91_SMC_NWS_(5)	/* wait states */				| AT91_SMC_TDF_(1)			/* float time */	);	at91_ics1523_init();}

void init_smc_ddr(){#if 0	printf("leds should change now!/n");  	at91_set_gpio_output(AT91_PIN_PA0, 1);	at91_set_gpio_output(AT91_PIN_PA1, 0);	vTaskDelay(2000);	printf("leds should change now!/n");	at91_set_gpio_value(AT91_PIN_PA0, 0);	at91_set_gpio_value(AT91_PIN_PA1, 1);#endif  /* Configure the EBI1 pins for the wr switch */	int i;		/* PC16..31: periphA as EBI1_D16..31 */	for (i = AT91_PIN_PC16; i <= AT91_PIN_PC31; i++){		at91_set_A_periph(i, 0);	}	/* PC2 and PC3 too: EBI1_A19 EBI1_A20 */	at91_set_A_periph(AT91_PIN_PC2, 0);	at91_set_A_periph(AT91_PIN_PC3, 0);			/* FIXME: We should pull rst high for when it is programmed */	/* Then, write the EBI1 configuration (NCS0 == 0x1000.0000) */	at91_sys_write(AT91_SMC_SETUP(0),				AT91_SMC_NWESETUP_(4) |				AT91_SMC_NCS_WRSETUP_(2) |				AT91_SMC_NRDSETUP_(4) |				AT91_SMC_NCS_RDSETUP_(2));	at91_sys_write(AT91_SMC_PULSE(0),				AT91_SMC_NWEPULSE_(30) |				AT91_SMC_NCS_WRPULSE_(34) |				AT91_SMC_NRDPULSE_(30) |				AT91_SMC_NCS_RDPULSE_(34));	at91_sys_write(AT91_SMC_CYCLE(0),				AT91_SMC_NWECYCLE_(40) |				AT91_SMC_NRDCYCLE_(40));	at91_sys_write(AT91_SMC_MODE(0),				AT91_SMC_DBW_32 |				AT91_SMC_TDF_(0) |				AT91_SMC_READMODE |				AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_FROZEN);			}

void nandflash_hw_init(void){	unsigned int reg;	/* Configure nand pins */	const struct pio_desc nand_pins_lo[] = {		{"NANDOE",	AT91C_PIN_PD(0), 0,		PIO_PULLUP, PIO_PERIPH_A},		{"NANDWE",	AT91C_PIN_PD(1), 0,		PIO_PULLUP, PIO_PERIPH_A},		{"NANDALE",	AT91C_PIN_PD(2), 0,		PIO_PULLUP, PIO_PERIPH_A},		{"NANDCLE",	AT91C_PIN_PD(3), 0,		PIO_PULLUP, PIO_PERIPH_A},		{"NANDCS",	CONFIG_SYS_NAND_ENABLE_PIN,	1, PIO_PULLUP, PIO_OUTPUT},		{(char *)0,	0, 0, PIO_DEFAULT, PIO_PERIPH_A},	};	reg = readl(AT91C_BASE_CCFG + CCFG_EBICSA);	reg |= AT91C_EBI_CS3A_SM;	reg &= ~AT91C_EBI_NFD0_ON_D16;	/* nandflash connect to D0~D15 */	reg |= AT91C_EBI_DRV;	/* according to IAR verification package */	writel(reg, AT91C_BASE_CCFG + CCFG_EBICSA);	/* Configure SMC CS3 */	writel((AT91C_SMC_NWESETUP_(1)		| AT91C_SMC_NCS_WRSETUP_(0)		| AT91C_SMC_NRDSETUP_(3)		| AT91C_SMC_NCS_RDSETUP_(0)), 		AT91C_BASE_SMC + SMC_SETUP3);	writel((AT91C_SMC_NWEPULSE_(3)		| AT91C_SMC_NCS_WRPULSE_(5) 		| AT91C_SMC_NRDPULSE_(4) 		| AT91C_SMC_NCS_RDPULSE_(6)), 		AT91C_BASE_SMC + SMC_PULSE3);	writel((AT91C_SMC_NWECYCLE_(5)		| AT91C_SMC_NRDCYCLE_(8)),		AT91C_BASE_SMC + SMC_CYCLE3);	writel((AT91C_SMC_READMODE 		| AT91C_SMC_WRITEMODE 		| AT91C_SMC_NWAITM_NWAIT_DISABLE 		| AT91C_SMC_DBW_WIDTH_BITS_8		| AT91_SMC_TDF_(1)), 		AT91C_BASE_SMC + SMC_CTRL3);	/* Configure the nand controller pins*/	writel((1 << AT91C_ID_PIOC_D), (PMC_PCER + AT91C_BASE_PMC));	pio_configure(nand_pins_lo);}

static void __init yl_9200_init_video(void){	at91_sys_write(AT91_PIOC + PIO_ASR,AT91_PIN_PC6);	at91_sys_write(AT91_PIOC + PIO_BSR,0);	at91_sys_write(AT91_PIOC + PIO_ASR,AT91_PIN_PC6);	at91_sys_write( AT91_SMC_CSR(2),	AT91_SMC_NWS_(0x4) |	AT91_SMC_WSEN |	AT91_SMC_TDF_(0x100) |	AT91_SMC_DBW	);}

void nandflash_hw_init(void){	unsigned int reg;	/* Setup Smart Media, first enable the address range of	 * CS3 in HMATRIX user interface  */	reg = readl(AT91C_BASE_CCFG + CCFG_EBICSA);	reg |= AT91C_EBI_CS3A_SM;	writel(reg, AT91C_BASE_CCFG + CCFG_EBICSA);	/* Configure SMC CS3 */	writel((AT91C_SMC_NWESETUP_(1)		| AT91C_SMC_NCS_WRSETUP_(0)		| AT91C_SMC_NRDSETUP_(1)		| AT91C_SMC_NCS_RDSETUP_(0)),		AT91C_BASE_SMC + SMC_SETUP3);	writel((AT91C_SMC_NWEPULSE_(3)		| AT91C_SMC_NCS_WRPULSE_(3)		| AT91C_SMC_NRDPULSE_(3)		| AT91C_SMC_NCS_RDPULSE_(3)),		AT91C_BASE_SMC + SMC_PULSE3);	writel((AT91C_SMC_NWECYCLE_(5)		| AT91C_SMC_NRDCYCLE_(5)),		AT91C_BASE_SMC + SMC_CYCLE3);	writel((AT91C_SMC_READMODE		| AT91C_SMC_WRITEMODE		/* AT91C_SMC_NWAITM_NWAIT_DISABLE */		| (0x0 << 5)		| AT91C_SMC_DBW_WIDTH_BITS_16		| AT91_SMC_TDF_(2)),		AT91C_BASE_SMC + SMC_CTRL3);	/* configure NAND pins */	/* {"NANDCS", AT91C_PIN_PC(14), 1, PIO_PULLUP, PIO_OUTPUT} */	writel((0x01 << 14), AT91C_BASE_PIOC + PIO_IDR(0));	writel((0x01 << 14), AT91C_BASE_PIOC + PIO_PPUDR(0));	writel((0x01 << 14), AT91C_BASE_PIOC + PIO_SODR(0));	writel((0x01 << 14), AT91C_BASE_PIOC + PIO_OER(0));	writel((0x01 << 14), AT91C_BASE_PIOC + PIO_PER(0));	/* enable PIOC clock  */	writel((1 << AT91C_ID_PIOC), PMC_PCER + AT91C_BASE_PMC);}

void nandflash_hw_init(void){	unsigned int reg;	/* Configure PIOs */	const struct pio_desc nand_pins[] = {		{"NANDCS",	CONFIG_SYS_NAND_ENABLE_PIN,	1, PIO_PULLUP, PIO_OUTPUT},		{(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},	};	/* Setup Smart Media, first enable the address range of CS3	 * in HMATRIX user interface	* EBI IO in 1.8V mode */	reg = readl(AT91C_BASE_CCFG + CCFG_EBICSA);	reg |= AT91C_EBI_CS3A_SM;	reg &= ~AT91C_VDDIOM_SEL_33V;	writel(reg, AT91C_BASE_CCFG + CCFG_EBICSA);	/* Configure SMC CS3 */	writel((AT91C_SMC_NWESETUP_(2)		| AT91C_SMC_NCS_WRSETUP_(0)		| AT91C_SMC_NRDSETUP_(2)		| AT91C_SMC_NCS_RDSETUP_(0)),		AT91C_BASE_SMC + SMC_SETUP3);	writel((AT91C_SMC_NWEPULSE_(4)		| AT91C_SMC_NCS_WRPULSE_(4)		| AT91C_SMC_NRDPULSE_(4)		| AT91C_SMC_NCS_RDPULSE_(4)),		AT91C_BASE_SMC + SMC_PULSE3);	writel((AT91C_SMC_NWECYCLE_(7)		|  AT91C_SMC_NRDCYCLE_(7)),		AT91C_BASE_SMC + SMC_CYCLE3);	writel((AT91C_SMC_READMODE		| AT91C_SMC_WRITEMODE		| AT91C_SMC_NWAITM_NWAIT_DISABLE		| AT91C_SMC_DBW_WIDTH_BITS_16		| AT91_SMC_TDF_(3)),		AT91C_BASE_SMC + SMC_CTRL3);	/* Configure the PIO controll */	writel((1 << AT91C_ID_PIOC), (PMC_PCER + AT91C_BASE_PMC));	pio_configure(nand_pins);}

void nandflash_hw_init(void){	unsigned int reg;	/* Configure NANDFlash pins*/	const struct pio_desc nand_pins[] = {		{"NANDALE",	AT91C_PIN_PB(2),		0, PIO_PULLUP, PIO_PERIPH_A},		{"NANDCLE",	AT91C_PIN_PB(3),		0, PIO_PULLUP, PIO_PERIPH_A},		{"NANDOE",	AT91C_PIN_PB(4),		0, PIO_PULLUP, PIO_PERIPH_A},		{"NANDWE",	AT91C_PIN_PB(5),		0, PIO_PULLUP, PIO_PERIPH_A},		{"NANDCS",	CONFIG_SYS_NAND_ENABLE_PIN,	1, PIO_PULLUP, PIO_OUTPUT},		{(char *)0, 	0, 0, PIO_DEFAULT, PIO_PERIPH_A},	};	/* Setup Smart Media, first enable the address range of CS3 in HMATRIX user interface  */	reg = readl(AT91C_BASE_CCFG + CCFG_EBI0CSA);	reg |= AT91C_EBI_CS3A_SM;	writel(reg, AT91C_BASE_CCFG + CCFG_EBI0CSA);	/* Configure SMC CS3 */	writel((AT91C_SMC_NWESETUP_(1)		| AT91C_SMC_NCS_WRSETUP_(0)		| AT91C_SMC_NRDSETUP_(1)		| AT91C_SMC_NCS_RDSETUP_(0)),		AT91C_BASE_SMC + SMC_SETUP3);	writel((AT91C_SMC_NWEPULSE_(3)		| AT91C_SMC_NCS_WRPULSE_(3)		| AT91C_SMC_NRDPULSE_(3)		| AT91C_SMC_NCS_RDPULSE_(3)),		AT91C_BASE_SMC + SMC_PULSE3);	writel((AT91C_SMC_NWECYCLE_(5)		|  AT91C_SMC_NRDCYCLE_(5)),		AT91C_BASE_SMC + SMC_CYCLE3);	writel((AT91C_SMC_READMODE		| AT91C_SMC_WRITEMODE		| AT91C_SMC_NWAITM_NWAIT_DISABLE		| AT91C_SMC_DBW_WIDTH_BITS_8		| AT91_SMC_TDF_(2)),		AT91C_BASE_SMC + SMC_CTRL3);	/* Configure the NANDFlash pins */	pmc_enable_periph_clock(AT91C_ID_PIOB);	pio_configure(nand_pins);}

/* * Enable NAND and detect card. */static void at91_nand_enable(struct at91_nand_host *host){	unsigned int csa;	/* Setup Smart Media, first enable the address range of CS3 */	csa = at91_sys_read(AT91_EBI_CSA);	at91_sys_write(AT91_EBI_CSA, csa | AT91_EBI_CS3A_SMC_SMARTMEDIA);	/* set the bus interface characteristics */	at91_sys_write(AT91_SMC_CSR(3), AT91_SMC_ACSS_STD | AT91_SMC_DBW_8 | AT91_SMC_WSEN				| AT91_SMC_NWS_(5)				| AT91_SMC_TDF_(1)				| AT91_SMC_RWSETUP_(0)	/* tDS Data Set up Time 30 - ns */				| AT91_SMC_RWHOLD_(1)	/* tDH Data Hold Time 20 - ns */	);	if (host->board->enable_pin)		at91_set_gpio_value(host->board->enable_pin, 0);}

/* * Static memory controller initialization to enable Beckhoff ET1100 EtherCAT * controller debugging * The ET1100 is located at physical address 0x70000000 * Its process memory is located at physical address 0x70001000 */static void meesc_ethercat_hw_init(void){	/* Configure SMC EBI1_CS0 for EtherCAT */	at91_sys_write(AT91_SMC1_SETUP(0),		AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) |		AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));	at91_sys_write(AT91_SMC1_PULSE(0),		AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(9) |		AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(9));	at91_sys_write(AT91_SMC1_CYCLE(0),		AT91_SMC_NWECYCLE_(10) | AT91_SMC_NRDCYCLE_(5));	/* Configure behavior at external wait signal, byte-select mode, 16 bit	data bus width, none data float wait states and TDF optimization */	at91_sys_write(AT91_SMC1_MODE(0),		AT91_SMC_READMODE | AT91_SMC_EXNWMODE_READY |		AT91_SMC_BAT_SELECT | AT91_SMC_DBW_16 | AT91_SMC_TDF_(0) |		AT91_SMC_TDFMODE);	/* Configure RDY/BSY */	at91_set_B_periph(AT91_PIN_PE20, 0);	/* EBI1_NWAIT */}

static void at91cap9_nor_hw_init(void){    unsigned long csa;    /* Ensure EBI supply is 3.3V */    csa = at91_sys_read(AT91_MATRIX_EBICSA);    at91_sys_write(AT91_MATRIX_EBICSA,                   csa | AT91_MATRIX_EBI_VDDIOMSEL_3_3V);    /* Configure SMC CS0 for parallel flash */    at91_sys_write(AT91_SMC_SETUP(0),                   AT91_SMC_NWESETUP_(4) | AT91_SMC_NCS_WRSETUP_(2) |                   AT91_SMC_NRDSETUP_(4) | AT91_SMC_NCS_RDSETUP_(2));    at91_sys_write(AT91_SMC_PULSE(0),                   AT91_SMC_NWEPULSE_(8) | AT91_SMC_NCS_WRPULSE_(10) |                   AT91_SMC_NRDPULSE_(8) | AT91_SMC_NCS_RDPULSE_(10));    at91_sys_write(AT91_SMC_CYCLE(0),                   AT91_SMC_NWECYCLE_(16) | AT91_SMC_NRDCYCLE_(16));    at91_sys_write(AT91_SMC_MODE(0),                   AT91_SMC_READMODE | AT91_SMC_WRITEMODE |                   AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_BAT_WRITE |                   AT91_SMC_DBW_16 | AT91_SMC_TDF_(1));}

static void at91sam9261ek_nand_hw_init(void){	unsigned long csa;	/* Enable CS3 */	csa = at91_sys_read(AT91_MATRIX_EBICSA);	at91_sys_write(AT91_MATRIX_EBICSA,		       csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);	/* Configure SMC CS3 for NAND/SmartMedia */	at91_sys_write(AT91_SMC_SETUP(3),		       AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |		       AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));	at91_sys_write(AT91_SMC_PULSE(3),		       AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |		       AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));	at91_sys_write(AT91_SMC_CYCLE(3),		       AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));	at91_sys_write(AT91_SMC_MODE(3),		       AT91_SMC_READMODE | AT91_SMC_WRITEMODE |		       AT91_SMC_EXNWMODE_DISABLE |#ifdef CFG_NAND_DBW_16		       AT91_SMC_DBW_16 |#else /* CFG_NAND_DBW_8 */		       AT91_SMC_DBW_8 |#endif		       AT91_SMC_TDF_(2));	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_PIOC);	/* Configure RDY/BSY */	at91_set_gpio_input(AT91_PIN_PC15, 1);	/* Enable NandFlash */	at91_set_gpio_output(AT91_PIN_PC14, 1);	at91_set_A_periph(AT91_PIN_PC0, 0);	/* NANDOE */	at91_set_A_periph(AT91_PIN_PC1, 0);	/* NANDWE */}

static __init void cap9adk_add_device_nor(void){	unsigned long csa;	csa = at91_sys_read(AT91_MATRIX_EBICSA);	at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_VDDIOMSEL_3_3V);	/* set the bus interface characteristics */	at91_sys_write(AT91_SMC_SETUP(0), AT91_SMC_NWESETUP_(4) | AT91_SMC_NCS_WRSETUP_(2)			| AT91_SMC_NRDSETUP_(4) | AT91_SMC_NCS_RDSETUP_(2));	at91_sys_write(AT91_SMC_PULSE(0), AT91_SMC_NWEPULSE_(8) | AT91_SMC_NCS_WRPULSE_(10)			| AT91_SMC_NRDPULSE_(8) | AT91_SMC_NCS_RDPULSE_(10));	at91_sys_write(AT91_SMC_CYCLE(0), AT91_SMC_NWECYCLE_(16) | AT91_SMC_NRDCYCLE_(16));	at91_sys_write(AT91_SMC_MODE(0), AT91_SMC_READMODE | AT91_SMC_WRITEMODE			| AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_BAT_WRITE			| AT91_SMC_DBW_16 | AT91_SMC_TDF_(1));	platform_device_register(&cap9adk_nor_flash);}

static void at91sam9261ek_dm9000_hw_init(void){	/* Configure SMC CS2 for DM9000 */	at91_sys_write(AT91_SMC_SETUP(2),		       AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(0) |		       AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(0));	at91_sys_write(AT91_SMC_PULSE(2),		       AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(8) |		       AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(8));	at91_sys_write(AT91_SMC_CYCLE(2),		       AT91_SMC_NWECYCLE_(16) | AT91_SMC_NRDCYCLE_(16));	at91_sys_write(AT91_SMC_MODE(2),		       AT91_SMC_READMODE | AT91_SMC_WRITEMODE |		       AT91_SMC_EXNWMODE_DISABLE |		       AT91_SMC_BAT_WRITE | AT91_SMC_DBW_16 |		       AT91_SMC_TDF_(1));	/* Configure Reset signal as output */	at91_set_gpio_output(AT91_PIN_PC10, 0);	/* Configure Interrupt pin as input, no pull-up */	at91_set_gpio_input(AT91_PIN_PC11, 0);}

void __init at91_add_device_nand(struct atmel_nand_data *data){	unsigned int csa;	if (!data)		return;	/* enable the address range of CS3 */	csa = at91_ramc_read(0, AT91_EBI_CSA);	at91_ramc_write(0, AT91_EBI_CSA, csa | AT91_EBI_CS3A_SMC_SMARTMEDIA);	/* set the bus interface characteristics */	at91_ramc_write(0, AT91_SMC_CSR(3), AT91_SMC_ACSS_STD | AT91_SMC_DBW_8 | AT91_SMC_WSEN		| AT91_SMC_NWS_(5)		| AT91_SMC_TDF_(1)		| AT91_SMC_RWSETUP_(0)	/* tDS Data Set up Time 30 - ns */		| AT91_SMC_RWHOLD_(1)	/* tDH Data Hold Time 20 - ns */	);	/* enable pin */	if (gpio_is_valid(data->enable_pin))		at91_set_gpio_output(data->enable_pin, 1);	/* ready/busy pin */	if (gpio_is_valid(data->rdy_pin))		at91_set_gpio_input(data->rdy_pin, 1);	/* card detect pin */	if (gpio_is_valid(data->det_pin))		at91_set_gpio_input(data->det_pin, 1);	at91_set_A_periph(AT91_PIN_PC1, 0);		/* SMOE */	at91_set_A_periph(AT91_PIN_PC3, 0);		/* SMWE */	nand_data = *data;	platform_device_register(&at91rm9200_nand_device);}

void __init at91_add_device_nand(struct atmel_nand_data *data){	unsigned int csa;	if (!data)		return;	/* enable the address range of CS3 */	csa = at91_sys_read(AT91_EBI_CSA);	at91_sys_write(AT91_EBI_CSA, csa | AT91_EBI_CS3A_SMC_SMARTMEDIA);	/* set the bus interface characteristics */	at91_sys_write(AT91_SMC_CSR(3), AT91_SMC_ACSS_STD | AT91_SMC_DBW_8 | AT91_SMC_WSEN		| AT91_SMC_NWS_(5)		| AT91_SMC_TDF_(1)		| AT91_SMC_RWSETUP_(0)	/* tDS Data Set up Time 30 - ns */		| AT91_SMC_RWHOLD_(1)	/* tDH Data Hold Time 20 - ns */	);	/* enable pin */	if (data->enable_pin)		at91_set_gpio_output(data->enable_pin, 1);	/* ready/busy pin */	if (data->rdy_pin)		at91_set_gpio_input(data->rdy_pin, 1);	/* card detect pin */	if (data->det_pin)		at91_set_gpio_input(data->det_pin, 1);	at91_set_A_periph(AT91_PIN_PC1, 0);		/* SMOE */	at91_set_A_periph(AT91_PIN_PC3, 0);		/* SMWE */	add_generic_device("atmel_nand", 0, NULL, AT91_CHIPSELECT_3, 0x10,			   IORESOURCE_MEM, data);}

static void at91cap9_nand_hw_init(void){    unsigned long csa;    /* Enable CS3 */    csa = at91_sys_read(AT91_MATRIX_EBICSA);    at91_sys_write(AT91_MATRIX_EBICSA,                   csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA |                   AT91_MATRIX_EBI_VDDIOMSEL_3_3V);    /* Configure SMC CS3 for NAND/SmartMedia */    at91_sys_write(AT91_SMC_SETUP(3),                   AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(1) |                   AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(1));    at91_sys_write(AT91_SMC_PULSE(3),                   AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(6) |                   AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(6));    at91_sys_write(AT91_SMC_CYCLE(3),                   AT91_SMC_NWECYCLE_(8) | AT91_SMC_NRDCYCLE_(8));    at91_sys_write(AT91_SMC_MODE(3),                   AT91_SMC_READMODE | AT91_SMC_WRITEMODE |                   AT91_SMC_EXNWMODE_DISABLE |#ifdef CFG_NAND_DBW_16                   AT91_SMC_DBW_16 |#else /* CFG_NAND_DBW_8 */                   AT91_SMC_DBW_8 |#endif                   AT91_SMC_TDF_(1));    at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_PIOABCD);    /* RDY/BSY is not connected */    /* Enable NandFlash */    at91_set_gpio_output(AT91_PIN_PD15, 1);}

void __bare_init at91sam926x_lowlevel_board_config(struct at91sam926x_lowlevel_cfg *cfg){	/* Disable Watchdog */	cfg->wdt_mr =		AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT |		AT91_WDT_WDV |		AT91_WDT_WDDIS |		AT91_WDT_WDD;	/* define PDC[31:16] as DATA[31:16] */	cfg->ebi_pio_pdr = 0xFFFF0000;	/* no pull-up for D[31:16] */	cfg->ebi_pio_ppudr = 0xFFFF0000;	/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */	cfg->ebi_csa =		AT91_MATRIX_DBPUC | AT91_MATRIX_CS1A_SDRAMC;	cfg->smc_cs = 3;	cfg->smc_mode =		AT91_SMC_READMODE | AT91_SMC_WRITEMODE |		AT91_SMC_DBW_8 |		AT91_SMC_EXNWMODE_DISABLE |		AT91_SMC_TDF_(2);	cfg->smc_cycle =		AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5);	cfg->smc_pulse =		AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |		AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3);	cfg->smc_setup =		AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |		AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0);	cfg->pmc_mor =		AT91_PMC_MOSCEN |		(255 << 8);		/* Main Oscillator Start-up Time */	cfg->pmc_pllar =		AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */		AT91_PMC_OUT |		((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV);	/* PCK/2 = MCK Master Clock from PLLA */	cfg->pmc_mckr1 =		AT91_PMC_CSS_SLOW |		AT91_PMC_PRES_1 |		AT91SAM9_PMC_MDIV_2 |		AT91_PMC_PDIV_1;	/* PCK/2 = MCK Master Clock from PLLA */	cfg->pmc_mckr2 =		AT91_PMC_CSS_PLLA |		AT91_PMC_PRES_1 |		AT91SAM9_PMC_MDIV_2 |		AT91_PMC_PDIV_1;	/* SDRAM */	/* SDRAMC_TR - Refresh Timer register */	cfg->sdrc_tr1 = 0x13C;	/* SDRAMC_CR - Configuration register*/	cfg->sdrc_cr =		AT91_SDRAMC_NC_9 |		AT91_SDRAMC_NR_13 |		AT91_SDRAMC_NB_4 |		AT91_SDRAMC_CAS_2 |		AT91_SDRAMC_DBW_32 |		(2 <<  8) |		/* Write Recovery Delay */		(7 << 12) |		/* Row Cycle Delay */		(2 << 16) |		/* Row Precharge Delay */		(2 << 20) |		/* Row to Column Delay */		(5 << 24) |		/* Active to Precharge Delay */		(8 << 28);		/* Exit Self Refresh to Active Delay */	/* Memory Device Register -> SDRAM */	cfg->sdrc_mdr = AT91_SDRAMC_MD_SDRAM;	/* SDRAM_TR */	cfg->sdrc_tr2 = (MASTER_CLOCK * 7);	/* user reset enable */	cfg->rstc_rmr =		AT91_RSTC_KEY |		AT91_RSTC_PROCRST |		AT91_RSTC_RSTTYP_WAKEUP |		AT91_RSTC_RSTTYP_WATCHDOG;}

static void __init ek_add_device_dm9000(void){	/*	 * Configure Chip-Select 2 on SMC for the DM9000.	 * Note: These timings were calculated for MASTER_CLOCK = 100000000	 *  according to the DM9000 timings.	 */	at91_sys_write(AT91_SMC_SETUP(2), AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(0) | AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(0));	at91_sys_write(AT91_SMC_PULSE(2), AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(8) | AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(8));	at91_sys_write(AT91_SMC_CYCLE(2), AT91_SMC_NWECYCLE_(16) | AT91_SMC_NRDCYCLE_(16));	at91_sys_write(AT91_SMC_MODE(2), AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_BAT_WRITE | AT91_SMC_DBW_16 | AT91_SMC_TDF_(1));	/* Configure Reset signal as output */	at91_set_gpio_output(AT91_PIN_PC10, 0);	/* Configure Interrupt pin as input, no pull-up */	at91_set_gpio_input(AT91_PIN_PC11, 0);	platform_device_register(&at91sam9261_dm9000_device);}

void nandflash_hw_init(void){	unsigned int reg;	/* Configure Nand PINs */	const struct pio_desc nand_pins_hi[] = {		{"NANDOE",	CONFIG_SYS_NAND_OE_PIN,		0, PIO_PULLUP, PIO_PERIPH_A},		{"NANDWE",	CONFIG_SYS_NAND_WE_PIN,		0, PIO_PULLUP, PIO_PERIPH_A},		{"NANDALE",	CONFIG_SYS_NAND_ALE_PIN,	0, PIO_PULLUP, PIO_PERIPH_A},		{"NANDCLE",	CONFIG_SYS_NAND_CLE_PIN,	0, PIO_PULLUP, PIO_PERIPH_A},		{"NANDCS",	CONFIG_SYS_NAND_ENABLE_PIN,	1, PIO_PULLUP, PIO_OUTPUT},		{"D0",	AT91C_PIN_PD(6), 0, PIO_PULLUP, PIO_PERIPH_A},		{"D1",	AT91C_PIN_PD(7), 0, PIO_PULLUP, PIO_PERIPH_A},		{"D2",	AT91C_PIN_PD(8), 0, PIO_PULLUP, PIO_PERIPH_A},		{"D3",	AT91C_PIN_PD(9), 0, PIO_PULLUP, PIO_PERIPH_A},		{"D4",	AT91C_PIN_PD(10), 0, PIO_PULLUP, PIO_PERIPH_A},		{"D5",	AT91C_PIN_PD(11), 0, PIO_PULLUP, PIO_PERIPH_A},		{"D6",	AT91C_PIN_PD(12), 0, PIO_PULLUP, PIO_PERIPH_A},		{"D7",	AT91C_PIN_PD(13), 0, PIO_PULLUP, PIO_PERIPH_A},		{(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},	};	const struct pio_desc nand_pins_lo[] = {		{"NANDOE",	CONFIG_SYS_NAND_OE_PIN,		0, PIO_PULLUP, PIO_PERIPH_A},		{"NANDWE",	CONFIG_SYS_NAND_WE_PIN,		0, PIO_PULLUP, PIO_PERIPH_A},		{"NANDALE",	CONFIG_SYS_NAND_ALE_PIN,	0, PIO_PULLUP, PIO_PERIPH_A},		{"NANDCLE",	CONFIG_SYS_NAND_CLE_PIN,	0, PIO_PULLUP, PIO_PERIPH_A},		{"NANDCS", 	CONFIG_SYS_NAND_ENABLE_PIN,	1, PIO_PULLUP, PIO_OUTPUT},		{(char *)0,	0, 0, PIO_DEFAULT, PIO_PERIPH_A},	};	reg = readl(AT91C_BASE_CCFG + CCFG_EBICSA);	reg |= AT91C_EBI_CS3A_SM;	if (get_cm_rev() == 'A')		reg &= ~AT91C_EBI_NFD0_ON_D16;	else		reg |= (AT91C_EBI_DDR_MP_EN | AT91C_EBI_NFD0_ON_D16);	reg &= ~AT91C_EBI_DRV;	writel(reg, AT91C_BASE_CCFG + CCFG_EBICSA);	/* Configure SMC CS3 */	writel((AT91C_SMC_NWESETUP_(1)		| AT91C_SMC_NCS_WRSETUP_(0)		| AT91C_SMC_NRDSETUP_(2)		| AT91C_SMC_NCS_RDSETUP_(0)),		AT91C_BASE_SMC + SMC_SETUP3);	writel((AT91C_SMC_NWEPULSE_(3)		| AT91C_SMC_NCS_WRPULSE_(5)		| AT91C_SMC_NRDPULSE_(4)		| AT91C_SMC_NCS_RDPULSE_(6)),		AT91C_BASE_SMC + SMC_PULSE3);	writel((AT91C_SMC_NWECYCLE_(5)		| AT91C_SMC_NRDCYCLE_(7)),		AT91C_BASE_SMC + SMC_CYCLE3);	writel((AT91C_SMC_READMODE		| AT91C_SMC_WRITEMODE		| AT91C_SMC_NWAITM_NWAIT_DISABLE		| AT91C_SMC_DBW_WIDTH_BITS_8		| AT91_SMC_TDF_(1)),		AT91C_BASE_SMC + SMC_CTRL3);	/* Configure the PIO controller */	if (get_cm_rev() == 'A')		pio_configure(nand_pins_lo);	else		pio_configure(nand_pins_hi);	pmc_enable_periph_clock(AT91C_ID_PIOC_D);}

void __init at91_add_device_nand(struct at91_nand_data *data){	unsigned long csa;	if (!data)		return;	csa = at91_sys_read(AT91_MATRIX_EBICSA);	at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);	/* set the bus interface characteristics */	at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0)			| AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));	at91_sys_write(AT91_SMC_PULSE(3), AT91_SMC_NWEPULSE_(2) | AT91_SMC_NCS_WRPULSE_(5)			| AT91_SMC_NRDPULSE_(2) | AT91_SMC_NCS_RDPULSE_(5));	at91_sys_write(AT91_SMC_CYCLE(3), AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(7));	at91_sys_write(AT91_SMC_MODE(3), AT91_SMC_DBW_8 | AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_TDF_(1));	/* enable pin */	if (data->enable_pin)		at91_set_gpio_output(data->enable_pin, 1);	/* ready/busy pin */	if (data->rdy_pin)		at91_set_gpio_input(data->rdy_pin, 1);	/* card detect pin */	if (data->det_pin)		at91_set_gpio_input(data->det_pin, 1);	at91_set_A_periph(AT91_PIN_PB4, 0);		/* NANDOE */	at91_set_A_periph(AT91_PIN_PB5, 0);		/* NANDWE */	nand_data = *data;	platform_device_register(&at91_nand_device);}

void __init at91_add_device_nand(struct at91_nand_data *data){	unsigned long csa, mode;	if (!data)		return;	csa = at91_sys_read(AT91_MATRIX_EBICSA);	at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);	/* set the bus interface characteristics */	at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0)			| AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));	at91_sys_write(AT91_SMC_PULSE(3), AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3)			| AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));	at91_sys_write(AT91_SMC_CYCLE(3), AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));	if (data->bus_width_16)		mode = AT91_SMC_DBW_16;	else		mode = AT91_SMC_DBW_8;	at91_sys_write(AT91_SMC_MODE(3), mode | AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_TDF_(2));	/* enable pin */	if (data->enable_pin)		at91_set_gpio_output(data->enable_pin, 1);	/* ready/busy pin */	if (data->rdy_pin)		at91_set_gpio_input(data->rdy_pin, 1);	/* card detect pin */	if (data->det_pin)		at91_set_gpio_input(data->det_pin, 1);	nand_data = *data;	platform_device_register(&at91sam9260_nand_device);}

/* * initialize the som-9g20 for apcc. */static void apcc_init(void){    unsigned int cnt = 10000;    { /* initialize PCK1 - this is output to the FPGA as clock reference.       * select PLLA as clock source (18.432 * 42) and div by 32       * 24.192 mHz.       */	at91_sys_write(AT91_PMC_PCKR(1), AT91_PMC_CSS_PLLA | AT91_PMC_PRES_32);	/* Enable PCK1 output */	at91_sys_write(AT91_PMC_SCER, AT91_PMC_PCK1);	/* Wait for PCK1 to come ready or timeout */	while (cnt-- > 0) {	    volatile unsigned long scsr = at91_sys_read(AT91_PMC_SCSR);	    if ((scsr & AT91_PMC_PCK1RDY) != 0) {		break;	    }	}	/* configure PB31 to be used as PCK1 */	at91_set_A_periph(AT91_PIN_PB31, 0);    }    { /* initialize sensys fpga */	/*	 * Configure CS0 (Chip Select 0) for FPGA (SMC @ FFFFEC00)	 *	 * SETUP - 0x1F3F1F3F	 * PULSE - 0x403F403F	 * CYCLE - 0x013E013E	 * MODE  - 0x000F0003	 */	at91_sys_write(AT91_SMC_SETUP(0),		       AT91_SMC_NWESETUP_(4) | AT91_SMC_NCS_WRSETUP_(4) |		       AT91_SMC_NRDSETUP_(4) | AT91_SMC_NCS_RDSETUP_(4));	at91_sys_write(AT91_SMC_PULSE(0),		       AT91_SMC_NWEPULSE_(20) | AT91_SMC_NCS_WRPULSE_(20) |		       AT91_SMC_NRDPULSE_(22) | AT91_SMC_NCS_RDPULSE_(22));	at91_sys_write(AT91_SMC_CYCLE(0),		       AT91_SMC_NWECYCLE_(35) | AT91_SMC_NRDCYCLE_(29));	at91_sys_write(AT91_SMC_MODE(0),		       AT91_SMC_READMODE | AT91_SMC_WRITEMODE |		       AT91_SMC_EXNWMODE_DISABLE |		       AT91_SMC_DBW_8 |		       AT91_SMC_TDF_(1));    }    {	/* to conserve power, disable the AtoD of phy. 	 */        at91_set_gpio_output(AT91_PIN_PA22, 1);    }#ifdef CONFIG_HW_WATCHDOG    {	/* set up watchdog port */        at91_set_gpio_output(AT91_PIN_PB18, 1);	WATCHDOG_RESET();    }#endif}