自学教程：C++ A_SIZE_8函数代码示例

static int intel_830mp_configure(void){	u32 temp;	u16 temp2;	struct aper_size_info_8 *current_size;	current_size = A_SIZE_8(agp_bridge->current_size);	/* aperture size */	pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);	/* address to map to */	pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);	agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);	/* attbase - aperture base */	pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);	/* agpctrl */	pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);	/* gmch */	pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);	pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp2 | (1 << 9));	/* clear any possible AGP-related error conditions */	pci_write_config_word(agp_bridge->dev, INTEL_I830_ERRSTS, 0x1c);	return 0;}

static int intel_820_configure(void){	u32 temp;	u8 temp2;	struct aper_size_info_8 *current_size;	current_size = A_SIZE_8(agp_bridge->current_size);	/* aperture size */	pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);	/* address to map to */	pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);	agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);	/* attbase - aperture base */	pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);	/* agpctrl */	pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);	/* global enable aperture access */	/* This flag is not accessed through MCHCFG register as in */	/* i850 chipset. */	pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp2);	pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR, temp2 | (1 << 1));	/* clear any possible AGP-related error conditions */	pci_write_config_word(agp_bridge->dev, INTEL_I820_ERRSTS, 0x001c);	return 0;}

static int i460_insert_memory_large_io_page (struct agp_memory *mem,				off_t pg_start, int type){	int i, start_offset, end_offset, idx, pg, num_entries;	struct lp_desc *start, *end, *lp;	void *temp;	if (type >= AGP_USER_TYPES || mem->type >= AGP_USER_TYPES)		return -EINVAL;	temp = agp_bridge->current_size;	num_entries = A_SIZE_8(temp)->num_entries;	/* Figure out what pg_start means in terms of our large GART pages */	start = &i460.lp_desc[pg_start / I460_KPAGES_PER_IOPAGE];	end = &i460.lp_desc[(pg_start + mem->page_count - 1) / I460_KPAGES_PER_IOPAGE];	start_offset = pg_start % I460_KPAGES_PER_IOPAGE;	end_offset = (pg_start + mem->page_count - 1) % I460_KPAGES_PER_IOPAGE;	if (end > i460.lp_desc + num_entries) {		printk(KERN_ERR PFX "Looks like we're out of AGP memory/n");		return -EINVAL;	}	/* Check if the requested region of the aperture is free */	for (lp = start; lp <= end; ++lp) {		if (!lp->alloced_map)			continue;	/* OK, the entire large page is available... */		for (idx = ((lp == start) ? start_offset : 0);		     idx < ((lp == end) ? (end_offset + 1) : I460_KPAGES_PER_IOPAGE);		     idx++)		{			if (test_bit(idx, lp->alloced_map))				return -EBUSY;		}	}	for (lp = start, i = 0; lp <= end; ++lp) {		if (!lp->alloced_map) {			/* Allocate new GART pages... */			if (i460_alloc_large_page(lp) < 0)				return -ENOMEM;			pg = lp - i460.lp_desc;			WR_GATT(pg, agp_bridge->driver->mask_memory(agp_bridge,				lp->paddr, 0));			WR_FLUSH_GATT(pg);		}		for (idx = ((lp == start) ? start_offset : 0);		     idx < ((lp == end) ? (end_offset + 1) : I460_KPAGES_PER_IOPAGE);		     idx++, i++)		{			mem->memory[i] = lp->paddr + idx*PAGE_SIZE;			__set_bit(idx, lp->alloced_map);			++lp->refcount;		}	}	return 0;}

static int intel_7505_configure(void){	u32 temp;	u16 temp2;	struct aper_size_info_8 *current_size;	current_size = A_SIZE_8(agp_bridge->current_size);	/* aperture size */	pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);	/* address to map to */	pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);	agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);	/* attbase - aperture base */	pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);	/* agpctrl */	pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);	/* mchcfg */	pci_read_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, &temp2);	pci_write_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, temp2 | (1 << 9));	return 0;}

static int intel_830mp_configure(void){	u32 temp;	u16 temp2;	struct aper_size_info_8 *current_size;	current_size = A_SIZE_8(agp_bridge->current_size);		pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);		pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);	agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);		pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);		pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);		pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);	pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp2 | (1 << 9));		pci_write_config_word(agp_bridge->dev, INTEL_I830_ERRSTS, 0x1c);	return 0;}

static int intel_845_configure(void){	u32 temp;	u8 temp2;	struct aper_size_info_8 *current_size;	current_size = A_SIZE_8(agp_bridge->current_size);		pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);	if (agp_bridge->apbase_config != 0) {		pci_write_config_dword(agp_bridge->dev, AGP_APBASE,				       agp_bridge->apbase_config);	} else {				pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);		agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);		agp_bridge->apbase_config = temp;	}		pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);		pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);		pci_read_config_byte(agp_bridge->dev, INTEL_I845_AGPM, &temp2);	pci_write_config_byte(agp_bridge->dev, INTEL_I845_AGPM, temp2 | (1 << 1));		pci_write_config_word(agp_bridge->dev, INTEL_I845_ERRSTS, 0x001c);	return 0;}

static int intel_845_configure(void){	u32 temp;	u8 temp2;	struct aper_size_info_8 *current_size;	current_size = A_SIZE_8(agp_bridge->current_size);	/* aperture size */	pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);	if (agp_bridge->apbase_config != 0) {		pci_write_config_dword(agp_bridge->dev, AGP_APBASE,				       agp_bridge->apbase_config);	} else {		/* address to map to */		pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);		agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);		agp_bridge->apbase_config = temp;	}	/* attbase - aperture base */	pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);	/* agpctrl */	pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);	/* agpm */	pci_read_config_byte(agp_bridge->dev, INTEL_I845_AGPM, &temp2);	pci_write_config_byte(agp_bridge->dev, INTEL_I845_AGPM, temp2 | (1 << 1));	/* clear any possible error conditions */	pci_write_config_word(agp_bridge->dev, INTEL_I845_ERRSTS, 0x001c);	return 0;}

static int nvidia_configure(void){	int i, rc, num_dirs;	u32 apbase, aplimit;	struct aper_size_info_8 *current_size;	u32 temp;	current_size = A_SIZE_8(agp_bridge->current_size);	/* aperture size */	pci_write_config_byte(agp_bridge->dev, NVIDIA_0_APSIZE,		current_size->size_value);    /* address to map to */	pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &apbase);	apbase &= PCI_BASE_ADDRESS_MEM_MASK;	agp_bridge->gart_bus_addr = apbase;	aplimit = apbase + (current_size->size * 1024 * 1024) - 1;	pci_write_config_dword(nvidia_private.dev_2, NVIDIA_2_APBASE, apbase);	pci_write_config_dword(nvidia_private.dev_2, NVIDIA_2_APLIMIT, aplimit);	pci_write_config_dword(nvidia_private.dev_3, NVIDIA_3_APBASE, apbase);	pci_write_config_dword(nvidia_private.dev_3, NVIDIA_3_APLIMIT, aplimit);	if (0 != (rc = nvidia_init_iorr(apbase, current_size->size * 1024 * 1024)))		return rc;	/* directory size is 64k */	num_dirs = current_size->size / 64;	nvidia_private.num_active_entries = current_size->num_entries;	nvidia_private.pg_offset = 0;	if (num_dirs == 0) {		num_dirs = 1;		nvidia_private.num_active_entries /= (64 / current_size->size);		nvidia_private.pg_offset = (apbase & (64 * 1024 * 1024 - 1) &			~(current_size->size * 1024 * 1024 - 1)) / PAGE_SIZE;	}	/* attbase */	for (i = 0; i < 8; i++) {		pci_write_config_dword(nvidia_private.dev_2, NVIDIA_2_ATTBASE(i),			(agp_bridge->gatt_bus_addr + (i % num_dirs) * 64 * 1024) | 1);	}	/* gtlb control */	pci_read_config_dword(nvidia_private.dev_2, NVIDIA_2_GARTCTRL, &temp);	pci_write_config_dword(nvidia_private.dev_2, NVIDIA_2_GARTCTRL, temp | 0x11);	/* gart control */	pci_read_config_dword(agp_bridge->dev, NVIDIA_0_APSIZE, &temp);	pci_write_config_dword(agp_bridge->dev, NVIDIA_0_APSIZE, temp | 0x100);	/* map aperture */	nvidia_private.aperture =		(volatile u32 __iomem *) ioremap(apbase, 33 * PAGE_SIZE);	if (!nvidia_private.aperture)		return -ENOMEM;	return 0;}

static void sis_cleanup(void){	struct aper_size_info_8 *previous_size;	previous_size = A_SIZE_8(agp_bridge->previous_size);	pci_write_config_byte(agp_bridge->dev, SIS_APSIZE,			      (previous_size->size_value & ~(0x03)));}

static void intel_8xx_cleanup(void){	u16 temp;	struct aper_size_info_8 *previous_size;	previous_size = A_SIZE_8(agp_bridge->previous_size);	pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);	pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));	pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);}

static void i460_cleanup (void){	struct aper_size_info_8 *previous_size;	previous_size = A_SIZE_8(agp_bridge->previous_size);	i460_write_agpsiz(previous_size->size_value);	if (I460_IO_PAGE_SHIFT > PAGE_SHIFT)		kfree(i460.lp_desc);}

static void via_cleanup(void){	struct aper_size_info_8 *previous_size;	previous_size = A_SIZE_8(agp_bridge->previous_size);	pci_write_config_byte(agp_bridge->dev, VIA_APSIZE,			      previous_size->size_value);	/* Do not disable by writing 0 to VIA_ATTBASE, it screws things up	 * during reinitialization.	 */}

static void intel_820_cleanup(void){	u8 temp;	struct aper_size_info_8 *previous_size;	previous_size = A_SIZE_8(agp_bridge->previous_size);	pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp);	pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR,			temp & ~(1 << 1));	pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,			previous_size->size_value);}

static int sis_configure(void){	u32 temp;	struct aper_size_info_8 *current_size;	current_size = A_SIZE_8(agp_bridge->current_size);	pci_write_config_byte(agp_bridge->dev, SIS_TLBCNTRL, 0x05);	pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);	agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);	pci_write_config_dword(agp_bridge->dev, SIS_ATTBASE,			       agp_bridge->gatt_bus_addr);	pci_write_config_byte(agp_bridge->dev, SIS_APSIZE,			      current_size->size_value);	return 0;}

static int i460_free_gatt_table (struct agp_bridge_data *bridge){	int num_entries, i;	void *temp;	temp = agp_bridge->current_size;	num_entries = A_SIZE_8(temp)->num_entries;	for (i = 0; i < num_entries; ++i)		WR_GATT(i, 0);	WR_FLUSH_GATT(num_entries - 1);	iounmap(i460.gatt);	return 0;}

static int __intel_8xx_fetch_size(u8 temp){	int i;	struct aper_size_info_8 *values;	values = A_SIZE_8(agp_bridge->driver->aperture_sizes);	for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {		if (temp == values[i].size_value) {			agp_bridge->previous_size =				agp_bridge->current_size = (void *) (values + i);			agp_bridge->aperture_size_idx = i;			return values[i].size;		}	}	return 0;}

static int via_fetch_size(void){	int i;	u8 temp;	struct aper_size_info_8 *values;	values = A_SIZE_8(agp_bridge->driver->aperture_sizes);	pci_read_config_byte(agp_bridge->dev, VIA_APSIZE, &temp);	for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {		if (temp == values[i].size_value) {			agp_bridge->previous_size =			    agp_bridge->current_size = (void *) (values + i);			agp_bridge->aperture_size_idx = i;			return values[i].size;		}	}	return 0;}

static int i460_insert_memory_small_io_page (struct agp_memory *mem,				off_t pg_start, int type){	unsigned long paddr, io_pg_start, io_page_size;	int i, j, k, num_entries;	void *temp;	pr_debug("i460_insert_memory_small_io_page(mem=%p, pg_start=%ld, type=%d, paddr0=0x%lx)/n",		 mem, pg_start, type, mem->memory[0]);	if (type >= AGP_USER_TYPES || mem->type >= AGP_USER_TYPES)		return -EINVAL;	io_pg_start = I460_IOPAGES_PER_KPAGE * pg_start;	temp = agp_bridge->current_size;	num_entries = A_SIZE_8(temp)->num_entries;	if ((io_pg_start + I460_IOPAGES_PER_KPAGE * mem->page_count) > num_entries) {		printk(KERN_ERR PFX "Looks like we're out of AGP memory/n");		return -EINVAL;	}	j = io_pg_start;	while (j < (io_pg_start + I460_IOPAGES_PER_KPAGE * mem->page_count)) {		if (!PGE_EMPTY(agp_bridge, RD_GATT(j))) {			pr_debug("i460_insert_memory_small_io_page: GATT[%d]=0x%x is busy/n",				 j, RD_GATT(j));			return -EBUSY;		}		j++;	}	io_page_size = 1UL << I460_IO_PAGE_SHIFT;	for (i = 0, j = io_pg_start; i < mem->page_count; i++) {		paddr = mem->memory[i];		for (k = 0; k < I460_IOPAGES_PER_KPAGE; k++, j++, paddr += io_page_size)			WR_GATT(j, agp_bridge->driver->mask_memory(agp_bridge,				paddr, mem->type));	}	WR_FLUSH_GATT(j - 1);	return 0;}

static int i460_configure (void){	union {		u32 small[2];		u64 large;	} temp;	size_t size;	u8 scratch;	struct aper_size_info_8 *current_size;	temp.large = 0;	current_size = A_SIZE_8(agp_bridge->current_size);	i460_write_agpsiz(current_size->size_value);	/*	 * Do the necessary rigmarole to read all eight bytes of APBASE.	 * This has to be done since the AGP aperture can be above 4GB on	 * 460 based systems.	 */	pci_read_config_dword(agp_bridge->dev, i460.dynamic_apbase, &(temp.small[0]));	pci_read_config_dword(agp_bridge->dev, i460.dynamic_apbase + 4, &(temp.small[1]));	/* Clear BAR control bits */	agp_bridge->gart_bus_addr = temp.large & ~((1UL << 3) - 1);	pci_read_config_byte(agp_bridge->dev, INTEL_I460_GXBCTL, &scratch);	pci_write_config_byte(agp_bridge->dev, INTEL_I460_GXBCTL,			      (scratch & 0x02) | I460_GXBCTL_OOG | I460_GXBCTL_BWC);	/*	 * Initialize partial allocation trackers if a GART page is bigger than a kernel	 * page.	 */	if (I460_IO_PAGE_SHIFT > PAGE_SHIFT) {		size = current_size->num_entries * sizeof(i460.lp_desc[0]);		i460.lp_desc = kzalloc(size, GFP_KERNEL);		if (!i460.lp_desc)			return -ENOMEM;	}	return 0;}

static int via_configure(void){	struct aper_size_info_8 *current_size;	current_size = A_SIZE_8(agp_bridge->current_size);	/* aperture size */	pci_write_config_byte(agp_bridge->dev, VIA_APSIZE,			      current_size->size_value);	/* address to map to */	agp_bridge->gart_bus_addr = pci_bus_address(agp_bridge->dev,						    AGP_APERTURE_BAR);	/* GART control register */	pci_write_config_dword(agp_bridge->dev, VIA_GARTCTRL, 0x0000000f);	/* attbase - aperture GATT base */	pci_write_config_dword(agp_bridge->dev, VIA_ATTBASE,			    (agp_bridge->gatt_bus_addr & 0xfffff000) | 3);	return 0;}

static int via_configure(void){	u32 temp;	struct aper_size_info_8 *current_size;	current_size = A_SIZE_8(agp_bridge->current_size);	/* aperture size */	pci_write_config_byte(agp_bridge->dev, VIA_APSIZE,			      current_size->size_value);	/* address to map too */	pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);	agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);	/* GART control register */	pci_write_config_dword(agp_bridge->dev, VIA_GARTCTRL, 0x0000000f);	/* attbase - aperture GATT base */	pci_write_config_dword(agp_bridge->dev, VIA_ATTBASE,			    (agp_bridge->gatt_bus_addr & 0xfffff000) | 3);	return 0;}

static int nvidia_fetch_size(void){	int i;	u8 size_value;	struct aper_size_info_8 *values;	pci_read_config_byte(agp_bridge->dev, NVIDIA_0_APSIZE, &size_value);	size_value &= 0x0f;	values = A_SIZE_8(agp_bridge->driver->aperture_sizes);	for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {		if (size_value == values[i].size_value) {			agp_bridge->previous_size =				agp_bridge->current_size = (void *) (values + i);			agp_bridge->aperture_size_idx = i;			return values[i].size;		}	}	return 0;}

static int intel_815_configure(void){	u32 temp, addr;	u8 temp2;	struct aper_size_info_8 *current_size;	/* attbase - aperture base */	/* the Intel 815 chipset spec. says that bits 29-31 in the	* ATTBASE register are reserved -> try not to write them */	if (agp_bridge->gatt_bus_addr & INTEL_815_ATTBASE_MASK) {		dev_emerg(&agp_bridge->dev->dev, "gatt bus addr too high");		return -EINVAL;	}	current_size = A_SIZE_8(agp_bridge->current_size);	/* aperture size */	pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,			current_size->size_value);	/* address to map to */	pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);	agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);	pci_read_config_dword(agp_bridge->dev, INTEL_ATTBASE, &addr);	addr &= INTEL_815_ATTBASE_MASK;	addr |= agp_bridge->gatt_bus_addr;	pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, addr);	/* agpctrl */	pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);	/* apcont */	pci_read_config_byte(agp_bridge->dev, INTEL_815_APCONT, &temp2);	pci_write_config_byte(agp_bridge->dev, INTEL_815_APCONT, temp2 | (1 << 1));	/* clear any possible error conditions */	/* Oddness : this chipset seems to have no ERRSTS register ! */	return 0;}

static int sis_fetch_size(void){	u8 temp_size;	int i;	struct aper_size_info_8 *values;	pci_read_config_byte(agp_bridge->dev, SIS_APSIZE, &temp_size);	values = A_SIZE_8(agp_bridge->driver->aperture_sizes);	for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {		if ((temp_size == values[i].size_value) ||		    ((temp_size & ~(0x03)) ==		     (values[i].size_value & ~(0x03)))) {			agp_bridge->previous_size =			    agp_bridge->current_size = (void *) (values + i);			agp_bridge->aperture_size_idx = i;			return values[i].size;		}	}	return 0;}

static int intel_815_configure(void){	u32 temp, addr;	u8 temp2;	struct aper_size_info_8 *current_size;		if (agp_bridge->gatt_bus_addr & INTEL_815_ATTBASE_MASK) {		dev_emerg(&agp_bridge->dev->dev, "gatt bus addr too high");		return -EINVAL;	}	current_size = A_SIZE_8(agp_bridge->current_size);		pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,			current_size->size_value);		pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);	agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);	pci_read_config_dword(agp_bridge->dev, INTEL_ATTBASE, &addr);	addr &= INTEL_815_ATTBASE_MASK;	addr |= agp_bridge->gatt_bus_addr;	pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, addr);		pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);		pci_read_config_byte(agp_bridge->dev, INTEL_815_APCONT, &temp2);	pci_write_config_byte(agp_bridge->dev, INTEL_815_APCONT, temp2 | (1 << 1));			return 0;}

static int i460_remove_memory_large_io_page (struct agp_memory *mem,				off_t pg_start, int type){	int i, pg, start_offset, end_offset, idx, num_entries;	struct lp_desc *start, *end, *lp;	void *temp;	temp = agp_bridge->current_size;	num_entries = A_SIZE_8(temp)->num_entries;	/* Figure out what pg_start means in terms of our large GART pages */	start = &i460.lp_desc[pg_start / I460_KPAGES_PER_IOPAGE];	end = &i460.lp_desc[(pg_start + mem->page_count - 1) / I460_KPAGES_PER_IOPAGE];	start_offset = pg_start % I460_KPAGES_PER_IOPAGE;	end_offset = (pg_start + mem->page_count - 1) % I460_KPAGES_PER_IOPAGE;	for (i = 0, lp = start; lp <= end; ++lp) {		for (idx = ((lp == start) ? start_offset : 0);		     idx < ((lp == end) ? (end_offset + 1) : I460_KPAGES_PER_IOPAGE);		     idx++, i++)		{			mem->pages[i] = NULL;			__clear_bit(idx, lp->alloced_map);			--lp->refcount;		}		/* Free GART pages if they are unused */		if (lp->refcount == 0) {			pg = lp - i460.lp_desc;			WR_GATT(pg, 0);			WR_FLUSH_GATT(pg);			i460_free_large_page(lp);		}	}	return 0;}