自学教程：C++ A_SIZE_LVL2函数代码示例

static int ati_create_gatt_table(struct agp_bridge_data *bridge){	struct aper_size_info_lvl2 *value;	ati_page_map page_dir;	unsigned long addr;	int retval;	u32 temp;	int i;	struct aper_size_info_lvl2 *current_size;	value = A_SIZE_LVL2(agp_bridge->current_size);	retval = ati_create_page_map(&page_dir);	if (retval != 0)		return retval;	retval = ati_create_gatt_pages(value->num_entries / 1024);	if (retval != 0) {		ati_free_page_map(&page_dir);		return retval;	}	agp_bridge->gatt_table_real = (u32 *)page_dir.real;	agp_bridge->gatt_table = (u32 __iomem *) page_dir.remapped;	agp_bridge->gatt_bus_addr = virt_to_gart(page_dir.real);	/* Write out the size register */	current_size = A_SIZE_LVL2(agp_bridge->current_size);	if (is_r200()) {		pci_read_config_dword(agp_bridge->dev, ATI_RS100_APSIZE, &temp);		temp = (((temp & ~(0x0000000e)) | current_size->size_value)			| 0x00000001);		pci_write_config_dword(agp_bridge->dev, ATI_RS100_APSIZE, temp);		pci_read_config_dword(agp_bridge->dev, ATI_RS100_APSIZE, &temp);	} else {		pci_read_config_dword(agp_bridge->dev, ATI_RS300_APSIZE, &temp);		temp = (((temp & ~(0x0000000e)) | current_size->size_value)			| 0x00000001);		pci_write_config_dword(agp_bridge->dev, ATI_RS300_APSIZE, temp);		pci_read_config_dword(agp_bridge->dev, ATI_RS300_APSIZE, &temp);	}	/*	 * Get the address for the gart region.	 * This is a bus address even on the alpha, b/c its	 * used to program the agp master not the cpu	 */	pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);	addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);	agp_bridge->gart_bus_addr = addr;	/* Calculate the agp offset */	for(i = 0; i < value->num_entries / 1024; i++, addr += 0x00400000) {		writel(virt_to_gart(ati_generic_private.gatt_pages[i]->real) | 1,			page_dir.remapped+GET_PAGE_DIR_OFF(addr));		readl(page_dir.remapped+GET_PAGE_DIR_OFF(addr));	/* PCI Posting. */	}	return 0;}

static int ati_fetch_size(void){	int i;	u32 temp;	struct aper_size_info_lvl2 *values;	if (is_r200())		pci_read_config_dword(agp_bridge->dev, ATI_RS100_APSIZE, &temp);	else		pci_read_config_dword(agp_bridge->dev, ATI_RS300_APSIZE, &temp);	temp = (temp & 0x0000000e);	values = A_SIZE_LVL2(agp_bridge->driver->aperture_sizes);	for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {		if (temp == values[i].size_value) {			agp_bridge->previous_size =			    agp_bridge->current_size = (void *) (values + i);			agp_bridge->aperture_size_idx = i;			return values[i].size;		}	}	return 0;}

static int serverworks_fetch_size(void){	int i;	u32 temp;	u32 temp2;	struct aper_size_info_lvl2 *values;	values = A_SIZE_LVL2(agp_bridge->driver->aperture_sizes);	pci_read_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,&temp);	pci_write_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,					SVWRKS_SIZE_MASK);	pci_read_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,&temp2);	pci_write_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,temp);	temp2 &= SVWRKS_SIZE_MASK;	for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {		if (temp2 == values[i].size_value) {			agp_bridge->previous_size =			    agp_bridge->current_size = (void *) (values + i);			agp_bridge->aperture_size_idx = i;			return values[i].size;		}	}	return 0;}

static int serverworks_create_gatt_table(void){	struct aper_size_info_lvl2 *value;	struct serverworks_page_map page_dir;	int retval;	u32 temp;	int i;	value = A_SIZE_LVL2(agp_bridge->current_size);	retval = serverworks_create_page_map(&page_dir);	if (retval != 0) {		return retval;	}	retval = serverworks_create_page_map(&serverworks_private.scratch_dir);	if (retval != 0) {		serverworks_free_page_map(&page_dir);		return retval;	}	/* Create a fake scratch directory */	for(i = 0; i < 1024; i++) {		serverworks_private.scratch_dir.remapped[i] = (unsigned long) agp_bridge->scratch_page;		page_dir.remapped[i] =			virt_to_phys(serverworks_private.scratch_dir.real);		page_dir.remapped[i] |= 0x00000001;	}	retval = serverworks_create_gatt_pages(value->num_entries / 1024);	if (retval != 0) {		serverworks_free_page_map(&page_dir);		serverworks_free_page_map(&serverworks_private.scratch_dir);		return retval;	}	agp_bridge->gatt_table_real = (u32 *)page_dir.real;	agp_bridge->gatt_table = (u32 *)page_dir.remapped;	agp_bridge->gatt_bus_addr = virt_to_phys(page_dir.real);	/* Get the address for the gart region.	 * This is a bus address even on the alpha, b/c its	 * used to program the agp master not the cpu	 */	pci_read_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,&temp);	agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);	/* Calculate the agp offset */		for(i = 0; i < value->num_entries / 1024; i++) {		page_dir.remapped[i] =			virt_to_phys(serverworks_private.gatt_pages[i]->real);		page_dir.remapped[i] |= 0x00000001;	}	return 0;}

static int serverworks_configure(void){	struct aper_size_info_lvl2 *current_size;	u32 temp;	u8 enable_reg;	u16 cap_reg;	current_size = A_SIZE_LVL2(agp_bridge->current_size);	/* Get the memory mapped registers */	pci_read_config_dword(agp_bridge->dev, serverworks_private.mm_addr_ofs, &temp);	temp = (temp & PCI_BASE_ADDRESS_MEM_MASK);	serverworks_private.registers = (volatile u8 *) ioremap(temp, 4096);	if (!serverworks_private.registers) {		printk (KERN_ERR PFX "Unable to ioremap() memory./n");		return -ENOMEM;	}	OUTREG8(serverworks_private.registers, SVWRKS_GART_CACHE, 0x0a);	OUTREG32(serverworks_private.registers, SVWRKS_GATTBASE, 		 agp_bridge->gatt_bus_addr);	cap_reg = INREG16(serverworks_private.registers, SVWRKS_COMMAND);	cap_reg &= ~0x0007;	cap_reg |= 0x4;	OUTREG16(serverworks_private.registers, SVWRKS_COMMAND, cap_reg);	pci_read_config_byte(serverworks_private.svrwrks_dev,			     SVWRKS_AGP_ENABLE, &enable_reg);	enable_reg |= 0x1; /* Agp Enable bit */	pci_write_config_byte(serverworks_private.svrwrks_dev,			      SVWRKS_AGP_ENABLE, enable_reg);	serverworks_tlbflush(NULL);	agp_bridge->capndx = pci_find_capability(serverworks_private.svrwrks_dev, PCI_CAP_ID_AGP);	/* Fill in the mode register */	pci_read_config_dword(serverworks_private.svrwrks_dev,			      agp_bridge->capndx+PCI_AGP_STATUS, &agp_bridge->mode);	pci_read_config_byte(agp_bridge->dev, SVWRKS_CACHING, &enable_reg);	enable_reg &= ~0x3;	pci_write_config_byte(agp_bridge->dev, SVWRKS_CACHING, enable_reg);	pci_read_config_byte(agp_bridge->dev, SVWRKS_FEATURE, &enable_reg);	enable_reg |= (1<<6);	pci_write_config_byte(agp_bridge->dev,SVWRKS_FEATURE, enable_reg);	return 0;}

static int serverworks_configure(void){	struct aper_size_info_lvl2 *current_size;	u32 temp;	u8 enable_reg;	u16 cap_reg;	current_size = A_SIZE_LVL2(agp_bridge->current_size);	/* Get the memory mapped registers */	pci_read_config_dword(agp_bridge->dev, serverworks_private.mm_addr_ofs, &temp);	temp = (temp & PCI_BASE_ADDRESS_MEM_MASK);	serverworks_private.registers = (volatile u8 __iomem *) ioremap(temp, 4096);	if (!serverworks_private.registers) {		dev_err(&agp_bridge->dev->dev, "can't ioremap(%#x)/n", temp);		return -ENOMEM;	}	writeb(0xA, serverworks_private.registers+SVWRKS_GART_CACHE);	readb(serverworks_private.registers+SVWRKS_GART_CACHE);	/* PCI Posting. */	writel(agp_bridge->gatt_bus_addr, serverworks_private.registers+SVWRKS_GATTBASE);	readl(serverworks_private.registers+SVWRKS_GATTBASE);	/* PCI Posting. */	cap_reg = readw(serverworks_private.registers+SVWRKS_COMMAND);	cap_reg &= ~0x0007;	cap_reg |= 0x4;	writew(cap_reg, serverworks_private.registers+SVWRKS_COMMAND);	readw(serverworks_private.registers+SVWRKS_COMMAND);	pci_read_config_byte(serverworks_private.svrwrks_dev,SVWRKS_AGP_ENABLE, &enable_reg);	enable_reg |= 0x1; /* Agp Enable bit */	pci_write_config_byte(serverworks_private.svrwrks_dev,SVWRKS_AGP_ENABLE, enable_reg);	serverworks_tlbflush(NULL);	agp_bridge->capndx = pci_find_capability(serverworks_private.svrwrks_dev, PCI_CAP_ID_AGP);	/* Fill in the mode register */	pci_read_config_dword(serverworks_private.svrwrks_dev,			      agp_bridge->capndx+PCI_AGP_STATUS, &agp_bridge->mode);	pci_read_config_byte(agp_bridge->dev, SVWRKS_CACHING, &enable_reg);	enable_reg &= ~0x3;	pci_write_config_byte(agp_bridge->dev, SVWRKS_CACHING, enable_reg);	pci_read_config_byte(agp_bridge->dev, SVWRKS_FEATURE, &enable_reg);	enable_reg |= (1<<6);	pci_write_config_byte(agp_bridge->dev,SVWRKS_FEATURE, enable_reg);	return 0;}

static int amd_create_gatt_table(struct agp_bridge_data *bridge){	struct aper_size_info_lvl2 *value;	struct amd_page_map page_dir;	unsigned long __iomem *cur_gatt;	unsigned long addr;	int retval;	u32 temp;	int i;	value = A_SIZE_LVL2(agp_bridge->current_size);	retval = amd_create_page_map(&page_dir);	if (retval != 0)		return retval;	retval = amd_create_gatt_pages(value->num_entries / 1024);	if (retval != 0) {		amd_free_page_map(&page_dir);		return retval;	}	agp_bridge->gatt_table_real = (u32 *)page_dir.real;	agp_bridge->gatt_table = (u32 __iomem *)page_dir.remapped;	agp_bridge->gatt_bus_addr = virt_to_phys(page_dir.real);	/* Get the address for the gart region.	 * This is a bus address even on the alpha, b/c its	 * used to program the agp master not the cpu	 */	pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);	addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);	agp_bridge->gart_bus_addr = addr;	/* Calculate the agp offset */	for (i = 0; i < value->num_entries / 1024; i++, addr += 0x00400000) {		writel(virt_to_phys(amd_irongate_private.gatt_pages[i]->real) | 1,			page_dir.remapped+GET_PAGE_DIR_OFF(addr));		readl(page_dir.remapped+GET_PAGE_DIR_OFF(addr));	/* PCI Posting. */	}	for (i = 0; i < value->num_entries; i++) {		addr = (i * PAGE_SIZE) + agp_bridge->gart_bus_addr;		cur_gatt = GET_GATT(addr);		writel(agp_bridge->scratch_page, cur_gatt+GET_GATT_OFF(addr));		readl(cur_gatt+GET_GATT_OFF(addr));	/* PCI Posting. */	}	return 0;}

static int ati_insert_memory(struct agp_memory * mem,			     off_t pg_start, int type){	int i, j, num_entries;	unsigned long __iomem *cur_gatt;	unsigned long addr;	int mask_type;	num_entries = A_SIZE_LVL2(agp_bridge->current_size)->num_entries;	mask_type = agp_generic_type_to_mask_type(mem->bridge, type);	if (mask_type != 0 || type != mem->type)		return -EINVAL;	if (mem->page_count == 0)		return 0;	if ((pg_start + mem->page_count) > num_entries)		return -EINVAL;	j = pg_start;	while (j < (pg_start + mem->page_count)) {		addr = (j * PAGE_SIZE) + agp_bridge->gart_bus_addr;		cur_gatt = GET_GATT(addr);		if (!PGE_EMPTY(agp_bridge,readl(cur_gatt+GET_GATT_OFF(addr))))			return -EBUSY;		j++;	}	if (!mem->is_flushed) {		/*CACHE_FLUSH(); */		global_cache_flush();		mem->is_flushed = true;	}	for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {		addr = (j * PAGE_SIZE) + agp_bridge->gart_bus_addr;		cur_gatt = GET_GATT(addr);		writel(agp_bridge->driver->mask_memory(agp_bridge,							       page_to_phys(mem->pages[i]),						       mem->type),		       cur_gatt+GET_GATT_OFF(addr));	}	readl(GET_GATT(agp_bridge->gart_bus_addr)); /* PCI posting */	agp_bridge->driver->tlb_flush(mem);	return 0;}

static int amd_create_gatt_table(struct agp_bridge_data *bridge){	struct aper_size_info_lvl2 *value;	struct amd_page_map page_dir;	unsigned long __iomem *cur_gatt;	unsigned long addr;	int retval;	u32 temp;	int i;	value = A_SIZE_LVL2(agp_bridge->current_size);	retval = amd_create_page_map(&page_dir);	if (retval != 0)		return retval;	retval = amd_create_gatt_pages(value->num_entries / 1024);	if (retval != 0) {		amd_free_page_map(&page_dir);		return retval;	}	agp_bridge->gatt_table_real = (u32 *)page_dir.real;	agp_bridge->gatt_table = (u32 __iomem *)page_dir.remapped;	agp_bridge->gatt_bus_addr = virt_to_phys(page_dir.real);	pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);	addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);	agp_bridge->gart_bus_addr = addr;		for (i = 0; i < value->num_entries / 1024; i++, addr += 0x00400000) {		writel(virt_to_phys(amd_irongate_private.gatt_pages[i]->real) | 1,			page_dir.remapped+GET_PAGE_DIR_OFF(addr));		readl(page_dir.remapped+GET_PAGE_DIR_OFF(addr));		}	for (i = 0; i < value->num_entries; i++) {		addr = (i * PAGE_SIZE) + agp_bridge->gart_bus_addr;		cur_gatt = GET_GATT(addr);		writel(agp_bridge->scratch_page, cur_gatt+GET_GATT_OFF(addr));		readl(cur_gatt+GET_GATT_OFF(addr));		}	return 0;}

static int serverworks_create_gatt_table(struct agp_bridge_data *bridge){    struct aper_size_info_lvl2 *value;    struct serverworks_page_map page_dir;    int retval;    u32 temp;    int i;    value = A_SIZE_LVL2(agp_bridge->current_size);    retval = serverworks_create_page_map(&page_dir);    if (retval != 0) {        return retval;    }    retval = serverworks_create_page_map(&serverworks_private.scratch_dir);    if (retval != 0) {        serverworks_free_page_map(&page_dir);        return retval;    }    for (i = 0; i < 1024; i++) {        writel(agp_bridge->scratch_page, serverworks_private.scratch_dir.remapped+i);        writel(virt_to_phys(serverworks_private.scratch_dir.real) | 1, page_dir.remapped+i);    }    retval = serverworks_create_gatt_pages(value->num_entries / 1024);    if (retval != 0) {        serverworks_free_page_map(&page_dir);        serverworks_free_page_map(&serverworks_private.scratch_dir);        return retval;    }    agp_bridge->gatt_table_real = (u32 *)page_dir.real;    agp_bridge->gatt_table = (u32 __iomem *)page_dir.remapped;    agp_bridge->gatt_bus_addr = virt_to_phys(page_dir.real);    pci_read_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,&temp);    agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);    for (i = 0; i < value->num_entries / 1024; i++)        writel(virt_to_phys(serverworks_private.gatt_pages[i]->real)|1, page_dir.remapped+i);    return 0;}

static void ati_cleanup(void){	struct aper_size_info_lvl2 *previous_size;	u32 temp;	previous_size = A_SIZE_LVL2(agp_bridge->previous_size);	/* Write back the previous size and disable gart translation */	if (is_r200()) {		pci_read_config_dword(agp_bridge->dev, ATI_RS100_APSIZE, &temp);		temp = ((temp & ~(0x0000000f)) | previous_size->size_value);		pci_write_config_dword(agp_bridge->dev, ATI_RS100_APSIZE, temp);	} else {		pci_read_config_dword(agp_bridge->dev, ATI_RS300_APSIZE, &temp);		temp = ((temp & ~(0x0000000f)) | previous_size->size_value);		pci_write_config_dword(agp_bridge->dev, ATI_RS300_APSIZE, temp);	}	iounmap((volatile u8 __iomem *)ati_generic_private.registers);}

static int amd_irongate_configure(void){	struct aper_size_info_lvl2 *current_size;	u32 temp;	u16 enable_reg;	current_size = A_SIZE_LVL2(agp_bridge->current_size);	if (!amd_irongate_private.registers) {		/* Get the memory mapped registers */		pci_read_config_dword(agp_bridge->dev, AMD_MMBASE, &temp);		temp = (temp & PCI_BASE_ADDRESS_MEM_MASK);		amd_irongate_private.registers = (volatile u8 __iomem *) ioremap(temp, 4096);		if (!amd_irongate_private.registers)			return -ENOMEM;	}	/* Write out the address of the gatt table */	writel(agp_bridge->gatt_bus_addr, amd_irongate_private.registers+AMD_ATTBASE);	readl(amd_irongate_private.registers+AMD_ATTBASE);	/* PCI Posting. */	/* Write the Sync register */	pci_write_config_byte(agp_bridge->dev, AMD_MODECNTL, 0x80);	/* Set indexing mode */	pci_write_config_byte(agp_bridge->dev, AMD_MODECNTL2, 0x00);	/* Write the enable register */	enable_reg = readw(amd_irongate_private.registers+AMD_GARTENABLE);	enable_reg = (enable_reg | 0x0004);	writew(enable_reg, amd_irongate_private.registers+AMD_GARTENABLE);	readw(amd_irongate_private.registers+AMD_GARTENABLE);	/* PCI Posting. */	/* Write out the size register */	pci_read_config_dword(agp_bridge->dev, AMD_APSIZE, &temp);	temp = (((temp & ~(0x0000000e)) | current_size->size_value) | 1);	pci_write_config_dword(agp_bridge->dev, AMD_APSIZE, temp);	/* Flush the tlb */	writel(1, amd_irongate_private.registers+AMD_TLBFLUSH);	readl(amd_irongate_private.registers+AMD_TLBFLUSH);	/* PCI Posting.*/	return 0;}

static int amd_irongate_configure(void){	struct aper_size_info_lvl2 *current_size;	u32 temp;	u16 enable_reg;	current_size = A_SIZE_LVL2(agp_bridge->current_size);	if (!amd_irongate_private.registers) {				pci_read_config_dword(agp_bridge->dev, AMD_MMBASE, &temp);		temp = (temp & PCI_BASE_ADDRESS_MEM_MASK);		amd_irongate_private.registers = (volatile u8 __iomem *) ioremap(temp, 4096);		if (!amd_irongate_private.registers)			return -ENOMEM;	}		writel(agp_bridge->gatt_bus_addr, amd_irongate_private.registers+AMD_ATTBASE);	readl(amd_irongate_private.registers+AMD_ATTBASE);			pci_write_config_byte(agp_bridge->dev, AMD_MODECNTL, 0x80);		pci_write_config_byte(agp_bridge->dev, AMD_MODECNTL2, 0x00);		enable_reg = readw(amd_irongate_private.registers+AMD_GARTENABLE);	enable_reg = (enable_reg | 0x0004);	writew(enable_reg, amd_irongate_private.registers+AMD_GARTENABLE);	readw(amd_irongate_private.registers+AMD_GARTENABLE);			pci_read_config_dword(agp_bridge->dev, AMD_APSIZE, &temp);	temp = (((temp & ~(0x0000000e)) | current_size->size_value) | 1);	pci_write_config_dword(agp_bridge->dev, AMD_APSIZE, temp);		writel(1, amd_irongate_private.registers+AMD_TLBFLUSH);	readl(amd_irongate_private.registers+AMD_TLBFLUSH);		return 0;}

static int serverworks_insert_memory(struct agp_memory *mem,			     off_t pg_start, int type){	int i, j, num_entries;	unsigned long *cur_gatt;	unsigned long addr;	num_entries = A_SIZE_LVL2(agp_bridge->current_size)->num_entries;	if (type != 0 || mem->type != 0) {		return -EINVAL;	}	if ((pg_start + mem->page_count) > num_entries) {		return -EINVAL;	}	j = pg_start;	while (j < (pg_start + mem->page_count)) {		addr = (j * PAGE_SIZE) + agp_bridge->gart_bus_addr;		cur_gatt = SVRWRKS_GET_GATT(addr);		if (!PGE_EMPTY(agp_bridge, cur_gatt[GET_GATT_OFF(addr)])) {			return -EBUSY;		}		j++;	}	if (mem->is_flushed == FALSE) {		global_cache_flush();		mem->is_flushed = TRUE;	}	for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {		addr = (j * PAGE_SIZE) + agp_bridge->gart_bus_addr;		cur_gatt = SVRWRKS_GET_GATT(addr);		cur_gatt[GET_GATT_OFF(addr)] =			agp_bridge->driver->mask_memory(mem->memory[i], mem->type);	}	serverworks_tlbflush(mem);	return 0;}

static int serverworks_insert_memory(struct agp_memory *mem,			     off_t pg_start, int type){	int i, j, num_entries;	unsigned long __iomem *cur_gatt;	unsigned long addr;	num_entries = A_SIZE_LVL2(agp_bridge->current_size)->num_entries;	if (type != 0 || mem->type != 0) {		return -EINVAL;	}	if ((pg_start + mem->page_count) > num_entries) {		return -EINVAL;	}	j = pg_start;	while (j < (pg_start + mem->page_count)) {		addr = (j * PAGE_SIZE) + agp_bridge->gart_bus_addr;		cur_gatt = SVRWRKS_GET_GATT(addr);		if (!PGE_EMPTY(agp_bridge, readl(cur_gatt+GET_GATT_OFF(addr))))			return -EBUSY;		j++;	}	if (!mem->is_flushed) {		global_cache_flush();		mem->is_flushed = true;	}	for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {		addr = (j * PAGE_SIZE) + agp_bridge->gart_bus_addr;		cur_gatt = SVRWRKS_GET_GATT(addr);		writel(agp_bridge->driver->mask_memory(agp_bridge, 				page_to_phys(mem->pages[i]), mem->type),		       cur_gatt+GET_GATT_OFF(addr));	}	serverworks_tlbflush(mem);	return 0;}

static int ati_insert_memory(struct agp_memory * mem,			     off_t pg_start, int type){	int i, j, num_entries;	unsigned long __iomem *cur_gatt;	unsigned long addr;	num_entries = A_SIZE_LVL2(agp_bridge->current_size)->num_entries;	if (type != 0 || mem->type != 0)		return -EINVAL;	if ((pg_start + mem->page_count) > num_entries)		return -EINVAL;	j = pg_start;	while (j < (pg_start + mem->page_count)) {		addr = (j * PAGE_SIZE) + agp_bridge->gart_bus_addr;		cur_gatt = GET_GATT(addr);		if (!PGE_EMPTY(agp_bridge,readl(cur_gatt+GET_GATT_OFF(addr))))			return -EBUSY;		j++;	}	if (mem->is_flushed == FALSE) {		/*CACHE_FLUSH(); */		global_cache_flush();		mem->is_flushed = TRUE;	}	for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {		addr = (j * PAGE_SIZE) + agp_bridge->gart_bus_addr;		cur_gatt = GET_GATT(addr);		writel(agp_bridge->driver->mask_memory(agp_bridge,			mem->memory[i], mem->type), cur_gatt+GET_GATT_OFF(addr));		readl(cur_gatt+GET_GATT_OFF(addr));	/* PCI Posting. */	}	agp_bridge->driver->tlb_flush(mem);	return 0;}