自学教程：C++ soc_is_exynos4212函数代码示例

void s3c_i2c4_cfg_gpio(struct platform_device *dev){	if (soc_is_exynos4210())		s3c_gpio_cfgall_range(EXYNOS4_GPB(2), 2,				      S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);	else if (soc_is_exynos4212() || soc_is_exynos4412())		s3c_gpio_cfgall_range(EXYNOS4_GPB(0), 2,				      S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);	else if (soc_is_exynos5250())		s3c_gpio_cfgall_range(EXYNOS5_GPA2(0), 2,				      S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);	else		pr_err("failed to configure gpio for i2c4/n");}

static int __maybe_unused exynos_usb_hsic_exit(struct platform_device *pdev){	u32 hsic_ctrl;	if (soc_is_exynos4212() || soc_is_exynos4412()) {		exynos_usb_phy_control(USB_PHY_HSIC0			| USB_PHY_HSIC1,			PHY_DISABLE);	} else {		hsic_ctrl = (HSIC_CTRL_REFCLKDIV(0x24) | HSIC_CTRL_REFCLKSEL(0x2) |				HSIC_CTRL_SIDDQ | HSIC_CTRL_FORCESLEEP | HSIC_CTRL_FORCESUSPEND);		writel(hsic_ctrl, EXYNOS5_PHY_HSIC_CTRL1);		writel(hsic_ctrl, EXYNOS5_PHY_HSIC_CTRL2);	}	return 0;}

static int __init exynos_dma_init(void){	if (soc_is_exynos4210()) {		exynos_device_pdma0.dev.platform_data = &exynos4210_pdma0_pdata;		exynos_device_pdma1.dev.platform_data = &exynos4210_pdma1_pdata;	} else if (soc_is_exynos4212() || soc_is_exynos4412()) {		exynos_device_pdma0.dev.platform_data = &exynos4212_pdma0_pdata;		exynos_device_pdma1.dev.platform_data = &exynos4212_pdma1_pdata;	} else if (soc_is_exynos5210() || soc_is_exynos5250()) {		exynos_device_pdma0.dev.platform_data = &exynos5210_pdma0_pdata;		exynos_device_pdma1.dev.platform_data = &exynos5210_pdma1_pdata;	}	platform_add_devices(exynos_dmacs, ARRAY_SIZE(exynos_dmacs));	return 0;}

int s5p_usb_phy_suspend(struct platform_device *pdev, int type){	int ret = 0;#ifdef CONFIG_USB_OHCI_S5P	struct s5p_ohci_hcd *s5p_ohci = platform_get_drvdata(&s5p_device_ohci);	struct usb_hcd *ohci_hcd = s5p_ohci->hcd;	u32 phyclk;#endif	if (exynos_usb_phy_clock_enable(pdev))		return 0;	mutex_lock(&phy_lock);	if (!strcmp(pdev->name, "s5p-ehci"))		clear_bit(HOST_PHY_EHCI, &usb_phy_control.flags);	else if (!strcmp(pdev->name, "s5p-ohci"))		clear_bit(HOST_PHY_OHCI, &usb_phy_control.flags);	if (usb_phy_control.flags)		goto done;	if (type == S5P_USB_PHY_HOST) {		if (soc_is_exynos4210() ||			soc_is_exynos4212() ||			soc_is_exynos4412()) {#ifdef CONFIG_USB_OHCI_S5P			/* Set OHCI clock off when ohci_hcd is suspended */			if (ohci_hcd->state == HC_STATE_SUSPENDED) {				phyclk = readl(EXYNOS4_PHYCLK);				phyclk &= ~(PHY1_COMMON_ON_N);				writel(phyclk, EXYNOS4_PHYCLK);			}			dev_info(&pdev->dev, "host_phy_susp:%d/n",					ohci_hcd->state);#endif			ret = exynos4_usb_phy1_suspend(pdev);		} else			ret = exynos5_usb_phy_host_suspend(pdev);	}done:	mutex_unlock(&phy_lock);	exynos_usb_phy_clock_disable(pdev);	return ret;}

static int exynos_usb_phy_clock_disable(struct platform_device *pdev){	if (!phy_clk) {		if (soc_is_exynos4210() || soc_is_exynos4212() || soc_is_exynos4412())			phy_clk = clk_get(&pdev->dev, "usbotg");		else			phy_clk = clk_get(&pdev->dev, "usbhost");		if (IS_ERR(phy_clk)) {			dev_err(&pdev->dev, "Failed to get phy clock/n");			return PTR_ERR(phy_clk);		}	}	clk_disable(phy_clk);	return 0;}

static int exynos_cpufreq_probe(struct platform_device *pdev){	int ret = -EINVAL;	exynos_info = kzalloc(sizeof(*exynos_info), GFP_KERNEL);	if (!exynos_info)		return -ENOMEM;	exynos_info->dev = &pdev->dev;	if (soc_is_exynos4210())		ret = exynos4210_cpufreq_init(exynos_info);	else if (soc_is_exynos4212() || soc_is_exynos4412())		ret = exynos4x12_cpufreq_init(exynos_info);	else if (soc_is_exynos5250())		ret = exynos5250_cpufreq_init(exynos_info);	else		return 0;	if (ret)		goto err_vdd_arm;	if (exynos_info->set_freq == NULL) {		dev_err(&pdev->dev, "No set_freq function (ERR)/n");		goto err_vdd_arm;	}	arm_regulator = regulator_get(NULL, "vdd_arm");	if (IS_ERR(arm_regulator)) {		dev_err(&pdev->dev, "failed to get resource vdd_arm/n");		goto err_vdd_arm;	}	/* Done here as we want to capture boot frequency */	locking_frequency = clk_get_rate(exynos_info->cpu_clk) / 1000;	if (!cpufreq_register_driver(&exynos_driver))		return 0;	dev_err(&pdev->dev, "failed to register cpufreq driver/n");	regulator_put(arm_regulator);err_vdd_arm:	kfree(exynos_info);	return -EINVAL;}

void __init smp_init_cpus(void){	void __iomem *scu_base = scu_base_addr();	unsigned int i, ncores;	if (soc_is_exynos4210() || soc_is_exynos4212() ||			soc_is_exynos5250() || soc_is_exynos3250())		ncores = 2;	else if (soc_is_exynos4412() || soc_is_exynos5410()		|| soc_is_exynos4415() || soc_is_exynos3470())		ncores = 4;	else if (soc_is_exynos5260())#ifdef CONFIG_EXYNOS5_MP		ncores = NR_CPUS;#else		ncores = read_cpuid_mpidr() & 0x100 ? 4 : 2;#endif	else if (soc_is_exynos5420())

static int exynos_cfg_i2s_gpio(struct platform_device *pdev){	/* configure GPIO for i2s port */	struct exynos_gpio_cfg exynos4_cfg[3] = {				{ EXYNOS4_GPZ(0),  7, S3C_GPIO_SFN(2) },				{ EXYNOS4_GPC0(0), 5, S3C_GPIO_SFN(2) },				{ EXYNOS4_GPC1(0), 5, S3C_GPIO_SFN(2) }	};	struct exynos_gpio_cfg exynos5_cfg[3] = {				{ EXYNOS5_GPZ(0),  7, S3C_GPIO_SFN(2) },				{ EXYNOS5_GPB0(0), 5, S3C_GPIO_SFN(2) },				{ EXYNOS5_GPB1(0), 5, S3C_GPIO_SFN(2) }	};	struct exynos_gpio_cfg exynos5410_cfg[3] = {				{ EXYNOS5410_GPZ(0),  7, S3C_GPIO_SFN(2) },				{ EXYNOS5410_GPB0(0), 5, S3C_GPIO_SFN(2) },				{ EXYNOS5410_GPB1(0), 5, S3C_GPIO_SFN(2) }	};	struct exynos_gpio_cfg exynos5420_cfg[3] = {				{ EXYNOS5420_GPZ(0),  7, S3C_GPIO_SFN(2) },				{ EXYNOS5420_GPB0(0), 5, S3C_GPIO_SFN(2) },				{ EXYNOS5420_GPB1(0), 5, S3C_GPIO_SFN(2) }	};	if (pdev->id < 0 || pdev->id > 2) {		printk(KERN_ERR "Invalid Device %d/n", pdev->id);		return -EINVAL;	}	if (soc_is_exynos5250())		s3c_gpio_cfgpin_range(exynos5_cfg[pdev->id].addr,			exynos5_cfg[pdev->id].num, exynos5_cfg[pdev->id].bit);	else if (soc_is_exynos5410())		s3c_gpio_cfgpin_range(exynos5410_cfg[pdev->id].addr,			exynos5410_cfg[pdev->id].num, exynos5410_cfg[pdev->id].bit);	else if (soc_is_exynos5420())		s3c_gpio_cfgpin_range(exynos5420_cfg[pdev->id].addr,			exynos5420_cfg[pdev->id].num, exynos5420_cfg[pdev->id].bit);	else if (soc_is_exynos4210() || soc_is_exynos4212() || soc_is_exynos4412())		s3c_gpio_cfgpin_range(exynos4_cfg[pdev->id].addr,			exynos4_cfg[pdev->id].num, exynos4_cfg[pdev->id].bit);	return 0;}

void __init s5p_i2c_hdmiphy_set_platdata(struct s3c2410_platform_i2c *pd){	struct s3c2410_platform_i2c *npd;	if (!pd) {		pd = &default_i2c_data;		if (soc_is_exynos4210() ||		    soc_is_exynos4212() || soc_is_exynos4412())			pd->bus_num = 8;		else if (soc_is_s5pv210())			pd->bus_num = 3;		else			pd->bus_num = 0;	}	npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),			       &s5p_device_i2c_hdmiphy);}

int s5p_usb_phy_exit(struct platform_device *pdev, int type){	int ret = -EINVAL;	if (exynos_usb_phy_clock_enable(pdev))		return ret;	mutex_lock(&phy_lock);	if (type == S5P_USB_PHY_HOST) {		if (soc_is_exynos4210())			ret = exynos4_usb_phy1_exit(pdev);		else if (soc_is_exynos4212() || soc_is_exynos4412())			ret = exynos4_usb_phy20_exit(pdev);		else			ret = exynos5_usb_phy20_exit(pdev);		if (!strcmp(pdev->name, "s5p-ehci"))			clear_bit(HOST_PHY_EHCI, &usb_phy_control.flags);		else if (!strcmp(pdev->name, "s5p-ohci"))			clear_bit(HOST_PHY_OHCI, &usb_phy_control.flags);	} else if (type == S5P_USB_PHY_DEVICE) {		/* set default usb phy tune */		if (pdev->dev.platform_data && soc_is_exynos4210())			ret = s5p_usb_phy0_tune(pdev->dev.platform_data, 1);		if (soc_is_exynos4210())			ret = exynos4_usb_phy0_exit(pdev);		else			ret = exynos_usb_dev_phy20_exit(pdev);	} else if (type == S5P_USB_PHY_DRD)		ret = exynos5_usb_phy30_exit(pdev);	else if (type == S5P_USB_PHY_OTGHOST) {		if (soc_is_exynos4210())			ret = exynos4_usb_phy0_exit(pdev);		else			ret = exynos_usb_dev_phy20_exit(pdev);	}	mutex_unlock(&phy_lock);	exynos_usb_phy_clock_disable(pdev);	return ret;}

void exynos4_sys_powerdown_conf(enum sys_powerdown mode){	unsigned int count = entry_cnt;	unsigned int tmp;	for (; count > 0; count--){		if(S5P_XUSBXTI_SYS != exynos4_pmu_config[count - 1].reg){			__raw_writel(exynos4_pmu_config[count - 1].val[mode],					exynos4_pmu_config[count - 1].reg);		}		else if(S5P_XUSBXTI_SYS == exynos4_pmu_config[count - 1].reg){			//printk("++++++++++++Terry++++++++++call_flag=%d , mode=%d /n", tc4_get_call_flg(),mode);			if((tc4_get_call_flg() != 1)||(mode != SYS_SLEEP)){				//printk("%s ------Terry1--------close xclk------tc4_get_call_flg=%d---/n",__func__,tc4_get_call_flg());				__raw_writel(exynos4_pmu_config[count - 1].val[mode],						exynos4_pmu_config[count - 1].reg);			}			else			{				//printk("%s ------Terry2--------close xclk------tc4_get_call_flg=%d---/n",__func__,tc4_get_call_flg());				__raw_writel(0x1, exynos4_pmu_config[count - 1].reg);			}		} 	}	if ((!soc_is_exynos4210()) && (exynos4_is_c2c_use())) {		for (count = 0 ; count < ARRAY_SIZE(exynos4x12_c2c_pmu_conf) ; count++)			__raw_writel(exynos4x12_c2c_pmu_conf[count].val[mode],					exynos4x12_c2c_pmu_conf[count].reg);		if (soc_is_exynos4212())			__raw_writel(exynos4212_c2c_pmu_conf[0].val[mode],					exynos4212_c2c_pmu_conf[0].reg);		for (count = 0 ; count < ARRAY_SIZE(exynos4_config_for_c2c) ; count++) {			printk("exynos4_config_for_c2c /n");			tmp = __raw_readl(exynos4_config_for_c2c[count].reg);			tmp |= exynos4_config_for_c2c[count].val;			__raw_writel(tmp, exynos4_config_for_c2c[count].reg);		}	}}

static int exynos_dwmci_init(u32 slot_id, irq_handler_t handler, void *data){	struct dw_mci *host = (struct dw_mci *)data;	/* Set Phase Shift Register */	if (soc_is_exynos4210()) {		host->pdata->sdr_timing = 0x00010001;		host->pdata->ddr_timing = 0x00020002;	} else if (soc_is_exynos4212() || soc_is_exynos4412()) {		host->pdata->sdr_timing = 0x00010001;		host->pdata->ddr_timing = 0x00010002;	}#ifdef CONFIG_SLP	host->pdata->sdr_timing = 0x00020001;	host->pdata->ddr_timing = 0x00020002;#endif	return 0;}

int __init exynos4_init(void){    unsigned int value;    unsigned int tmp;    unsigned int i;    printk(KERN_INFO "EXYNOS4: Initializing architecture/n");    /* set idle function */    pm_idle = exynos4_idle;    /*     * on exynos4x12, CMU reset system power register should to be set 0x0     */    if (!soc_is_exynos4210()) {        for (i = 0; i < ARRAY_SIZE(exynos4_pmu_init_zero); i++)            __raw_writel(0x0, exynos4_pmu_init_zero[i]);    }    /* set sw_reset function */    s5p_reset_hook = exynos4_sw_reset;    /* Disable auto wakeup from power off mode */    for (i = 0; i < num_possible_cpus(); i++) {        tmp = __raw_readl(S5P_ARM_CORE_OPTION(i));        tmp &= ~S5P_CORE_OPTION_DIS;        __raw_writel(tmp, S5P_ARM_CORE_OPTION(i));    }    if (soc_is_exynos4212() || soc_is_exynos4412()) {        value = __raw_readl(S5P_AUTOMATIC_WDT_RESET_DISABLE);        value &= ~S5P_SYS_WDTRESET;        __raw_writel(value, S5P_AUTOMATIC_WDT_RESET_DISABLE);        value = __raw_readl(S5P_MASK_WDT_RESET_REQUEST);        value &= ~S5P_SYS_WDTRESET;        //__raw_writel(value, S5P_MASK_WDT_RESET_REQUEST);        //Temperory ignore ISP reset, for ISP test. Jiangshanbin120405        __raw_writel((value | (1<< 26)), S5P_MASK_WDT_RESET_REQUEST);    }    return sysdev_register(&exynos4_sysdev);}

static mali_bool mali_dvfs_table_update(void){	unsigned int i;	unsigned int step_num = MALI_DVFS_STEPS;	if(soc_is_exynos4412()) {		/*check it's pega-prime or pega-Q*/		if(samsung_rev() < EXYNOS4412_REV_2_0) {			step_num = MALI_DVFS_STEPS-1;			for (i = 0; i < step_num; i++) {				MALI_PRINT((":::exynos_result_of_asv : %d/n", exynos_result_of_asv));				mali_dvfs[i].vol = asv_3d_volt_4412_9_table[i][exynos_result_of_asv];				MALI_PRINT(("mali_dvfs[%d].vol = %d/n", i, mali_dvfs[i].vol));			}		}		/* For Pega-Prime e-fuse, add 25mV from default ASV table*//*		else if((is_special_flag() >> G3D_LOCK_FLAG) & 0x1) {			for (i = 0; i < step_num; i++) {				MALI_PRINT((":::exynos_result_of_asv : %d/n", exynos_result_of_asv));				mali_dvfs[i].vol = asv_3d_volt_9_table_for_prime[i][exynos_result_of_asv] + 25000;				MALI_PRINT(("mali_dvfs[%d].vol = %d/n", i, mali_dvfs[i].vol));			}		}*/		/* pega-prime default ASV table */		else {			for (i = 0; i < step_num; i++) {				MALI_PRINT((":::exynos_result_of_asv : %d/n", exynos_result_of_asv));				mali_dvfs[i].vol = asv_3d_volt_9_table_for_prime[i][exynos_result_of_asv];				MALI_PRINT(("mali_dvfs[%d].vol = %d/n", i, mali_dvfs[i].vol));			} 		}	}	else if(soc_is_exynos4212()) {		for (i = 0; i < step_num; i++) {			MALI_PRINT((":::exynos_result_of_asv : %d/n", exynos_result_of_asv));			mali_dvfs[i].vol = asv_3d_volt_4212_9_table[i][exynos_result_of_asv];			MALI_PRINT(("mali_dvfs[%d].vol = %d/n", i, mali_dvfs[i].vol));		}	}	return MALI_TRUE;}

static void exynos_usb_mux_change(struct platform_device *pdev, int val){	u32 is_host;	if(val)		return;	if (soc_is_exynos4212() || soc_is_exynos4412()) {		is_host = readl(EXYNOS4_USB_CFG);		writel(val, EXYNOS4_USB_CFG);	} else {		is_host = readl(EXYNOS5_USB_CFG);		writel(val, EXYNOS5_USB_CFG);	}	if (is_host != val)		dev_dbg(&pdev->dev, "Change USB MUX from %s to %s",			is_host ? "Host" : "Device",			val ? "Host" : "Device");}

static int exynos_cpu_boot(int cpu){	/*	 * Exynos3250 doesn't need to send smc command for secondary CPU boot	 * because Exynos3250 removes WFE in secure mode.	 */	if (soc_is_exynos3250())		return 0;	/*	 * The second parameter of SMC_CMD_CPU1BOOT command means CPU id.	 * But, Exynos4212 has only one secondary CPU so second parameter	 * isn't used for informing secure firmware about CPU id.	 */	if (soc_is_exynos4212())		cpu = 0;	exynos_smc(SMC_CMD_CPU1BOOT, cpu, 0, 0);	return 0;}

void __init s5p_hdmi_set_platdata(struct i2c_board_info *hdmiphy_info,				  struct i2c_board_info *mhl_info, int mhl_bus){	struct s5p_hdmi_platform_data *pd = &s5p_hdmi_def_platdata;	if (soc_is_exynos4210() ||	    soc_is_exynos4212() || soc_is_exynos4412())		pd->hdmiphy_bus = 8;	else if (soc_is_s5pv210())		pd->hdmiphy_bus = 3;	else		pd->hdmiphy_bus = 0;	pd->hdmiphy_info = hdmiphy_info;	pd->mhl_info = mhl_info;	pd->mhl_bus = mhl_bus;	s3c_set_platdata(pd, sizeof(struct s5p_hdmi_platform_data),			 &s5p_device_hdmi);}

static int __init exynos4_l2x0_cache_init(void){	/* TAG, Data Latency Control: 2cycle */	__raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);	if (soc_is_exynos4210())		__raw_writel(0x110, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);	else if (soc_is_exynos4212() || soc_is_exynos4412())		__raw_writel(0x120, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);	/* L2X0 Prefetch Control */	__raw_writel(0x30000007, S5P_VA_L2CC + L2X0_PREFETCH_CTRL);	/* L2X0 Power Control */	__raw_writel(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN,		     S5P_VA_L2CC + L2X0_POWER_CTRL);	l2x0_init(S5P_VA_L2CC, 0x7C470001, 0xC200ffff);	return 0;}

int s3cfb_enable_window(struct s3cfb_global *fbdev, int id){	struct s3cfb_window *win = fbdev->fb[id]->par;#ifdef CONFIG_BUSFREQ_OPP	if (soc_is_exynos4212() || soc_is_exynos4412()) {		if (id != CONFIG_FB_S5P_DEFAULT_WINDOW)			dev_lock(fbdev->bus_dev, fbdev->dev, 133133);	}#endif	if (!win->enabled)		atomic_inc(&fbdev->enabled_win);	if (s3cfb_window_on(fbdev, id)) {		win->enabled = 0;		return -EFAULT;	} else {		win->enabled = 1;		return 0;	}}

void __init s3c_csis0_set_platdata(struct s3c_platform_csis *pd){	struct s3c_platform_csis *npd;	if (!pd) {		pd = &default_csis0_data_rev2;	}	npd = kmemdup(pd, sizeof(struct s3c_platform_csis), GFP_KERNEL);	if (!npd) {		printk(KERN_ERR "%s: no memory for platform data/n", __func__);		return;	}	if (soc_is_exynos4212() || soc_is_exynos4412())		npd->srclk_name = "mout_mpll_user";	npd->cfg_gpio = s3c_csis0_cfg_gpio;	npd->cfg_phy_global = s3c_csis0_cfg_phy_global;	npd->clk_on = s3c_csis_clk_on;	npd->clk_off = s3c_csis_clk_off;	s3c_device_csis0.dev.platform_data = npd;}

int s5p_usb_phy_resume(struct platform_device *pdev, int type){    int ret = 0;#ifdef CONFIG_USB_OHCI_S5P    u32 phyclk;#endif    if (exynos_usb_phy_clock_enable(pdev))        return 0;    mutex_lock(&phy_lock);    if (usb_phy_control.flags)        goto done;    if (type == S5P_USB_PHY_HOST) {        if (soc_is_exynos4210() ||                soc_is_exynos4212() ||                soc_is_exynos4412()) {#ifdef CONFIG_USB_OHCI_S5P            phyclk = readl(EXYNOS4_PHYCLK);            phyclk |= PHY1_COMMON_ON_N;            writel(phyclk, EXYNOS4_PHYCLK);#endif            ret = exynos4_usb_phy1_resume(pdev);        } else            ret = exynos5_usb_phy_host_resume(pdev);    }done:    if (!strcmp(pdev->name, "s5p-ehci"))        set_bit(HOST_PHY_EHCI, &usb_phy_control.flags);    else if (!strcmp(pdev->name, "s5p-ohci"))        set_bit(HOST_PHY_OHCI, &usb_phy_control.flags);    mutex_unlock(&phy_lock);    exynos_usb_phy_clock_disable(pdev);    return ret;}

void __init platform_smp_prepare_cpus(unsigned int max_cpus){	int i;	if (soc_is_exynos4210() || soc_is_exynos4212() || soc_is_exynos4412())		scu_enable(scu_base_addr());	for (i = 1; i < max_cpus; i++) {		int pwr_offset = 0;#ifdef CONFIG_ARM_TRUSTZONE		cpu_boot_info[i].boot_base = S5P_VA_SYSRAM_NS + 0x1C;#else		if (soc_is_exynos4210() &&			(samsung_rev() >= EXYNOS4210_REV_1_1))			cpu_boot_info[i].boot_base = EXYNOS_INFORM5;		else			cpu_boot_info[i].boot_base = S5P_VA_SYSRAM;#endif		if (soc_is_exynos4412())			cpu_boot_info[i].boot_base += (0x4 * i);		else if (soc_is_exynos5410()) {			int cluster_id = read_cpuid_mpidr() & 0x100;			if (samsung_rev() < EXYNOS5410_REV_1_0) {				if (cluster_id == 0)					pwr_offset = 4;			} else {				if (cluster_id != 0)					pwr_offset = 4;			}		}		cpu_boot_info[i].power_base =			EXYNOS_ARM_CORE_CONFIGURATION(i + pwr_offset);	}}

int s5p_usb_phy_suspend(struct platform_device *pdev, int type){	int ret = 0;#ifdef CONFIG_USB_OHCI_S5P	struct s5p_ohci_hcd *s5p_ohci = platform_get_drvdata(&s5p_device_ohci);	struct usb_hcd *ohci_hcd = s5p_ohci->hcd;	u32 phyclk;#endif	if (exynos_usb_phy_clock_enable(pdev))		return 0;	mutex_lock(&phy_lock);	if (!strcmp(pdev->name, "s5p-ehci"))		clear_bit(HOST_PHY_EHCI, &usb_phy_control.flags);	else if (!strcmp(pdev->name, "s5p-ohci"))		clear_bit(HOST_PHY_OHCI, &usb_phy_control.flags);	if (usb_phy_control.flags)		goto done;	if (type == S5P_USB_PHY_HOST) {		if (soc_is_exynos4210() ||			soc_is_exynos4212() ||			soc_is_exynos4412())			ret = exynos4_usb_phy1_suspend(pdev);		else			ret = exynos5_usb_phy_host_suspend(pdev);	}done:	mutex_unlock(&phy_lock);	exynos_usb_phy_clock_disable(pdev);	return ret;}

static int __init exynos4_pmu_init(void){	unsigned int i;	if(!soc_is_exynos4210())		exynos4_reset_assert_ctrl(1);	/*	 * on exynos4x12, CMU reset system power register should to be set 0x0	 */	if (!soc_is_exynos4210()) {		for (i = 0; i < ARRAY_SIZE(exynos4_pmu_init_zero); i++)			__raw_writel(0x0, exynos4_pmu_init_zero[i]);	}	if (soc_is_exynos4210()) {		exynos4_pmu_config = exynos4210_pmu_config;		entry_cnt = ARRAY_SIZE(exynos4210_pmu_config);		printk(KERN_INFO "%s: PMU supports 4210(%d)/n",					__func__, entry_cnt);	} else if (soc_is_exynos4212()) {		exynos4_pmu_config = exynos4212_pmu_config;		entry_cnt = ARRAY_SIZE(exynos4212_pmu_config);		printk(KERN_INFO "%s: PMU supports 4212(%d)/n",					__func__, entry_cnt);	} else if (soc_is_exynos4412()) {		exynos4_pmu_config = exynos4412_pmu_config;		entry_cnt = ARRAY_SIZE(exynos4412_pmu_config);		printk(KERN_INFO "%s: PMU supports 4412(%d)/n",					__func__, entry_cnt);	} else {		printk(KERN_INFO "%s: PMU not supported/n", __func__);	}	return 0;}

void __init exynos_dwmci_set_platdata(struct dw_mci_board *pd){	struct dw_mci_board *npd = NULL;	if ((soc_is_exynos4210()) ||		soc_is_exynos4212() || soc_is_exynos4412()) {		npd = s3c_set_platdata(pd, sizeof(struct dw_mci_board), &exynos_device_dwmci);	} else {		printk("dwmci platform data support only exynos4/5!/n");#ifdef CONFIG_SLP	npd = s3c_set_platdata(pd, sizeof(struct dw_mci_board),			&exynos_device_dwmci);#endif	}	if (npd) {	if (!npd->init)		npd->init = exynos_dwmci_init;	if (!npd->get_bus_wd)		npd->get_bus_wd = exynos_dwmci_get_bus_wd;		if (!npd->set_io_timing)			npd->set_io_timing = exynos_dwmci_set_io_timing;	}}

static u32 exynos_usb_phy_set_clock(struct platform_device *pdev){	struct clk *ref_clk;	u32 refclk_freq = 0;	if (soc_is_exynos4210() || soc_is_exynos4212() || soc_is_exynos4412())		ref_clk = clk_get(&pdev->dev, "xusbxti");	else		ref_clk = clk_get(&pdev->dev, "ext_xtal");	if (IS_ERR(ref_clk)) {		dev_err(&pdev->dev, "Failed to get reference clock/n");		return PTR_ERR(ref_clk);	}	if (soc_is_exynos4210()) {		switch (clk_get_rate(ref_clk)) {		case 12 * MHZ:			refclk_freq = EXYNOS4210_CLKSEL_12M;			break;		case 48 * MHZ:			refclk_freq = EXYNOS4210_CLKSEL_48M;			break;		case 24 * MHZ:		default:			/* default reference clock */			refclk_freq = EXYNOS4210_CLKSEL_24M;			break;		}	} else if (soc_is_exynos4212() | soc_is_exynos4412()) {		switch (clk_get_rate(ref_clk)) {		case 96 * 100000:			refclk_freq = EXYNOS4212_CLKSEL_9600K;			break;		case 10 * MHZ:			refclk_freq = EXYNOS4212_CLKSEL_10M;			break;		case 12 * MHZ:			refclk_freq = EXYNOS4212_CLKSEL_12M;			break;		case 192 * 100000:			refclk_freq = EXYNOS4212_CLKSEL_19200K;			break;		case 20 * MHZ:			refclk_freq = EXYNOS4212_CLKSEL_20M;			break;		case 24 * MHZ:		default:			/* default reference clock */			refclk_freq = EXYNOS4212_CLKSEL_24M;			break;		}	} else {		switch (clk_get_rate(ref_clk)) {		case 96 * 100000:			refclk_freq = EXYNOS5_CLKSEL_9600K;			break;		case 10 * MHZ:			refclk_freq = EXYNOS5_CLKSEL_10M;			break;		case 12 * MHZ:			refclk_freq = EXYNOS5_CLKSEL_12M;			break;		case 192 * 100000:			refclk_freq = EXYNOS5_CLKSEL_19200K;			break;		case 20 * MHZ:			refclk_freq = EXYNOS5_CLKSEL_20M;			break;		case 50 * MHZ:			refclk_freq = EXYNOS5_CLKSEL_50M;			break;		case 24 * MHZ:		default:			/* default reference clock */			refclk_freq = EXYNOS5_CLKSEL_24M;			break;		}	}	clk_put(ref_clk);	return refclk_freq;}

static int __init exynos_dma_init(void){	if (of_have_populated_dt())		return 0;	if (soc_is_exynos4210()) {		exynos_pdma0_pdata.nr_valid_peri =			ARRAY_SIZE(exynos4210_pdma0_peri);		exynos_pdma0_pdata.peri_id = exynos4210_pdma0_peri;		exynos_pdma1_pdata.nr_valid_peri =			ARRAY_SIZE(exynos4210_pdma1_peri);		exynos_pdma1_pdata.peri_id = exynos4210_pdma1_peri;	} else if (soc_is_exynos4212() || soc_is_exynos4412()) {		exynos_pdma0_pdata.nr_valid_peri =			ARRAY_SIZE(exynos4212_pdma0_peri);		exynos_pdma0_pdata.peri_id = exynos4212_pdma0_peri;		exynos_pdma1_pdata.nr_valid_peri =			ARRAY_SIZE(exynos4212_pdma1_peri);		exynos_pdma1_pdata.peri_id = exynos4212_pdma1_peri;	} else if (soc_is_exynos4415()) {		exynos_pdma0_pdata.nr_valid_peri =			ARRAY_SIZE(exynos4415_pdma0_peri);		exynos_pdma0_pdata.peri_id = exynos4415_pdma0_peri;		exynos_pdma1_pdata.nr_valid_peri =			ARRAY_SIZE(exynos4415_pdma1_peri);		exynos_pdma1_pdata.peri_id = exynos4415_pdma1_peri;	} else if (soc_is_exynos5250()) {		exynos_pdma0_pdata.nr_valid_peri =			ARRAY_SIZE(exynos5250_pdma0_peri);		exynos_pdma0_pdata.peri_id = exynos5250_pdma0_peri;		exynos_pdma1_pdata.nr_valid_peri =			ARRAY_SIZE(exynos5250_pdma1_peri);		exynos_pdma1_pdata.peri_id = exynos5250_pdma1_peri;	} else if (soc_is_exynos5410()) {		exynos_pdma0_pdata.nr_valid_peri =			ARRAY_SIZE(exynos5410_pdma0_peri);		exynos_pdma0_pdata.peri_id = exynos5410_pdma0_peri;		exynos_pdma1_pdata.nr_valid_peri =			ARRAY_SIZE(exynos5410_pdma1_peri);		exynos_pdma1_pdata.peri_id = exynos5410_pdma1_peri;	} else if (soc_is_exynos5420()) {		exynos_pdma0_pdata.nr_valid_peri =			ARRAY_SIZE(exynos5420_pdma0_peri);		exynos_pdma0_pdata.peri_id = exynos5420_pdma0_peri;		exynos_pdma1_pdata.nr_valid_peri =			ARRAY_SIZE(exynos5420_pdma1_peri);		exynos_pdma1_pdata.peri_id = exynos5420_pdma1_peri;		exynos_adma0_pdata.nr_valid_peri =			ARRAY_SIZE(adma0_peri);		exynos_adma0_pdata.peri_id = adma0_peri;	} else if (soc_is_exynos5260()) {		exynos5260_pdma0_pdata.nr_valid_peri =			ARRAY_SIZE(exynos5260_pdma0_peri);		exynos5260_pdma0_pdata.peri_id = exynos5260_pdma0_peri;	} else if (soc_is_exynos3470()) {		exynos_pdma0_pdata.nr_valid_peri =			ARRAY_SIZE(exynos3470_pdma0_peri);		exynos_pdma0_pdata.peri_id = exynos3470_pdma0_peri;		exynos_pdma1_pdata.nr_valid_peri =			ARRAY_SIZE(exynos3470_pdma1_peri);		exynos_pdma1_pdata.peri_id = exynos3470_pdma1_peri;	} else if (soc_is_exynos3250()) {		exynos_pdma0_pdata.nr_valid_peri =			ARRAY_SIZE(exynos3250_pdma0_peri);		exynos_pdma0_pdata.peri_id = exynos3250_pdma0_peri;		exynos_pdma1_pdata.nr_valid_peri =			ARRAY_SIZE(exynos3250_pdma1_peri);		exynos_pdma1_pdata.peri_id = exynos3250_pdma1_peri;	}	if (soc_is_exynos4210() || soc_is_exynos4212() ||		soc_is_exynos4412() || soc_is_exynos3470()) {		exynos_pdma0_device.res.start = EXYNOS4_PA_PDMA0;		exynos_pdma0_device.res.end = EXYNOS4_PA_PDMA0 + SZ_4K;		exynos_pdma0_device.irq[0] = EXYNOS4_IRQ_PDMA0;		exynos_pdma1_device.res.start = EXYNOS4_PA_PDMA1;		exynos_pdma1_device.res.end = EXYNOS4_PA_PDMA1 + SZ_4K;		exynos_pdma1_device.irq[0] = EXYNOS4_IRQ_PDMA1;		exynos_mdma_device.res.start = EXYNOS4_PA_MDMA1;		exynos_mdma_device.res.end = EXYNOS4_PA_MDMA1 + SZ_4K;		exynos_mdma_device.irq[0] = EXYNOS4_IRQ_MDMA1;	} else if (soc_is_exynos5410() || soc_is_exynos5420()) {		exynos_mdma_device.res.start = EXYNOS5_PA_MDMA0;		exynos_mdma_device.res.end = EXYNOS5_PA_MDMA0 + SZ_4K;		exynos_mdma_device.irq[0] = EXYNOS5_IRQ_MDMA0;	} else if (soc_is_exynos5260()) {		exynos5260_pdma0_device.res.start = EXYNOS5260_PA_PDMA0;		exynos5260_pdma0_device.res.end = EXYNOS5260_PA_PDMA0 + SZ_4K;		exynos5260_pdma0_device.irq[0] = EXYNOS5260_IRQ_PDMA0;		exynos5260_mdma_device.res.start = EXYNOS5260_PA_NS_MDMA0;		exynos5260_mdma_device.res.end = EXYNOS5260_PA_NS_MDMA0 + SZ_4K;		exynos5260_mdma_device.irq[0] = EXYNOS5260_IRQ_MDMA_1;		exynos5260_adma_device.res.start = EXYNOS5260_PA_ADMA0;		exynos5260_adma_device.res.end = EXYNOS5260_PA_ADMA0 + SZ_4K;		exynos5260_adma_device.irq[0] = EXYNOS5260_IRQ_ADMA;	} else if (soc_is_exynos4415()) {		exynos_pdma0_device.res.start = EXYNOS4_PA_PDMA0;		exynos_pdma0_device.res.end = EXYNOS4_PA_PDMA0 + SZ_4K;		exynos_pdma0_device.irq[0] = EXYNOS4_IRQ_PDMA0;		exynos_pdma1_device.res.start = EXYNOS4_PA_PDMA1;//.........这里部分代码省略.........

static int mfc_open(struct inode *inode, struct file *file){	struct mfc_inst_ctx *mfc_ctx;	int ret;	enum mfc_ret_code retcode;	int inst_id;#ifdef CONFIG_EXYNOS_CONTENT_PATH_PROTECTION	struct mfc_alloc_buffer *alloc;#endif	/* prevent invalid reference */	file->private_data = NULL;	mutex_lock(&mfcdev->lock);#if defined(CONFIG_USE_MFC_CMA) && defined(CONFIG_MACH_MEHMET)	if (atomic_read(&mfcdev->inst_cnt) == 0) {		size_t size = 0x02800000;		mfcdev->cma_vaddr = dma_alloc_coherent(mfcdev->device, size,						&mfcdev->cma_dma_addr, 0);		if (!mfcdev->cma_vaddr) {			printk(KERN_ERR "%s: dma_alloc_coherent returns "						"-ENOMEM/n", __func__);			mutex_unlock(&mfcdev->lock);			return -ENOMEM;		}		printk(KERN_INFO "%s[%d] size 0x%x, vaddr 0x%x, base 0x%x/n",					 __func__, __LINE__, (int)size,						(int)mfcdev->cma_vaddr,						(int)mfcdev->cma_dma_addr);	}#endif#ifdef CONFIG_EXYNOS_CONTENT_PATH_PROTECTION	if (mfcdev->drm_playback) {		mfc_err("DRM playback was activated, cannot open no more instance/n");		ret = -EINVAL;		goto err_drm_playback;	}#endif	if (!mfcdev->fw.state) {		if (mfcdev->fw.requesting) {			printk(KERN_INFO "MFC F/W request is on-going, try again/n");			ret = -ENODEV;			goto err_fw_state;		}		printk(KERN_INFO "MFC F/W is not existing, requesting.../n");		ret = request_firmware(&mfcdev->fw.info, MFC_FW_NAME, mfcdev->device);		if (ret < 0) {			printk(KERN_INFO "failed to copy MFC F/W during open/n");			ret = -ENODEV;			goto err_fw_state;		}		if (soc_is_exynos4212() || soc_is_exynos4412()) {			mfcdev->fw.state = mfc_load_firmware(mfcdev->fw.info->data, mfcdev->fw.info->size);			if (!mfcdev->fw.state) {				printk(KERN_ERR "failed to load MFC F/W, MFC will not working/n");				ret = -ENODEV;				goto err_fw_state;			} else {				printk(KERN_INFO "MFC F/W loaded successfully (size: %d)/n", mfcdev->fw.info->size);			}		}	}	if (atomic_read(&mfcdev->inst_cnt) == 0) {#ifdef CONFIG_EXYNOS_CONTENT_PATH_PROTECTION		if (check_magic(mfcdev->drm_info.addr)) {			mfc_dbg("DRM playback starting/n");			clear_magic(mfcdev->drm_info.addr);			mfcdev->drm_playback = 1;			mfc_set_buf_alloc_scheme(MBS_FIRST_FIT);		} else {			/* reload F/W for first instance again */			if (soc_is_exynos4210()) {				mfcdev->fw.state = mfc_load_firmware(mfcdev->fw.info->data, mfcdev->fw.info->size);				if (!mfcdev->fw.state) {					printk(KERN_ERR "failed to reload MFC F/W, MFC will not working/n");					ret = -ENODEV;					goto err_fw_state;				} else {					printk(KERN_INFO "MFC F/W reloaded successfully (size: %d)/n", mfcdev->fw.info->size);				}			}		}#else		/* reload F/W for first instance again */		if (soc_is_exynos4210()) {			mfcdev->fw.state = mfc_load_firmware(mfcdev->fw.info->data, mfcdev->fw.info->size);			if (!mfcdev->fw.state) {				printk(KERN_ERR "failed to reload MFC F/W, MFC will not working/n");				ret = -ENODEV;				goto err_fw_state;			} else {//.........这里部分代码省略.........

static int mfc_open(struct inode *inode, struct file *file){	struct mfc_inst_ctx *mfc_ctx;	int ret;	enum mfc_ret_code retcode;	int inst_id;#ifdef CONFIG_EXYNOS_CONTENT_PATH_PROTECTION	struct mfc_alloc_buffer *alloc;#endif	/* prevent invalid reference */	file->private_data = NULL;	mutex_lock(&mfcdev->lock);#if SUPPORT_SLICE_ENCODING	mfcdev->frame_working_flag = 1;	mfcdev->frame_sys = 0;#endif	if (!mfcdev->fw.state) {		if (mfcdev->fw.requesting) {			printk(KERN_INFO "MFC F/W request is on-going, try again/n");			ret = -ENODEV;			goto err_fw_state;		}		printk(KERN_INFO "MFC F/W is not existing, requesting.../n");		ret = request_firmware(&mfcdev->fw.info, MFC_FW_NAME, mfcdev->device);		if (ret < 0) {			printk(KERN_INFO "failed to copy MFC F/W during open/n");			ret = -ENODEV;			goto err_fw_state;		}		if (soc_is_exynos4212() || soc_is_exynos4412()) {			mfcdev->fw.state = mfc_load_firmware(mfcdev->fw.info->data, mfcdev->fw.info->size);			if (!mfcdev->fw.state) {				printk(KERN_ERR "failed to load MFC F/W, MFC will not working/n");				ret = -ENODEV;				goto err_fw_state;			} else {				printk(KERN_INFO "MFC F/W loaded successfully (size: %d)/n", mfcdev->fw.info->size);			}		}	}	if (atomic_read(&mfcdev->inst_cnt) == 0) {		/* reload F/W for first instance again */		if (soc_is_exynos4210()) {			mfcdev->fw.state = mfc_load_firmware(mfcdev->fw.info->data, mfcdev->fw.info->size);			if (!mfcdev->fw.state) {				printk(KERN_ERR "failed to reload MFC F/W, MFC will not working/n");				ret = -ENODEV;				goto err_fw_state;			} else {				printk(KERN_INFO "MFC F/W reloaded successfully (size: %d)/n", mfcdev->fw.info->size);			}		}#if defined(CONFIG_BUSFREQ_OPP) || defined(CONFIG_BUSFREQ_LOCK_WRAPPER)		dev_lock(mfcdev->bus_dev, mfcdev->device, 133133);#endif#ifdef CONFIG_BUSFREQ		pm_qos_add_request(&bus_qos_pm_qos_req, PM_QOS_BUS_QOS, 1);#endif		ret = mfc_power_on();		if (ret < 0) {			mfc_err("power enable failed/n");			goto err_pwr_enable;		}#ifndef CONFIG_PM_RUNTIME#ifdef SYSMMU_MFC_ON		mfc_clock_on(mfcdev);		s5p_sysmmu_enable(mfcdev->device);#ifdef CONFIG_VIDEO_MFC_VCM_UMP		vcm_set_pgtable_base(VCM_DEV_MFC);#else /* CONFIG_S5P_VMEM or kernel virtual memory allocator */		s5p_sysmmu_set_tablebase_pgd(mfcdev->device,							__pa(swapper_pg_dir));		/*		 * RMVME: the power-gating work really (on <-> off),		 * all TBL entry was invalidated already when the power off		 */		s5p_sysmmu_tlb_invalidate(mfcdev->device, SYSMMU_MFC_R);#endif		mfc_clock_off(mfcdev);#endif#endif		/* MFC hardware initialization */		retcode = mfc_start(mfcdev);		if (retcode != MFC_OK) {			mfc_err("MFC H/W init failed: %d/n", retcode);			ret = -ENODEV;			goto err_start_hw;//.........这里部分代码省略.........