自学教程：C++ soc_is_exynos4412函数代码示例

void __init exynos4_init_irq(void){	int irq;	gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;	gic_init(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);	gic_arch_extn.irq_eoi = exynos4_gic_irq_fix_base;	gic_arch_extn.irq_unmask = exynos4_gic_irq_fix_base;	gic_arch_extn.irq_mask = exynos4_gic_irq_fix_base;	for (irq = 0; irq < MAX_COMBINER_NR; irq++) {		combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),				COMBINER_IRQ(irq, 0));		combiner_cascade_irq(irq, IRQ_SPI(irq));	}	/*	 * The parameters of s5p_init_irq() are for VIC init.	 * Theses parameters should be NULL and 0 because EXYNOS4	 * uses GIC instead of VIC.	 */	s5p_init_irq(NULL, 0);}

static mali_bool mali_dvfs_table_update(void){	unsigned int i;	unsigned int step_num = MALI_DVFS_STEPS;	if(soc_is_exynos4412()) {		if (exynos_armclk_max == 1000000) {			step_num = MALI_DVFS_STEPS - 1;			for (i = 0; i < step_num; i++) {				MALI_PRINT((":::exynos_result_of_asv : %d/n", exynos_result_of_asv));				mali_dvfs[i].vol = asv_3d_volt_9_table_1ghz_type[i][exynos_result_of_asv];				MALI_PRINT(("mali_dvfs[%d].vol = %d 1ghz_type/n", i, mali_dvfs[i].vol));			}		} else if (samsung_rev() >= EXYNOS4412_REV_2_0) {			for (i = 0; i < step_num; i++) {				MALI_PRINT((":::exynos_result_of_asv : %d/n", exynos_result_of_asv));				mali_dvfs[i].vol = asv_3d_volt_9_table_for_prime[i][exynos_result_of_asv];				MALI_PRINT(("mali_dvfs[%d].vol = %d 1.6ghz_type/n", i, mali_dvfs[i].vol));			}		} else {			step_num = MALI_DVFS_STEPS - 1;			for (i = 0; i < step_num; i++) {				MALI_PRINT((":::exynos_result_of_asv : %d/n", exynos_result_of_asv));				mali_dvfs[i].vol = asv_3d_volt_9_table[i][exynos_result_of_asv];				MALI_PRINT(("mali_dvfs[%d].vol = %d 1.4ghz_type/n", i, mali_dvfs[i].vol));			}		}	}	return MALI_TRUE;}

/* * Enable the SCU */void scu_enable(void __iomem *scu_base){	u32 scu_ctrl;#ifdef CONFIG_ARM_ERRATA_764369	/* Cortex-A9 only */	if ((read_cpuid(CPUID_ID) & 0xff0ffff0) == 0x410fc090) {		scu_ctrl = __raw_readl(scu_base + 0x30);		if (!(scu_ctrl & 1))			__raw_writel(scu_ctrl | 0x1, scu_base + 0x30);	}#endif	scu_ctrl = __raw_readl(scu_base + SCU_CTRL);	/* already enabled? */	if (scu_ctrl & 1)		return;	if ((soc_is_exynos4412() && (samsung_rev() >= EXYNOS4412_REV_1_0)) ||		soc_is_exynos4210())		scu_ctrl |= (1<<3);	scu_ctrl |= 1;	__raw_writel(scu_ctrl, scu_base + SCU_CTRL);	/*	 * Ensure that the data accessed by CPU0 before the SCU was	 * initialised is visible to the other CPUs.	 */	flush_cache_all();#ifdef CONFIG_MACH_PX	logbuf_force_unlock();#endif}

int s5p_usb_phy_exit(struct platform_device *pdev, int type){	int ret = -EINVAL;	if (exynos_usb_phy_clock_enable(pdev))		return ret;	mutex_lock(&phy_lock);	if (type == S5P_USB_PHY_HOST) {		if (soc_is_exynos4210())			ret = exynos4_usb_phy1_exit(pdev);		else if (soc_is_exynos4212() || soc_is_exynos4412())			ret = exynos4_usb_phy20_exit(pdev);		else			ret = exynos5_usb_phy20_exit(pdev);		if (!strcmp(pdev->name, "s5p-ehci"))			clear_bit(HOST_PHY_EHCI, &usb_phy_control.flags);		else if (!strcmp(pdev->name, "s5p-ohci"))			clear_bit(HOST_PHY_OHCI, &usb_phy_control.flags);	} else if (type == S5P_USB_PHY_DEVICE) {		if (soc_is_exynos4210())			ret = exynos4_usb_phy0_exit(pdev);		else			ret = exynos_usb_dev_phy20_exit(pdev);	} else if (type == S5P_USB_PHY_DRD)		ret = exynos5_usb_phy30_exit(pdev);	mutex_unlock(&phy_lock);	exynos_usb_phy_clock_disable(pdev);	return ret;}

static int __init exynos4_pmu_init(void){	unsigned int i;	if(!soc_is_exynos4210())		exynos4_reset_assert_ctrl(1);	if (soc_is_exynos4210()) {		exynos4_pmu_config = exynos4210_pmu_config;		entry_cnt = ARRAY_SIZE(exynos4210_pmu_config);		printk(KERN_INFO "%s: PMU supports 4210(%d)/n",					__func__, entry_cnt);	} else if (soc_is_exynos4212()) {		exynos4_pmu_config = exynos4212_pmu_config;		entry_cnt = ARRAY_SIZE(exynos4212_pmu_config);		printk(KERN_INFO "%s: PMU supports 4212(%d)/n",					__func__, entry_cnt);	} else if (soc_is_exynos4412()) {		exynos4_pmu_config = exynos4412_pmu_config;		entry_cnt = ARRAY_SIZE(exynos4412_pmu_config);		printk(KERN_INFO "%s: PMU supports 4412(%d)/n",					__func__, entry_cnt);	} else {		printk(KERN_INFO "%s: PMU not supported/n", __func__);	}	return 0;}

void exynos4_c2c_request_pwr_mode(enum c2c_pwr_mode mode){	exynos4_config_for_c2c[0].val = 0x3;	switch (mode) {	/* If C2C mode is MAXIMAL LATENCY */	case MAX_LATENCY:		exynos4_config_for_c2c[1].val = 0x0;		if (soc_is_exynos4412() && (samsung_rev() < EXYNOS4412_REV_1_0))			exynos4_config_for_c2c[2].val = 0x1;		else			exynos4_config_for_c2c[2].val = 0x0;#ifdef CONFIG_MACH_SMDK4212		exynos4_config_for_c2c[3].val = 0x0;#endif		break;	/* If C2C mode is Minimal or Short LATENCY */	default:		exynos4_config_for_c2c[1].val = 0x3;		exynos4_config_for_c2c[2].val = 0x1;#ifdef CONFIG_MACH_SMDK4212		exynos4_config_for_c2c[3].val = 0x1;#endif		break;	}}

static int exynos_cfg_i2s_gpio(struct platform_device *pdev){	/* configure GPIO for i2s port */	struct exynos_gpio_cfg exynos4_cfg[3] = {				{ EXYNOS4_GPZ(0),  7, S3C_GPIO_SFN(2) },				{ EXYNOS4_GPC0(0), 5, S3C_GPIO_SFN(2) },				{ EXYNOS4_GPC1(0), 5, S3C_GPIO_SFN(2) }	};	struct exynos_gpio_cfg exynos5_cfg[3] = {				{ EXYNOS5_GPZ(0),  7, S3C_GPIO_SFN(2) },				{ EXYNOS5_GPB0(0), 5, S3C_GPIO_SFN(2) },				{ EXYNOS5_GPB1(0), 5, S3C_GPIO_SFN(2) }	};	if (pdev->id < 0 || pdev->id > 2) {		printk(KERN_ERR "Invalid Device %d/n", pdev->id);		return -EINVAL;	}	if (soc_is_exynos4210() || soc_is_exynos4212() || soc_is_exynos4412())		s3c_gpio_cfgpin_range(exynos4_cfg[pdev->id].addr,			exynos4_cfg[pdev->id].num, exynos4_cfg[pdev->id].bit);	else if (soc_is_exynos5250())		s3c_gpio_cfgpin_range(exynos5_cfg[pdev->id].addr,			exynos5_cfg[pdev->id].num, exynos5_cfg[pdev->id].bit);	return 0;}

void s5p_tv_setup(void){	int ret;	/* direct HPD to HDMI chip */	if (soc_is_exynos4412()) {		gpio_request(GPIO_HDMI_HPD, "hpd-plug");		gpio_direction_input(GPIO_HDMI_HPD);		s3c_gpio_cfgpin(GPIO_HDMI_HPD, S3C_GPIO_SFN(0x3));		s3c_gpio_setpull(GPIO_HDMI_HPD, S3C_GPIO_PULL_NONE);	} else if (soc_is_exynos5250()) {		gpio_request(GPIO_HDMI_HPD, "hpd-plug");		gpio_direction_input(GPIO_HDMI_HPD);		s3c_gpio_cfgpin(GPIO_HDMI_HPD, S3C_GPIO_SFN(0x3));		s3c_gpio_setpull(GPIO_HDMI_HPD, S3C_GPIO_PULL_NONE);		/* HDMI CEC */		gpio_request(GPIO_HDMI_CEC, "hdmi-cec");		gpio_direction_input(GPIO_HDMI_CEC);		s3c_gpio_cfgpin(GPIO_HDMI_CEC, S3C_GPIO_SFN(0x3));		s3c_gpio_setpull(GPIO_HDMI_CEC, S3C_GPIO_PULL_NONE);	} else {		printk(KERN_ERR "HPD GPIOs are not defined!/n");	}}

static int __init exynos4_l2x0_cache_init(void){	u32 tag_latency = 0x110;	u32 data_latency = soc_is_exynos4210() ? 0x110 : 0x120;	u32 prefetch = (soc_is_exynos4412() &&			samsung_rev() >= EXYNOS4412_REV_1_0) ?			0x71000007 : 0x30000007;	u32 aux_val = 0x7C470001;	u32 aux_mask = 0xC200FFFF;#ifdef CONFIG_ARM_TRUSTZONE	exynos_smc(SMC_CMD_L2X0SETUP1, tag_latency, data_latency, prefetch);	exynos_smc(SMC_CMD_L2X0SETUP2,		   L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN,		   aux_val, aux_mask);	exynos_smc(SMC_CMD_L2X0INVALL, 0, 0, 0);	exynos_smc(SMC_CMD_L2X0CTRL, 1, 0, 0);#else	__raw_writel(tag_latency, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);	__raw_writel(data_latency, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);	__raw_writel(prefetch, S5P_VA_L2CC + L2X0_PREFETCH_CTRL);	__raw_writel(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN,		     S5P_VA_L2CC + L2X0_POWER_CTRL);#endif	l2x0_init(S5P_VA_L2CC, aux_val, aux_mask);#ifdef CONFIG_ARM_TRUSTZONE#if defined(CONFIG_PL310_ERRATA_588369) || defined(CONFIG_PL310_ERRATA_727915)	outer_cache.set_debug = exynos4_l2x0_set_debug;#endif#endif	return 0;}

void __init smp_init_cpus(void){	void __iomem *scu_base = scu_base_addr();	unsigned int i, ncores;	if (soc_is_exynos4210() || soc_is_exynos4212() ||	    soc_is_exynos5250())		ncores = 2;	else if (soc_is_exynos4412() || soc_is_exynos5410())		ncores = 4;	else		ncores = scu_base ? scu_get_core_count(scu_base) : 1;	/* sanity check */	if (ncores > nr_cpu_ids) {		pr_warn("SMP: %u cores greater than maximum (%u), clipping/n",			ncores, nr_cpu_ids);		ncores = nr_cpu_ids;	}	for (i = 0; i < ncores; i++)		set_cpu_possible(i, true);	set_smp_cross_call(gic_raise_softirq);}

void __init exynos_dwmci_set_platdata(struct dw_mci_board *pd, u32 slot_id){	struct dw_mci_board *npd = NULL;	if ((soc_is_exynos4210()) || soc_is_exynos4212() ||		soc_is_exynos4412()) {		npd = s3c_set_platdata(pd, sizeof(struct dw_mci_board),				&exynos4_device_dwmci);	} else if (soc_is_exynos5250()) {		if (slot_id < ARRAY_SIZE(exynos5_dwmci_devs))			npd = s3c_set_platdata(pd, sizeof(struct dw_mci_board),					       exynos5_dwmci_devs[slot_id]);		else			pr_err("%s: slot %d is not supported/n", __func__,			       slot_id);	}	if (!npd)		return;	if (!npd->init)		npd->init = exynos_dwmci_init;	if (!npd->get_bus_wd)		npd->get_bus_wd = exynos_dwmci_get_bus_wd;	if (!npd->set_io_timing)		npd->set_io_timing = exynos_dwmci_set_io_timing;	if (!npd->get_ocr)		npd->get_ocr = exynos_dwmci_get_ocr;}

void set_exynos_usb_phy_tune(int type){	u32 phytune;	if (soc_is_exynos4412()) {		if (type == S5P_USB_PHY_DEVICE) {			phytune = readl(PHY0_PHYTUNE);			printk(KERN_DEBUG "usb: %s old phy0 tune=0x%x t=%d/n",					__func__, phytune, type);			/* sqrxtune [13:11] 3b110 : -15% */			phytune &= ~(0x7 << 11);			phytune |= (0x6 << 11);			udelay(10);			writel(phytune, PHY0_PHYTUNE);			phytune = readl(PHY0_PHYTUNE);			printk(KERN_DEBUG "usb: %s new phy0 tune=0x%x/n",					__func__, phytune);		} else if (type == S5P_USB_PHY_HOST) {			phytune = readl(PHY1_PHYTUNE);			printk(KERN_DEBUG "usb: %s old phy1 tune=0x%x t=%d/n",					__func__, phytune, type);			/* sqrxtune [13:11] 3b110 : -15% */			phytune &= ~(0x7 << 11);			phytune |= (0x6 << 11);			udelay(10);			writel(phytune, PHY1_PHYTUNE);			phytune = readl(PHY1_PHYTUNE);			printk(KERN_DEBUG "usb: %s new phy1 tune=0x%x/n",					__func__, phytune);		}	} else		printk(KERN_DEBUG "usb: %s it is not exynos4412.(t=%d)/n",				__func__, type);}

static int __init exynos_pmu_init(void){	unsigned int value;	exynos_pmu_config = exynos4210_pmu_config;	if (soc_is_exynos4210()) {		exynos_pmu_config = exynos4210_pmu_config;		pr_info("EXYNOS4210 PMU Initialize/n");	} else if (soc_is_exynos4212() || soc_is_exynos4412()) {		exynos_pmu_config = exynos4x12_pmu_config;		pr_info("EXYNOS4x12 PMU Initialize/n");	} else if (soc_is_exynos5250()) {		/*		 * When SYS_WDTRESET is set, watchdog timer reset request		 * is ignored by power management unit.		 */		value = __raw_readl(EXYNOS5_AUTO_WDTRESET_DISABLE);		value &= ~EXYNOS5_SYS_WDTRESET;		__raw_writel(value, EXYNOS5_AUTO_WDTRESET_DISABLE);		value = __raw_readl(EXYNOS5_MASK_WDTRESET_REQUEST);		value &= ~EXYNOS5_SYS_WDTRESET;		__raw_writel(value, EXYNOS5_MASK_WDTRESET_REQUEST);		exynos_pmu_config = exynos5250_pmu_config;		pr_info("EXYNOS5250 PMU Initialize/n");	} else {		pr_info("EXYNOS: PMU not supported/n");	}	return 0;}

void __cpuinit platform_secondary_init(unsigned int cpu){	/* Enable the full line of zero */	if (soc_is_exynos4210() || soc_is_exynos4212() ||	    soc_is_exynos4412() || soc_is_exynos4415())		enable_cache_foz();	/*	 * if any interrupts are already enabled for the primary	 * core (e.g. timer irq), then they will not have been enabled	 * for us: do so	 */	gic_secondary_init(0);	/*	 * let the primary processor know we're out of the	 * pen, then head off into the C entry point	 */	write_pen_release(-1);#ifdef CONFIG_ARM_TRUSTZONE	clear_boot_flag(cpu, HOTPLUG);#endif	/*	 * Synchronise with the boot thread.	 */	spin_lock(&boot_lock);	spin_unlock(&boot_lock);}

static int __init exynos_pmu_init(void){	unsigned int value;	exynos_pmu_config = exynos4210_pmu_config;	if (soc_is_exynos3250()) {		/*		 * To prevent form issuing new bus request form L2 memory system		 * If core status is power down, should be set '1' to L2 power down		 */		value = __raw_readl(EXYNOS3_ARM_COMMON_OPTION);		value |= EXYNOS3_OPTION_SKIP_DEACTIVATE_ACEACP_IN_PWDN;		__raw_writel(value, EXYNOS3_ARM_COMMON_OPTION);		/* Enable USE_STANDBY_WFI for all CORE */		__raw_writel(S5P_USE_STANDBY_WFI_ALL, S5P_CENTRAL_SEQ_OPTION);		/*		 * Set PSHOLD port for ouput high		 */		value = __raw_readl(S5P_PS_HOLD_CONTROL);		value |= S5P_PS_HOLD_OUTPUT_HIGH;		__raw_writel(value, S5P_PS_HOLD_CONTROL);		/*		 * Enable signal for PSHOLD port		 */		value = __raw_readl(S5P_PS_HOLD_CONTROL);		value |= S5P_PS_HOLD_EN;		__raw_writel(value, S5P_PS_HOLD_CONTROL);		exynos_pmu_config = exynos3250_pmu_config;		pr_info("EXYNOS3250 PMU Initialize/n");	} else if (soc_is_exynos4210()) {		exynos_pmu_config = exynos4210_pmu_config;		pr_info("EXYNOS4210 PMU Initialize/n");	} else if (soc_is_exynos4212() || soc_is_exynos4412()) {		exynos_pmu_config = exynos4x12_pmu_config;		pr_info("EXYNOS4x12 PMU Initialize/n");	} else if (soc_is_exynos5250()) {		/*		 * When SYS_WDTRESET is set, watchdog timer reset request		 * is ignored by power management unit.		 */		value = __raw_readl(EXYNOS5_AUTO_WDTRESET_DISABLE);		value &= ~EXYNOS5_SYS_WDTRESET;		__raw_writel(value, EXYNOS5_AUTO_WDTRESET_DISABLE);		value = __raw_readl(EXYNOS5_MASK_WDTRESET_REQUEST);		value &= ~EXYNOS5_SYS_WDTRESET;		__raw_writel(value, EXYNOS5_MASK_WDTRESET_REQUEST);		exynos_pmu_config = exynos5250_pmu_config;		pr_info("EXYNOS5250 PMU Initialize/n");	} else {		pr_info("EXYNOS: PMU not supported/n");	}	return 0;}

void s3c_i2c4_cfg_gpio(struct platform_device *dev){	if (soc_is_exynos4210())		s3c_gpio_cfgall_range(EXYNOS4_GPB(2), 2,				      S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);	else if (soc_is_exynos4212() || soc_is_exynos4412() || soc_is_exynos4415())		s3c_gpio_cfgall_range(EXYNOS4_GPB(0), 2,				      S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);	else if (soc_is_exynos5250())		s3c_gpio_cfgall_range(EXYNOS5_GPA2(0), 2,				      S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);	else if (soc_is_exynos5260())		s3c_gpio_cfgall_range(EXYNOS5260_GPB5(0), 2,				      S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);	else if (soc_is_exynos3250())		s3c_gpio_cfgall_range(EXYNOS3_GPB(0), 2,				      S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);	else		pr_err("failed to configure gpio for i2c4/n");}

void exynos_sys_powerdown_conf(enum sys_powerdown mode){	unsigned int i;	if (soc_is_exynos3250()) {		exynos3250_init_pmu();		if (mode == SYS_SLEEP) {			__raw_writel(0x00000BB8, EXYNOS3_XUSBXTI_DURATION);			__raw_writel(0x00000BB8, EXYNOS3_XXTI_DURATION);			__raw_writel(0x00001D4C,				     EXYNOS3_EXT_REGULATOR_DURATION);			__raw_writel(0x00001D4C,				     EXYNOS3_EXT_REGULATOR_COREBLK_DURATION);		}	}	if (soc_is_exynos5250())		exynos5_init_pmu();	for (i = 0; (exynos_pmu_config[i].reg != PMU_TABLE_END) ; i++)		__raw_writel(exynos_pmu_config[i].val[mode],				exynos_pmu_config[i].reg);	if (soc_is_exynos4412()) {		for (i = 0; exynos4412_pmu_config[i].reg != PMU_TABLE_END ; i++)			__raw_writel(exynos4412_pmu_config[i].val[mode],				exynos4412_pmu_config[i].reg);	}}

static int __init exynos4_dma_init(void){	if (of_have_populated_dt())		return 0;	if (soc_is_exynos4210()) {		exynos4_pdma0_pdata.nr_valid_peri =			ARRAY_SIZE(exynos4210_pdma0_peri);		exynos4_pdma0_pdata.peri_id = exynos4210_pdma0_peri;		exynos4_pdma1_pdata.nr_valid_peri =			ARRAY_SIZE(exynos4210_pdma1_peri);		exynos4_pdma1_pdata.peri_id = exynos4210_pdma1_peri;	} else if (soc_is_exynos4212() || soc_is_exynos4412()) {		exynos4_pdma0_pdata.nr_valid_peri =			ARRAY_SIZE(exynos4212_pdma0_peri);		exynos4_pdma0_pdata.peri_id = exynos4212_pdma0_peri;		exynos4_pdma1_pdata.nr_valid_peri =			ARRAY_SIZE(exynos4212_pdma1_peri);		exynos4_pdma1_pdata.peri_id = exynos4212_pdma1_peri;	}	dma_cap_set(DMA_SLAVE, exynos4_pdma0_pdata.cap_mask);	dma_cap_set(DMA_CYCLIC, exynos4_pdma0_pdata.cap_mask);	amba_device_register(&exynos4_pdma0_device, &iomem_resource);	dma_cap_set(DMA_SLAVE, exynos4_pdma1_pdata.cap_mask);	dma_cap_set(DMA_CYCLIC, exynos4_pdma1_pdata.cap_mask);	amba_device_register(&exynos4_pdma1_device, &iomem_resource);	dma_cap_set(DMA_MEMCPY, exynos4_mdma1_pdata.cap_mask);	amba_device_register(&exynos4_mdma1_device, &iomem_resource);	return 0;}

int s3cfb_disable_window(struct s3cfb_global *fbdev, int id){	struct s3cfb_window *win = fbdev->fb[id]->par;	if (win->enabled)		atomic_dec(&fbdev->enabled_win);	if (s3cfb_window_off(fbdev, id)) {		win->enabled = 1;		return -EFAULT;	} else {		win->enabled = 0;#ifdef CONFIG_BUSFREQ_OPP		if (soc_is_exynos4212() || soc_is_exynos4412()) {			int win_status = 0, i;			for (i = 0; i < 5; i++) {		/* exynos4x12 has 5 windows */				win = fbdev->fb[i]->par;				if (win->enabled)					win_status |= (1 << i);			}			win_status &= ~(1 << CONFIG_FB_S5P_DEFAULT_WINDOW);			if (0 == win_status)	//check if all window be turned off except default				dev_unlock(fbdev->bus_dev, fbdev->dev);		}#endif		return 0;	}}

static int exynos4_usb_phy0_exit(struct platform_device *pdev){	struct clk *otg_clk;	otg_clk = clk_get(&pdev->dev, "usbotg");	if (IS_ERR(otg_clk)) {		dev_err(&pdev->dev, "Failed to get otg clock/n");		return PTR_ERR(otg_clk);	}	/* unset to normal of PHY0 */	writel((readl(EXYNOS4_PHYPWR) | PHY0_NORMAL_MASK),			EXYNOS4_PHYPWR);	exynos4_usb_phy_control(USB_PHY0, PHY_DISABLE);#ifndef USB_HOST_MODE_ONLY	/* USB MUX change from Device to Host */	if (soc_is_exynos4212() || soc_is_exynos4412())		exynos_usb_mux_change(pdev, 1);#endif	clk_disable(otg_clk);	clk_put(otg_clk);	return 0;}

int s5p_usb_phy_resume(struct platform_device *pdev, int type){	int ret = 0;	if (exynos_usb_phy_clock_enable(pdev))		return 0;	mutex_lock(&phy_lock);	if (usb_phy_control.flags)		goto done;	if (type == S5P_USB_PHY_HOST) {		if (soc_is_exynos4210() ||			soc_is_exynos4212() ||			soc_is_exynos4412())			ret = exynos4_usb_phy1_resume(pdev);		else			ret = exynos5_usb_phy_host_resume(pdev);	}done:	if (!strcmp(pdev->name, "s5p-ehci"))		set_bit(HOST_PHY_EHCI, &usb_phy_control.flags);	else if (!strcmp(pdev->name, "s5p-ohci"))		set_bit(HOST_PHY_OHCI, &usb_phy_control.flags);	mutex_unlock(&phy_lock);	exynos_usb_phy_clock_disable(pdev);	return ret;}

static int __maybe_unused exynos_usb_hsic_init(struct platform_device *pdev){	u32 rstcon, hsic_ctrl;	if (soc_is_exynos4212() || soc_is_exynos4412()) {		exynos_usb_phy_control(USB_PHY_HSIC0			| USB_PHY_HSIC1,			PHY_ENABLE);		/* reset both PHY and Link of Host */		rstcon = readl(EXYNOS4_RSTCON)			| EXYNOS4212_PHY1_HSIC0_SWRST			| EXYNOS4212_PHY1_HSIC1_SWRST;		writel(rstcon, EXYNOS4_RSTCON);		udelay(10);		rstcon &= ~(EXYNOS4212_PHY1_HSIC0_SWRST			| EXYNOS4212_PHY1_HSIC1_SWRST);		writel(rstcon, EXYNOS4_RSTCON);	} else {		/* HSIC phy reset */		hsic_ctrl = (HSIC_CTRL_REFCLKDIV(0x24) | HSIC_CTRL_REFCLKSEL(0x2) |			HSIC_CTRL_PHYSWRST);		writel(hsic_ctrl, EXYNOS5_PHY_HSIC_CTRL1);		writel(hsic_ctrl, EXYNOS5_PHY_HSIC_CTRL2);		udelay(10);		hsic_ctrl &= ~(HSIC_CTRL_PHYSWRST);		writel(hsic_ctrl, EXYNOS5_PHY_HSIC_CTRL1);		writel(hsic_ctrl, EXYNOS5_PHY_HSIC_CTRL2);	}	return 0;}

int s5p_usb_phy_exit(struct platform_device *pdev, int type){	int ret = -EINVAL;	if (exynos_usb_phy_clock_enable(pdev))		return ret;	mutex_lock(&phy_lock);	if (type == S5P_USB_PHY_HOST) {		if (soc_is_exynos4210())			ret = exynos4_usb_phy1_exit(pdev);		else if (soc_is_exynos4212() || soc_is_exynos4412())			ret = exynos4_usb_phy20_exit(pdev);	} else if (type == S5P_USB_PHY_DEVICE) {		if (soc_is_exynos4210())			ret = exynos4_usb_phy0_exit(pdev);		else			ret = exynos_usb_dev_phy20_exit(pdev);	}	mutex_unlock(&phy_lock);	exynos_usb_phy_clock_disable(pdev);	return ret;}

static void exynos_usb_phy_control(enum usb_phy_type phy_type , int on){	if (soc_is_exynos4210()) {		if (phy_type & USB_PHY0)			writel(on, S5P_USBOTG_PHY_CONTROL);		if (phy_type & USB_PHY1)			writel(on, S5P_USBHOST_PHY_CONTROL);	} else if (soc_is_exynos4212() | soc_is_exynos4412()) {		if (phy_type & USB_PHY)			writel(on, S5P_USB_PHY_CONTROL);#ifdef CONFIG_USB_S5P_HSIC0		if (phy_type & USB_PHY_HSIC0)			writel(on, S5P_HSIC_1_PHY_CONTROL);#endif#ifdef CONFIG_USB_S5P_HSIC1		if (phy_type & USB_PHY_HSIC1)			writel(on, S5P_HSIC_2_PHY_CONTROL);#endif	} else {		if (phy_type & USB_PHY0)			writel(on, EXYNOS5_USBDEV_PHY_CONTROL);		if (phy_type & USB_PHY1)			writel(on, EXYNOS5_USBHOST_PHY_CONTROL);	}}

static int exynos_usb_dev_phy20_exit(struct platform_device *pdev){	if (soc_is_exynos4212() || soc_is_exynos4412())		exynos4_usb_phy20_exit(pdev);	return 0;}

static int exynos_pcm_cfg_gpio(struct platform_device *pdev){	/* configure GPIO for pcm port */	struct exynos_gpio_cfg exynos4_cfg[3] = {				{ EXYNOS4_GPZ(0),  5, S3C_GPIO_SFN(3) },				{ EXYNOS4_GPC0(0), 5, S3C_GPIO_SFN(3) },				{ EXYNOS4_GPC1(0), 5, S3C_GPIO_SFN(3) }	};	struct exynos_gpio_cfg exynos5_cfg[3] = {				{ EXYNOS5_GPZ(0),  5, S3C_GPIO_SFN(3) },				{ EXYNOS5_GPB0(0), 5, S3C_GPIO_SFN(3) },				{ EXYNOS5_GPB1(0), 5, S3C_GPIO_SFN(3) }	};	if (pdev->id < 0 || pdev->id > 2) {		printk(KERN_ERR "Invalid Device %d/n", pdev->id);		return -EINVAL;	}	if (soc_is_exynos4210() || soc_is_exynos4212() || soc_is_exynos4412())		s3c_gpio_cfgpin_range(exynos4_cfg[pdev->id].addr,			exynos4_cfg[pdev->id].num, exynos4_cfg[pdev->id].bit);	else if (soc_is_exynos5250())		s3c_gpio_cfgpin_range(exynos5_cfg[pdev->id].addr,			exynos5_cfg[pdev->id].num, exynos5_cfg[pdev->id].bit);#ifdef CONFIG_SND_SOC_BCM4334	/* these are temporary settings, electrical characterics of pcm port should be checked. */	if (soc_is_exynos4412() && pdev->id == 1) {		s3c_gpio_setpull(EXYNOS4_GPC0(0), S3C_GPIO_PULL_NONE);		s5p_gpio_set_drvstr(EXYNOS4_GPC0(0), S5P_GPIO_DRVSTR_LV1);		s3c_gpio_cfgpin(EXYNOS4_GPC0(1), 0);		s3c_gpio_setpull(EXYNOS4_GPC0(2), S3C_GPIO_PULL_NONE);		s5p_gpio_set_drvstr(EXYNOS4_GPC0(2), S5P_GPIO_DRVSTR_LV4);		s3c_gpio_setpull(EXYNOS4_GPC0(3), S3C_GPIO_PULL_NONE);		s5p_gpio_set_drvstr(EXYNOS4_GPC0(3), S5P_GPIO_DRVSTR_LV1);		s3c_gpio_setpull(EXYNOS4_GPC0(4), S3C_GPIO_PULL_NONE);		s5p_gpio_set_drvstr(EXYNOS4_GPC0(4), S5P_GPIO_DRVSTR_LV1);	}#endif	return 0;}

static void exynos4_usb_phy_control(enum usb_phy_type phy_type , int on){	spin_lock(&phy_lock);	if (soc_is_exynos4210()) {		if (phy_type & USB_PHY0) {			if (on == PHY_ENABLE && (usb_phy_control.phy0_usage++) == 0)				writel(PHY_ENABLE, S5P_USBOTG_PHY_CONTROL);			else if (on == PHY_DISABLE && (--usb_phy_control.phy0_usage) == 0)				writel(PHY_DISABLE, S5P_USBOTG_PHY_CONTROL);		}		if (phy_type & USB_PHY1) {			if (on == PHY_ENABLE && (usb_phy_control.phy1_usage++) == 0)				writel(PHY_ENABLE, S5P_USBHOST_PHY_CONTROL);			else if (on == PHY_DISABLE && (--usb_phy_control.phy1_usage) == 0)				writel(PHY_DISABLE, S5P_USBHOST_PHY_CONTROL);		}	} else if (soc_is_exynos4212() | soc_is_exynos4412()){		if (phy_type & USB_PHY) {			if (on == PHY_ENABLE && (usb_phy_control.phy0_usage++) == 0)				writel(PHY_ENABLE, S5P_USB_PHY_CONTROL);			else if (on == PHY_DISABLE && (--usb_phy_control.phy0_usage) == 0)				writel(PHY_DISABLE, S5P_USB_PHY_CONTROL);		}#ifdef CONFIG_USB_S5P_HSIC0		if (phy_type & USB_PHY_HSIC0) {			if (on == PHY_ENABLE && (usb_phy_control.phy1_usage++) == 0)				writel(PHY_ENABLE, S5P_HSIC_1_PHY_CONTROL);			else if (on == PHY_DISABLE && (--usb_phy_control.phy1_usage) == 0)				writel(PHY_DISABLE, S5P_HSIC_1_PHY_CONTROL);		}#endif#ifdef CONFIG_USB_S5P_HSIC1		if (phy_type & USB_PHY_HSIC1) {			if (on == PHY_ENABLE && (usb_phy_control.phy2_usage++) == 0)				writel(PHY_ENABLE, S5P_HSIC_2_PHY_CONTROL);			else if (on == PHY_DISABLE && (--usb_phy_control.phy2_usage) == 0)				writel(PHY_DISABLE, S5P_HSIC_2_PHY_CONTROL);		}#endif	} else {		if (phy_type & USB_PHY0) {			if (on == PHY_ENABLE && (usb_phy_control.phy0_usage++) == 0)				writel(PHY_ENABLE, EXYNOS5_USBDEV_PHY_CONTROL);			else if (on == PHY_DISABLE && (--usb_phy_control.phy0_usage) == 0)				writel(PHY_DISABLE, EXYNOS5_USBDEV_PHY_CONTROL);		}		if (phy_type & USB_PHY1) {			if (on == PHY_ENABLE && (usb_phy_control.phy1_usage++) == 0)				writel(PHY_ENABLE, EXYNOS5_USBHOST_PHY_CONTROL);			else if (on == PHY_DISABLE && (--usb_phy_control.phy1_usage) == 0)				writel(PHY_DISABLE, EXYNOS5_USBHOST_PHY_CONTROL);		}	}	spin_unlock(&phy_lock);}

/** * setup_sysmmu_owner *           - make a relationship between System MMU and its master device * * This function changes the device hierarchy of the both of System MMU and * its master device that is specified by platfor_set_sysmmu(). * It must be ensured that this function is called after the both of System MMU * and its master device is registered. * It must be also ensured that this function is called before the both devices * are probe()ed since it is not correct to change the hierarchy of a probe()ed * device. */static int __init setup_sysmmu_owner(void){	if (soc_is_exynos5250() || soc_is_exynos5410())		exynos5_sysmmu_init();	else if (soc_is_exynos4412() || soc_is_exynos4212())		exynos4_sysmmu_init();	return 0;}

int s5p_usb_phy_exit(struct platform_device *pdev, int type){	if (type == S5P_USB_PHY_HOST) {		if (soc_is_exynos4210() || soc_is_exynos4212() || soc_is_exynos4412())			return exynos4_usb_phy1_exit(pdev);		else			return exynos5_usb_phy20_exit(pdev);	} else if (type == S5P_USB_PHY_DEVICE) {		if (soc_is_exynos4210() || soc_is_exynos4212() || soc_is_exynos4412())			return exynos4_usb_phy0_exit(pdev);		else			return exynos5_usb_dev_phy20_exit(pdev);	} else if (type == S5P_USB_PHY_DRD) {		return exynos5_usb_phy30_exit(pdev);	}	return -EINVAL;}

/** * exynos_check_usb_op - Check usb operation * * USB operation is checked for AP Power mode. * NOTE: Should be checked before Entering AP power mode. * exynos4 - USB Host & Device * exynos5 - USB Host & Device & DRD * * return 1 : operation, 0 : stop. */int exynos_check_usb_op(void){	if (soc_is_exynos4210() ||	    soc_is_exynos4212() ||	    soc_is_exynos4412())		return exynos4_check_usb_op();	else		return exynos5_check_usb_op();}