自学教程：C++ sysbus_connect_irq函数代码示例

static void xtfpga_net_init(MemoryRegion *address_space,        hwaddr base,        hwaddr descriptors,        hwaddr buffers,        qemu_irq irq, NICInfo *nd){    DeviceState *dev;    SysBusDevice *s;    MemoryRegion *ram;    dev = qdev_create(NULL, "open_eth");    qdev_set_nic_properties(dev, nd);    qdev_init_nofail(dev);    s = SYS_BUS_DEVICE(dev);    sysbus_connect_irq(s, 0, irq);    memory_region_add_subregion(address_space, base,            sysbus_mmio_get_region(s, 0));    memory_region_add_subregion(address_space, descriptors,            sysbus_mmio_get_region(s, 1));    ram = g_malloc(sizeof(*ram));    memory_region_init_ram_nomigrate(ram, OBJECT(s), "open_eth.ram", 16384,                           &error_fatal);    vmstate_register_ram_global(ram);    memory_region_add_subregion(address_space, buffers, ram);}

static void init_cpus(const char *cpu_model, const char *privdev,                      hwaddr periphbase, qemu_irq *pic, bool secure){    ObjectClass *cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model);    DeviceState *dev;    SysBusDevice *busdev;    int n;    if (!cpu_oc) {        fprintf(stderr, "Unable to find CPU definition/n");        exit(1);    }    /* Create the actual CPUs */    for (n = 0; n < smp_cpus; n++) {        Object *cpuobj = object_new(object_class_get_name(cpu_oc));        Error *err = NULL;        if (!secure) {            object_property_set_bool(cpuobj, false, "has_el3", NULL);        }        if (object_property_find(cpuobj, "reset-cbar", NULL)) {            object_property_set_int(cpuobj, periphbase,                                    "reset-cbar", &error_abort);        }        object_property_set_bool(cpuobj, true, "realized", &err);        if (err) {            error_report_err(err);            exit(1);        }    }    /* Create the private peripheral devices (including the GIC);     * this must happen after the CPUs are created because a15mpcore_priv     * wires itself up to the CPU's generic_timer gpio out lines.     */    dev = qdev_create(NULL, privdev);    qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);    qdev_init_nofail(dev);    busdev = SYS_BUS_DEVICE(dev);    sysbus_mmio_map(busdev, 0, periphbase);    /* Interrupts [42:0] are from the motherboard;     * [47:43] are reserved; [63:48] are daughterboard     * peripherals. Note that some documentation numbers     * external interrupts starting from 32 (because there     * are internal interrupts 0..31).     */    for (n = 0; n < 64; n++) {        pic[n] = qdev_get_gpio_in(dev, n);    }    /* Connect the CPUs to the GIC */    for (n = 0; n < smp_cpus; n++) {        DeviceState *cpudev = DEVICE(qemu_get_cpu(n));        sysbus_connect_irq(busdev, n, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));    }}

static DeviceState *slavio_intctl_init(hwaddr addr,                                       hwaddr addrg,                                       qemu_irq **parent_irq){    DeviceState *dev;    SysBusDevice *s;    unsigned int i, j;    dev = qdev_create(NULL, "slavio_intctl");    qdev_init_nofail(dev);    s = SYS_BUS_DEVICE(dev);    for (i = 0; i < MAX_CPUS; i++) {        for (j = 0; j < MAX_PILS; j++) {            sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]);        }    }    sysbus_mmio_map(s, 0, addrg);    for (i = 0; i < MAX_CPUS; i++) {        sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE);    }    return dev;}

void esp_init(hwaddr espaddr, int it_shift,              ESPDMAMemoryReadWriteFunc dma_memory_read,              ESPDMAMemoryReadWriteFunc dma_memory_write,              void *dma_opaque, qemu_irq irq, qemu_irq *reset,              qemu_irq *dma_enable){    DeviceState *dev;    SysBusDevice *s;    SysBusESPState *sysbus;    ESPState *esp;    dev = qdev_create(NULL, TYPE_ESP);    sysbus = ESP(dev);    esp = &sysbus->esp;    esp->dma_memory_read = dma_memory_read;    esp->dma_memory_write = dma_memory_write;    esp->dma_opaque = dma_opaque;    sysbus->it_shift = it_shift;    /* XXX for now until rc4030 has been changed to use DMA enable signal */    esp->dma_enabled = 1;    qdev_init_nofail(dev);    s = SYS_BUS_DEVICE(dev);    sysbus_connect_irq(s, 0, irq);    sysbus_mmio_map(s, 0, espaddr);    *reset = qdev_get_gpio_in(dev, 0);    *dma_enable = qdev_get_gpio_in(dev, 1);}

static void macio_newworld_realize(PCIDevice *d, Error **errp){    MacIOState *s = MACIO(d);    NewWorldMacIOState *ns = NEWWORLD_MACIO(d);    Error *err = NULL;    SysBusDevice *sysbus_dev;    MemoryRegion *timer_memory = NULL;    int i;    int cur_irq = 0;    macio_common_realize(d, &err);    if (err) {        error_propagate(errp, err);        return;    }    sysbus_dev = SYS_BUS_DEVICE(&s->cuda);    sysbus_connect_irq(sysbus_dev, 0, ns->irqs[cur_irq++]);    sysbus_dev = SYS_BUS_DEVICE(&s->escc);    sysbus_connect_irq(sysbus_dev, 0, ns->irqs[cur_irq++]);    sysbus_connect_irq(sysbus_dev, 1, ns->irqs[cur_irq++]);    /* OpenPIC */    sysbus_dev = SYS_BUS_DEVICE(ns->pic);    memory_region_add_subregion(&s->bar, 0x40000,                                sysbus_mmio_get_region(sysbus_dev, 0));    /* IDE buses */    for (i = 0; i < ARRAY_SIZE(ns->ide); i++) {        qemu_irq irq0 = ns->irqs[cur_irq++];        qemu_irq irq1 = ns->irqs[cur_irq++];        macio_realize_ide(s, &ns->ide[i], irq0, irq1, 0x16 + (i * 4), &err);        if (err) {            error_propagate(errp, err);            return;        }    }    /* Timer */    timer_memory = g_new(MemoryRegion, 1);    memory_region_init_io(timer_memory, OBJECT(s), &timer_ops, NULL, "timer",                          0x1000);    memory_region_add_subregion(&s->bar, 0x15000, timer_memory);}

static void overo_init(ram_addr_t ram_size,                       const char *boot_device,                       const char *kernel_filename,                       const char *kernel_cmdline,                       const char *initrd_filename,                       const char *cpu_model){    struct overo_s *s = (struct overo_s *) g_malloc0(sizeof(*s));    DriveInfo *dmtd = drive_get(IF_MTD, 0, 0);    DriveInfo *dsd  = drive_get(IF_SD, 0, 0);    if (ram_size > 1024 * 1024 * 1024) {        fprintf(stderr, "overo: maximum permitted RAM size 1024MB/n");        exit(1);    }    if (!dmtd && !dsd) {        hw_error("%s: SD or NAND image required", __FUNCTION__);    }    s->cpu = omap3_mpu_init(omap3430, ram_size,                            NULL, NULL, serial_hds[0], NULL);    s->nand = nand_init(dmtd ? dmtd->bdrv : NULL, NAND_MFR_MICRON, 0xba);    nand_setpins(s->nand, 0, 0, 0, 1, 0); /* no write-protect */    omap_gpmc_attach_nand(s->cpu->gpmc, OVERO_NAND_CS, s->nand);    if (dsd) {        omap3_mmc_attach(s->cpu->omap3_mmc[0], dsd->bdrv, 0, 0);    }    /* FAB revs >= 2516: 4030 interrupt is GPIO 0 (earlier ones were 112) */    s->twl4030 = twl4030_init(omap_i2c_bus(s->cpu->i2c, 0),                              qdev_get_gpio_in(s->cpu->gpio, 0),                              NULL, NULL);    /* Wire up an I2C slave which returns EDID monitor information;     * newer Linux kernels won't turn on the display unless they     * detect a monitor over DDC.     */    s->ddc = i2c_create_slave(omap_i2c_bus(s->cpu->i2c, 2), "i2c-ddc", 0x50);    omap_lcd_panel_attach(s->cpu->dss);    /* Strictly this should be a LAN9221 */    if (nd_table[0].vlan) {        /* The ethernet chip hangs off the GPMC */        NICInfo *nd = &nd_table[0];        qemu_check_nic_model(nd, "lan9118");        s->eth = qdev_create(NULL, "lan9118");        qdev_set_nic_properties(s->eth, nd);        qdev_init_nofail(s->eth);        omap_gpmc_attach(s->cpu->gpmc, OVERO_NET_CS,                         sysbus_mmio_get_region(sysbus_from_qdev(s->eth), 0));        sysbus_connect_irq(sysbus_from_qdev(s->eth), 0,                           qdev_get_gpio_in(s->cpu->gpio, 176));    }}

void pc_basic_device_init(qemu_irq *isa_irq,                          FDCtrl **floppy_controller,                          ISADevice **rtc_state){    int i;    DriveInfo *fd[MAX_FD];    PITState *pit;    qemu_irq rtc_irq = NULL;    qemu_irq *a20_line;    ISADevice *i8042;    qemu_irq *cpu_exit_irq;    register_ioport_write(0x80, 1, 1, ioport80_write, NULL);    register_ioport_write(0xf0, 1, 1, ioportF0_write, NULL);    if (!no_hpet) {        DeviceState *hpet = sysbus_create_simple("hpet", HPET_BASE, NULL);        for (i = 0; i < 24; i++) {            sysbus_connect_irq(sysbus_from_qdev(hpet), i, isa_irq[i]);        }        rtc_irq = qdev_get_gpio_in(hpet, 0);    }    *rtc_state = rtc_init(2000, rtc_irq);    qemu_register_boot_set(pc_boot_set, *rtc_state);    pit = pit_init(0x40, isa_reserve_irq(0));    pcspk_init(pit);    for(i = 0; i < MAX_SERIAL_PORTS; i++) {        if (serial_hds[i]) {            serial_isa_init(i, serial_hds[i]);        }    }    for(i = 0; i < MAX_PARALLEL_PORTS; i++) {        if (parallel_hds[i]) {            parallel_init(i, parallel_hds[i]);        }    }    a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 1);    i8042 = isa_create_simple("i8042");    i8042_setup_a20_line(i8042, a20_line);    vmmouse_init(i8042);    cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);    DMA_init(0, cpu_exit_irq);    for(i = 0; i < MAX_FD; i++) {        fd[i] = drive_get(IF_FLOPPY, 0, i);    }    *floppy_controller = fdctrl_init_isa(fd);}

static void slavio_timer_init_all(hwaddr addr, qemu_irq master_irq,                                  qemu_irq *cpu_irqs, unsigned int num_cpus){    DeviceState *dev;    SysBusDevice *s;    unsigned int i;    dev = qdev_create(NULL, "slavio_timer");    qdev_prop_set_uint32(dev, "num_cpus", num_cpus);    qdev_init_nofail(dev);    s = SYS_BUS_DEVICE(dev);    sysbus_connect_irq(s, 0, master_irq);    sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET);    for (i = 0; i < MAX_CPUS; i++) {        sysbus_mmio_map(s, i + 1, addr + (hwaddr)CPU_TIMER_OFFSET(i));        sysbus_connect_irq(s, i + 1, cpu_irqs[i]);    }}

static void mpcore_priv_map_setup(ARM11MPCorePriveState *s){    int i;    SysBusDevice *scubusdev = SYS_BUS_DEVICE(&s->scu);    DeviceState *gicdev = DEVICE(&s->gic);    SysBusDevice *gicbusdev = SYS_BUS_DEVICE(&s->gic);    SysBusDevice *timerbusdev = SYS_BUS_DEVICE(&s->mptimer);    SysBusDevice *wdtbusdev = SYS_BUS_DEVICE(&s->wdtimer);    memory_region_add_subregion(&s->container, 0,                                sysbus_mmio_get_region(scubusdev, 0));    /* GIC CPU interfaces: "current CPU" at 0x100, then specific CPUs     * at 0x200, 0x300...     */    for (i = 0; i < (s->num_cpu + 1); i++) {        hwaddr offset = 0x100 + (i * 0x100);        memory_region_add_subregion(&s->container, offset,                                    sysbus_mmio_get_region(gicbusdev, i + 1));    }    /* Add the regions for timer and watchdog for "current CPU" and     * for each specific CPU.     */    for (i = 0; i < (s->num_cpu + 1); i++) {        /* Timers at 0x600, 0x700, ...; watchdogs at 0x620, 0x720, ... */        hwaddr offset = 0x600 + i * 0x100;        memory_region_add_subregion(&s->container, offset,                                    sysbus_mmio_get_region(timerbusdev, i));        memory_region_add_subregion(&s->container, offset + 0x20,                                    sysbus_mmio_get_region(wdtbusdev, i));    }    memory_region_add_subregion(&s->container, 0x1000,                                sysbus_mmio_get_region(gicbusdev, 0));    /* Wire up the interrupt from each watchdog and timer.     * For each core the timer is PPI 29 and the watchdog PPI 30.     */    for (i = 0; i < s->num_cpu; i++) {        int ppibase = (s->num_irq - 32) + i * 32;        sysbus_connect_irq(timerbusdev, i,                           qdev_get_gpio_in(gicdev, ppibase + 29));        sysbus_connect_irq(wdtbusdev, i,                           qdev_get_gpio_in(gicdev, ppibase + 30));    }}

static DeviceState *stm32_init_periph(DeviceState *dev, stm32_periph_t periph,                                        hwaddr addr, qemu_irq irq){    qdev_init_nofail(dev);    sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);    if (irq) {        sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq);    }    return dev;}

DeviceState *s5l8930_spi_init(target_phys_addr_t base, qemu_irq irq){    DeviceState *dev = qdev_create(NULL, "s5l8930.spi");    //fprintf(stderr, "%s: irq %x base 0x%08x/n", __FUNCTION__, print_irq(irq), base);    qdev_init_nofail(dev);    sysbus_mmio_map(sysbus_from_qdev(dev), 0, base);    sysbus_connect_irq(sysbus_from_qdev(dev), 0, irq);    return dev;}

static inline void zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq,                                         bool is_qspi){    DeviceState *dev;    SysBusDevice *busdev;    SSIBus *spi;    DeviceState *flash_dev;    int i, j;    int num_busses =  is_qspi ? NUM_QSPI_BUSSES : 1;    int num_ss = is_qspi ? NUM_QSPI_FLASHES : NUM_SPI_FLASHES;    dev = qdev_create(NULL, "xilinx,spips");    qdev_prop_set_uint8(dev, "num-txrx-bytes", is_qspi ? 4 : 1);    qdev_prop_set_uint8(dev, "num-ss-bits", num_ss);    qdev_prop_set_uint8(dev, "num-busses", num_busses);    qdev_init_nofail(dev);    busdev = sysbus_from_qdev(dev);    sysbus_mmio_map(busdev, 0, base_addr);    if (is_qspi) {        sysbus_mmio_map(busdev, 1, 0xFC000000);    }    sysbus_connect_irq(busdev, 0, irq);    for (i = 0; i < num_busses; ++i) {        char bus_name[16];        qemu_irq cs_line;        snprintf(bus_name, 16, "spi%d", i);        spi = (SSIBus *)qdev_get_child_bus(dev, bus_name);        for (j = 0; j < num_ss; ++j) {            flash_dev = ssi_create_slave_no_init(spi, "m25p80");            qdev_prop_set_string(flash_dev, "partname", "n25q128");            qdev_init_nofail(flash_dev);            cs_line = qdev_get_gpio_in(flash_dev, 0);            sysbus_connect_irq(busdev, i * num_ss + j + 1, cs_line);        }    }}

static void xlnx_zynqmp_pmu_init(MachineState *machine){    XlnxZynqMPPMUSoCState *pmu = g_new0(XlnxZynqMPPMUSoCState, 1);    MemoryRegion *address_space_mem = get_system_memory();    MemoryRegion *pmu_rom = g_new(MemoryRegion, 1);    MemoryRegion *pmu_ram = g_new(MemoryRegion, 1);    XlnxZynqMPIPI *ipi[XLNX_ZYNQMP_PMU_NUM_IPIS];    qemu_irq irq[32];    int i;    /* Create the ROM */    memory_region_init_rom(pmu_rom, NULL, "xlnx-zynqmp-pmu.rom",                           XLNX_ZYNQMP_PMU_ROM_SIZE, &error_fatal);    memory_region_add_subregion(address_space_mem, XLNX_ZYNQMP_PMU_ROM_ADDR,                                pmu_rom);    /* Create the RAM */    memory_region_init_ram(pmu_ram, NULL, "xlnx-zynqmp-pmu.ram",                           machine->ram_size, &error_fatal);    memory_region_add_subregion(address_space_mem, XLNX_ZYNQMP_PMU_RAM_ADDR,                                pmu_ram);    /* Create the PMU device */    object_initialize(pmu, sizeof(XlnxZynqMPPMUSoCState), TYPE_XLNX_ZYNQMP_PMU_SOC);    object_property_add_child(OBJECT(machine), "pmu", OBJECT(pmu),                              &error_abort);    object_property_set_bool(OBJECT(pmu), true, "realized", &error_fatal);    for (i = 0; i < 32; i++) {        irq[i] = qdev_get_gpio_in(DEVICE(&pmu->intc), i);    }    /* Create and connect the IPI device */    for (i = 0; i < XLNX_ZYNQMP_PMU_NUM_IPIS; i++) {        ipi[i] = g_new0(XlnxZynqMPIPI, 1);        object_initialize(ipi[i], sizeof(XlnxZynqMPIPI), TYPE_XLNX_ZYNQMP_IPI);        qdev_set_parent_bus(DEVICE(ipi[i]), sysbus_get_default());    }    for (i = 0; i < XLNX_ZYNQMP_PMU_NUM_IPIS; i++) {        object_property_set_bool(OBJECT(ipi[i]), true, "realized",                                 &error_abort);        sysbus_mmio_map(SYS_BUS_DEVICE(ipi[i]), 0, ipi_addr[i]);        sysbus_connect_irq(SYS_BUS_DEVICE(ipi[i]), 0, irq[ipi_irq[i]]);    }    /* Load the kernel */    microblaze_load_kernel(&pmu->cpu, XLNX_ZYNQMP_PMU_RAM_ADDR,                           machine->ram_size,                           machine->initrd_filename,                           machine->dtb,                           NULL);}

static inline DeviceState *moxie_intc_create(hwaddr base, qemu_irq irq, int kind_of_intr){    DeviceState *dev;    dev = qdev_create(NULL, "moxie,intc");    qdev_prop_set_uint32(dev, "kind-of-intr", kind_of_intr);    qdev_init_nofail(dev);    sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);    sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq);    return dev;}

static void pl330_create(uint32_t base, qemu_irq irq, int nreq){    SysBusDevice *busdev;    DeviceState *dev;    dev = qdev_create(NULL, "pl330");    qdev_prop_set_uint8(dev, "num_periph_req",  nreq);    qdev_init_nofail(dev);    busdev = SYS_BUS_DEVICE(dev);    sysbus_mmio_map(busdev, 0, base);    sysbus_connect_irq(busdev, 0, irq);}

static void apc_init(hwaddr power_base, qemu_irq cpu_halt){    DeviceState *dev;    SysBusDevice *s;    dev = qdev_create(NULL, "apc");    qdev_init_nofail(dev);    s = SYS_BUS_DEVICE(dev);    /* Power management (APC) XXX: not a Slavio device */    sysbus_mmio_map(s, 0, power_base);    sysbus_connect_irq(s, 0, cpu_halt);}

static void tcx_init(hwaddr addr, qemu_irq irq, int vram_size, int width,                     int height, int depth){    DeviceState *dev;    SysBusDevice *s;    dev = qdev_create(NULL, "SUNW,tcx");    qdev_prop_set_uint32(dev, "vram_size", vram_size);    qdev_prop_set_uint16(dev, "width", width);    qdev_prop_set_uint16(dev, "height", height);    qdev_prop_set_uint16(dev, "depth", depth);    qdev_prop_set_uint64(dev, "prom_addr", addr);    qdev_init_nofail(dev);    s = SYS_BUS_DEVICE(dev);    /* 10/ROM : FCode ROM */    sysbus_mmio_map(s, 0, addr);    /* 2/STIP : Stipple */    sysbus_mmio_map(s, 1, addr + 0x04000000ULL);    /* 3/BLIT : Blitter */    sysbus_mmio_map(s, 2, addr + 0x06000000ULL);    /* 5/RSTIP : Raw Stipple */    sysbus_mmio_map(s, 3, addr + 0x0c000000ULL);    /* 6/RBLIT : Raw Blitter */    sysbus_mmio_map(s, 4, addr + 0x0e000000ULL);    /* 7/TEC : Transform Engine */    sysbus_mmio_map(s, 5, addr + 0x00700000ULL);    /* 8/CMAP  : DAC */    sysbus_mmio_map(s, 6, addr + 0x00200000ULL);    /* 9/THC : */    if (depth == 8) {        sysbus_mmio_map(s, 7, addr + 0x00300000ULL);    } else {        sysbus_mmio_map(s, 7, addr + 0x00301000ULL);    }    /* 11/DHC : */    sysbus_mmio_map(s, 8, addr + 0x00240000ULL);    /* 12/ALT : */    sysbus_mmio_map(s, 9, addr + 0x00280000ULL);    /* 0/DFB8 : 8-bit plane */    sysbus_mmio_map(s, 10, addr + 0x00800000ULL);    /* 1/DFB24 : 24bit plane */    sysbus_mmio_map(s, 11, addr + 0x02000000ULL);    /* 4/RDFB32: Raw framebuffer. Control plane */    sysbus_mmio_map(s, 12, addr + 0x0a000000ULL);    /* 9/THC24bits : NetBSD writes here even with 8-bit display: dummy */    if (depth == 8) {        sysbus_mmio_map(s, 13, addr + 0x00301000ULL);    }    sysbus_connect_irq(s, 0, irq);}

static void slavio_misc_init(hwaddr base,                             hwaddr aux1_base,                             hwaddr aux2_base, qemu_irq irq,                             qemu_irq fdc_tc){    DeviceState *dev;    SysBusDevice *s;    dev = qdev_create(NULL, "slavio_misc");    qdev_init_nofail(dev);    s = SYS_BUS_DEVICE(dev);    if (base) {        /* 8 bit registers */        /* Slavio control */        sysbus_mmio_map(s, 0, base + MISC_CFG);        /* Diagnostics */        sysbus_mmio_map(s, 1, base + MISC_DIAG);        /* Modem control */        sysbus_mmio_map(s, 2, base + MISC_MDM);        /* 16 bit registers */        /* ss600mp diag LEDs */        sysbus_mmio_map(s, 3, base + MISC_LEDS);        /* 32 bit registers */        /* System control */        sysbus_mmio_map(s, 4, base + MISC_SYS);    }    if (aux1_base) {        /* AUX 1 (Misc System Functions) */        sysbus_mmio_map(s, 5, aux1_base);    }    if (aux2_base) {        /* AUX 2 (Software Powerdown Control) */        sysbus_mmio_map(s, 6, aux2_base);    }    sysbus_connect_irq(s, 0, irq);    sysbus_connect_irq(s, 1, fdc_tc);    slavio_system_powerdown = qdev_get_gpio_in(dev, 0);    qemu_register_powerdown_notifier(&slavio_system_powerdown_notifier);}

static void gem_init(NICInfo *nd, uint32_t base, qemu_irq irq){    DeviceState *dev;    SysBusDevice *s;    qemu_check_nic_model(nd, "cadence_gem");    dev = qdev_create(NULL, "cadence_gem");    qdev_set_nic_properties(dev, nd);    qdev_init_nofail(dev);    s = sysbus_from_qdev(dev);    sysbus_mmio_map(s, 0, base);    sysbus_connect_irq(s, 0, irq);}

DeviceState *etsec_create(hwaddr         base,                          MemoryRegion * mr,                          NICInfo      * nd,                          qemu_irq       tx_irq,                          qemu_irq       rx_irq,                          qemu_irq       err_irq){    DeviceState *dev;    dev = qdev_create(NULL, "eTSEC");    qdev_set_nic_properties(dev, nd);    qdev_init_nofail(dev);    sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, tx_irq);    sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, rx_irq);    sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2, err_irq);    memory_region_add_subregion(mr, base,                                SYS_BUS_DEVICE(dev)->mmio[0].memory);    return dev;}

/* Legacy helper function.  Should go away when machine config files are   implemented.  */void smc91c111_init(NICInfo *nd, uint32_t base, qemu_irq irq){    DeviceState *dev;    SysBusDevice *s;    qemu_check_nic_model(nd, "smc91c111");    dev = qdev_create(NULL, "smc91c111");    qdev_set_netdev(dev, nd);    qdev_init(dev);    s = sysbus_from_qdev(dev);    sysbus_mmio_map(s, 0, base);    sysbus_connect_irq(s, 0, irq);}

static inline void zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq,                                         bool is_qspi){    DeviceState *dev;    SysBusDevice *busdev;    SSIBus *spi;    DeviceState *flash_dev;    int i, j;    int num_busses =  is_qspi ? NUM_QSPI_BUSSES : 1;    int num_ss = is_qspi ? NUM_QSPI_FLASHES : NUM_SPI_FLASHES;    dev = qdev_create(NULL, is_qspi ? "xlnx.ps7-qspi" : "cdns.spi-r1p6");    qdev_prop_set_uint8(dev, "num-txrx-bytes", is_qspi ? 4 : 1);    qdev_prop_set_uint8(dev, "num-ss-bits", num_ss);    qdev_prop_set_uint8(dev, "num-busses", num_busses);    qdev_init_nofail(dev);    busdev = SYS_BUS_DEVICE(dev);    sysbus_mmio_map(busdev, 0, base_addr);    if (is_qspi) {        sysbus_mmio_map(busdev, 1, 0xFC000000);    }    sysbus_connect_irq(busdev, 0, irq);    for (i = 0; i < num_busses; ++i) {        char bus_name[16];        qemu_irq cs_line;        snprintf(bus_name, 16, "spi%d", i);        spi = (SSIBus *)qdev_get_child_bus(dev, bus_name);        for (j = 0; j < num_ss; ++j) {            flash_dev = ssi_create_slave(spi, "n25q128");            cs_line = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0);            sysbus_connect_irq(busdev, i * num_ss + j + 1, cs_line);        }    }}

/* Legacy helper function.  Should go away when machine config files are   implemented.  */void smc91c111_init(NICInfo *nd, uint32_t base, qemu_irq irq){    DeviceState *dev;    SysBusDevice *s;    qemu_check_nic_model(nd, "smc91c111");    dev = qdev_create(NULL, "smc91c111");    qdev_set_nic_properties(dev, nd);    qdev_init_nofail(dev);    s = SYS_BUS_DEVICE(dev);    sysbus_mmio_map(s, 0, base);    sysbus_connect_irq(s, 0, irq);}

static int macio_oldworld_initfn(PCIDevice *d){    MacIOState *s = MACIO(d);    OldWorldMacIOState *os = OLDWORLD_MACIO(d);    SysBusDevice *sysbus_dev;    int ret = macio_common_initfn(d);    if (ret < 0) {        return ret;    }    sysbus_dev = SYS_BUS_DEVICE(&s->cuda);    sysbus_connect_irq(sysbus_dev, 0, os->irqs[0]);    ret = qdev_init(DEVICE(&os->nvram));    if (ret < 0) {        return ret;    }    sysbus_dev = SYS_BUS_DEVICE(&os->nvram);    memory_region_add_subregion(&s->bar, 0x60000,                                sysbus_mmio_get_region(sysbus_dev, 0));    pmac_format_nvram_partition(&os->nvram, os->nvram.size);    if (s->pic_mem) {        /* Heathrow PIC */        memory_region_add_subregion(&s->bar, 0x00000, s->pic_mem);    }    sysbus_dev = SYS_BUS_DEVICE(&os->ide);    sysbus_connect_irq(sysbus_dev, 0, os->irqs[1]);    sysbus_connect_irq(sysbus_dev, 1, os->irqs[2]);    macio_ide_register_dma(&os->ide, s->dbdma, 0x16);    ret = qdev_init(DEVICE(&os->ide));    if (ret < 0) {        return ret;    }    return 0;}

static int macio_newworld_initfn(PCIDevice *d){    MacIOState *s = MACIO(d);    NewWorldMacIOState *ns = NEWWORLD_MACIO(d);    SysBusDevice *sysbus_dev;    int ret = macio_common_initfn(d);    if (ret < 0) {        return ret;    }    sysbus_dev = SYS_BUS_DEVICE(&s->cuda);    sysbus_connect_irq(sysbus_dev, 0, ns->irqs[0]);    if (s->pic_mem) {        /* OpenPIC */        memory_region_add_subregion(&s->bar, 0x40000, s->pic_mem);    }    sysbus_dev = SYS_BUS_DEVICE(&ns->ide[0]);    sysbus_connect_irq(sysbus_dev, 0, ns->irqs[1]);    sysbus_connect_irq(sysbus_dev, 1, ns->irqs[2]);    macio_ide_register_dma(&ns->ide[0], s->dbdma, 0x16);    ret = qdev_init(DEVICE(&ns->ide[0]));    if (ret < 0) {        return ret;    }    sysbus_dev = SYS_BUS_DEVICE(&ns->ide[1]);    sysbus_connect_irq(sysbus_dev, 0, ns->irqs[3]);    sysbus_connect_irq(sysbus_dev, 1, ns->irqs[4]);    macio_ide_register_dma(&ns->ide[1], s->dbdma, 0x1a);    ret = qdev_init(DEVICE(&ns->ide[1]));    if (ret < 0) {        return ret;    }    return 0;}

static void *iommu_init(hwaddr addr, uint32_t version, qemu_irq irq){    DeviceState *dev;    SysBusDevice *s;    dev = qdev_create(NULL, "iommu");    qdev_prop_set_uint32(dev, "version", version);    qdev_init_nofail(dev);    s = SYS_BUS_DEVICE(dev);    sysbus_connect_irq(s, 0, irq);    sysbus_mmio_map(s, 0, addr);    return s;}

void *mcf_uart_init(qemu_irq irq, Chardev *chrdrv){    DeviceState  *dev;    dev = qdev_create(NULL, TYPE_MCF_UART);    if (chrdrv) {        qdev_prop_set_chr(dev, "chardev", chrdrv);    }    qdev_init_nofail(dev);    sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq);    return dev;}

static void ecc_init(hwaddr base, qemu_irq irq, uint32_t version){    DeviceState *dev;    SysBusDevice *s;    dev = qdev_create(NULL, "eccmemctl");    qdev_prop_set_uint32(dev, "version", version);    qdev_init_nofail(dev);    s = SYS_BUS_DEVICE(dev);    sysbus_connect_irq(s, 0, irq);    sysbus_mmio_map(s, 0, base);    if (version == 0) { // SS-600MP only        sysbus_mmio_map(s, 1, base + 0x1000);    }}

static void mipsnet_init(int base, qemu_irq irq, NICInfo *nd){    DeviceState *dev;    SysBusDevice *s;    dev = qdev_create(NULL, "mipsnet");    qdev_set_nic_properties(dev, nd);    qdev_init_nofail(dev);    s = SYS_BUS_DEVICE(dev);    sysbus_connect_irq(s, 0, irq);    memory_region_add_subregion(get_system_io(),                                base,                                sysbus_mmio_get_region(s, 0));}

static MemoryRegion *make_uart(MPS2TZMachineState *mms, void *opaque,                               const char *name, hwaddr size){    CMSDKAPBUART *uart = opaque;    int i = uart - &mms->uart[0];    int rxirqno = i * 2;    int txirqno = i * 2 + 1;    int combirqno = i + 10;    SysBusDevice *s;    DeviceState *orgate_dev = DEVICE(&mms->uart_irq_orgate);    sysbus_init_child_obj(OBJECT(mms), name, uart, sizeof(mms->uart[0]),                          TYPE_CMSDK_APB_UART);    qdev_prop_set_chr(DEVICE(uart), "chardev", serial_hd(i));    qdev_prop_set_uint32(DEVICE(uart), "pclk-frq", SYSCLK_FRQ);    object_property_set_bool(OBJECT(uart), true, "realized", &error_fatal);    s = SYS_BUS_DEVICE(uart);    sysbus_connect_irq(s, 0, get_sse_irq_in(mms, txirqno));    sysbus_connect_irq(s, 1, get_sse_irq_in(mms, rxirqno));    sysbus_connect_irq(s, 2, qdev_get_gpio_in(orgate_dev, i * 2));    sysbus_connect_irq(s, 3, qdev_get_gpio_in(orgate_dev, i * 2 + 1));    sysbus_connect_irq(s, 4, get_sse_irq_in(mms, combirqno));    return sysbus_mmio_get_region(SYS_BUS_DEVICE(uart), 0);}