自学教程：C++ sysbus_create_simple函数代码示例

static void puv3_soc_init(CPUUniCore32State *env){    qemu_irq *cpu_intc, irqs[PUV3_IRQS_NR];    DeviceState *dev;    MemoryRegion *i8042 = g_new(MemoryRegion, 1);    int i;    /* Initialize interrupt controller */    cpu_intc = qemu_allocate_irqs(puv3_intc_cpu_handler, env, 1);    dev = sysbus_create_simple("puv3_intc", PUV3_INTC_BASE, *cpu_intc);    for (i = 0; i < PUV3_IRQS_NR; i++) {        irqs[i] = qdev_get_gpio_in(dev, i);    }    /* Initialize minimal necessary devices for kernel booting */    sysbus_create_simple("puv3_pm", PUV3_PM_BASE, NULL);    sysbus_create_simple("puv3_dma", PUV3_DMA_BASE, NULL);    sysbus_create_simple("puv3_ost", PUV3_OST_BASE, irqs[PUV3_IRQS_OST0]);    sysbus_create_varargs("puv3_gpio", PUV3_GPIO_BASE,            irqs[PUV3_IRQS_GPIOLOW0], irqs[PUV3_IRQS_GPIOLOW1],            irqs[PUV3_IRQS_GPIOLOW2], irqs[PUV3_IRQS_GPIOLOW3],            irqs[PUV3_IRQS_GPIOLOW4], irqs[PUV3_IRQS_GPIOLOW5],            irqs[PUV3_IRQS_GPIOLOW6], irqs[PUV3_IRQS_GPIOLOW7],            irqs[PUV3_IRQS_GPIOHIGH], NULL);    /* Keyboard (i8042), mouse disabled for nographic */    i8042_mm_init(irqs[PUV3_IRQS_PS2_KBD], NULL, i8042, PUV3_REGS_OFFSET, 4);    memory_region_add_subregion(get_system_memory(), PUV3_PS2_BASE, i8042);}

static void a9_daughterboard_init(const VEDBoardInfo *daughterboard,                                  ram_addr_t ram_size,                                  const char *cpu_model,                                  qemu_irq *pic){    MemoryRegion *sysmem = get_system_memory();    MemoryRegion *ram = g_new(MemoryRegion, 1);    MemoryRegion *lowram = g_new(MemoryRegion, 1);    ram_addr_t low_ram_size;    if (!cpu_model) {        cpu_model = "cortex-a9";    }    if (ram_size > 0x40000000) {        /* 1GB is the maximum the address space permits */        fprintf(stderr, "vexpress-a9: cannot model more than 1GB RAM/n");        exit(1);    }    memory_region_init_ram(ram, NULL, "vexpress.highmem", ram_size,                           &error_abort);    vmstate_register_ram_global(ram);    low_ram_size = ram_size;    if (low_ram_size > 0x4000000) {        low_ram_size = 0x4000000;    }    /* RAM is from 0x60000000 upwards. The bottom 64MB of the     * address space should in theory be remappable to various     * things including ROM or RAM; we always map the RAM there.     */    memory_region_init_alias(lowram, NULL, "vexpress.lowmem", ram, 0, low_ram_size);    memory_region_add_subregion(sysmem, 0x0, lowram);    memory_region_add_subregion(sysmem, 0x60000000, ram);    /* 0x1e000000 A9MPCore (SCU) private memory region */    init_cpus(cpu_model, "a9mpcore_priv", 0x1e000000, pic);    /* Daughterboard peripherals : 0x10020000 .. 0x20000000 */    /* 0x10020000 PL111 CLCD (daughterboard) */    sysbus_create_simple("pl111", 0x10020000, pic[44]);    /* 0x10060000 AXI RAM */    /* 0x100e0000 PL341 Dynamic Memory Controller */    /* 0x100e1000 PL354 Static Memory Controller */    /* 0x100e2000 System Configuration Controller */    sysbus_create_simple("sp804", 0x100e4000, pic[48]);    /* 0x100e5000 SP805 Watchdog module */    /* 0x100e6000 BP147 TrustZone Protection Controller */    /* 0x100e9000 PL301 'Fast' AXI matrix */    /* 0x100ea000 PL301 'Slow' AXI matrix */    /* 0x100ec000 TrustZone Address Space Controller */    /* 0x10200000 CoreSight debug APB */    /* 0x1e00a000 PL310 L2 Cache Controller */    sysbus_create_varargs("l2x0", 0x1e00a000, NULL);}

static int realview_mpcore_init(SysBusDevice *dev){    mpcore_rirq_state *s = FROM_SYSBUS(mpcore_rirq_state, dev);    DeviceState *gic;    DeviceState *priv;    int n;    int i;    priv = qdev_create(NULL, "arm11mpcore_priv");    qdev_prop_set_uint32(priv, "num-cpu", s->num_cpu);    qdev_init_nofail(priv);    s->priv = SYS_BUS_DEVICE(priv);    sysbus_pass_irq(dev, s->priv);    for (i = 0; i < 32; i++) {        s->cpuic[i] = qdev_get_gpio_in(priv, i);    }    /* ??? IRQ routing is hardcoded to "normal" mode.  */    for (n = 0; n < 4; n++) {        gic = sysbus_create_simple("realview_gic", 0x10040000 + n * 0x10000,                                   s->cpuic[10 + n]);        for (i = 0; i < 64; i++) {            s->rvic[n][i] = qdev_get_gpio_in(gic, i);        }    }    qdev_init_gpio_in(&dev->qdev, mpcore_rirq_set_irq, 64);    sysbus_init_mmio(dev, sysbus_mmio_get_region(s->priv, 0));    return 0;}

static void collie_init(ram_addr_t ram_size,                const char *boot_device,                const char *kernel_filename, const char *kernel_cmdline,                const char *initrd_filename, const char *cpu_model){    StrongARMState *s;    DriveInfo *dinfo;    ram_addr_t phys_flash;    if (!cpu_model) {        cpu_model = "sa1110";    }    s = sa1110_init(collie_binfo.ram_size, cpu_model);    phys_flash = qemu_ram_alloc(NULL, "collie.fl1", 0x02000000);    dinfo = drive_get(IF_PFLASH, 0, 0);    pflash_cfi01_register(SA_CS0, phys_flash,                    dinfo ? dinfo->bdrv : NULL, (64 * 1024),                    512, 4, 0x00, 0x00, 0x00, 0x00, 0);    phys_flash = qemu_ram_alloc(NULL, "collie.fl2", 0x02000000);    dinfo = drive_get(IF_PFLASH, 0, 1);    pflash_cfi01_register(SA_CS1, phys_flash,                    dinfo ? dinfo->bdrv : NULL, (64 * 1024),                    512, 4, 0x00, 0x00, 0x00, 0x00, 0);    sysbus_create_simple("scoop", 0x40800000, NULL);    collie_binfo.kernel_filename = kernel_filename;    collie_binfo.kernel_cmdline = kernel_cmdline;    collie_binfo.initrd_filename = initrd_filename;    collie_binfo.board_id = 0x208;    arm_load_kernel(s->env, &collie_binfo);}

static void apic_common_realize(DeviceState *dev, Error **errp){    APICCommonState *s = APIC_COMMON(dev);    APICCommonClass *info;    static DeviceState *vapic;    int instance_id = s->id;    info = APIC_COMMON_GET_CLASS(s);    info->realize(dev, errp);    /* Note: We need at least 1M to map the VAPIC option ROM */    if (!vapic && s->vapic_control & VAPIC_ENABLE_MASK &&        ram_size >= 1024 * 1024) {        vapic = sysbus_create_simple("kvmvapic", -1, NULL);    }    s->vapic = vapic;    if (apic_report_tpr_access && info->enable_tpr_reporting) {        info->enable_tpr_reporting(s, true);    }    if (s->legacy_instance_id) {        instance_id = -1;    }    vmstate_register_with_alias_id(NULL, instance_id, &vmstate_apic_common,                                   s, -1, 0);}

static int apic_init_common(SysBusDevice *dev){    APICCommonState *s = APIC_COMMON(dev);    APICCommonClass *info;    static DeviceState *vapic;    static int apic_no;    if (apic_no >= MAX_APICS) {        return -1;    }    s->idx = apic_no++;    info = APIC_COMMON_GET_CLASS(s);    info->init(s);    sysbus_init_mmio(dev, &s->io_memory);    /* Note: We need at least 1M to map the VAPIC option ROM */    if (!vapic && s->vapic_control & VAPIC_ENABLE_MASK &&        ram_size >= 1024 * 1024) {        vapic = sysbus_create_simple("kvmvapic", -1, NULL);    }    s->vapic = vapic;    if (apic_report_tpr_access && info->enable_tpr_reporting) {        info->enable_tpr_reporting(s, true);    }    return 0;}

static void apic_common_realize(DeviceState *dev, Error **errp){    APICCommonState *s = APIC_COMMON(dev);    APICCommonClass *info;    static DeviceState *vapic;    static int apic_no;    static bool mmio_registered;    if (apic_no >= MAX_APICS) {        error_setg(errp, "%s initialization failed.",                   object_get_typename(OBJECT(dev)));        return;    }    s->idx = apic_no++;    info = APIC_COMMON_GET_CLASS(s);    info->realize(dev, errp);    if (!mmio_registered) {        ICCBus *b = ICC_BUS(qdev_get_parent_bus(dev));        memory_region_add_subregion(b->apic_address_space, 0, &s->io_memory);        mmio_registered = true;    }    /* Note: We need at least 1M to map the VAPIC option ROM */    if (!vapic && s->vapic_control & VAPIC_ENABLE_MASK &&        ram_size >= 1024 * 1024) {        vapic = sysbus_create_simple("kvmvapic", -1, NULL);    }    s->vapic = vapic;    if (apic_report_tpr_access && info->enable_tpr_reporting) {        info->enable_tpr_reporting(s, true);    }}

/* Note: Must be called after VCPU initialization. */void kvmclock_create(void){    if (kvm_enabled() &&        first_cpu->cpuid_kvm_features & (1ULL << KVM_FEATURE_CLOCKSOURCE)) {        sysbus_create_simple("kvmclock", -1, NULL);    }}

static void apic_common_realize(DeviceState *dev, Error **errp){    APICCommonState *s = APIC_COMMON(dev);    APICCommonClass *info;    static DeviceState *vapic;    static int apic_no;    if (apic_no >= MAX_APICS) {        error_setg(errp, "%s initialization failed.",                   object_get_typename(OBJECT(dev)));        return;    }    s->idx = apic_no++;    info = APIC_COMMON_GET_CLASS(s);    info->realize(dev, errp);    /* Note: We need at least 1M to map the VAPIC option ROM */    if (!vapic && s->vapic_control & VAPIC_ENABLE_MASK &&        ram_size >= 1024 * 1024) {        vapic = sysbus_create_simple("kvmvapic", -1, NULL);    }    s->vapic = vapic;    if (apic_report_tpr_access && info->enable_tpr_reporting) {        info->enable_tpr_reporting(s, true);    }}

static void collie_init(QEMUMachineInitArgs *args){    const char *cpu_model = args->cpu_model;    const char *kernel_filename = args->kernel_filename;    const char *kernel_cmdline = args->kernel_cmdline;    const char *initrd_filename = args->initrd_filename;    StrongARMState *s;    DriveInfo *dinfo;    MemoryRegion *sysmem = get_system_memory();    if (!cpu_model) {        cpu_model = "sa1110";    }    s = sa1110_init(sysmem, collie_binfo.ram_size, cpu_model);    dinfo = drive_get(IF_PFLASH, 0, 0);    pflash_cfi01_register(SA_CS0, NULL, "collie.fl1", 0x02000000,                          dinfo ? dinfo->bdrv : NULL, (64 * 1024),                          512, 4, 0x00, 0x00, 0x00, 0x00, 0);    dinfo = drive_get(IF_PFLASH, 0, 1);    pflash_cfi01_register(SA_CS1, NULL, "collie.fl2", 0x02000000,                          dinfo ? dinfo->bdrv : NULL, (64 * 1024),                          512, 4, 0x00, 0x00, 0x00, 0x00, 0);    sysbus_create_simple("scoop", 0x40800000, NULL);    collie_binfo.kernel_filename = kernel_filename;    collie_binfo.kernel_cmdline = kernel_cmdline;    collie_binfo.initrd_filename = initrd_filename;    collie_binfo.board_id = 0x208;    arm_load_kernel(s->cpu, &collie_binfo);}

static void stm32l152rbt6_init(ram_addr_t ram_size, const char *boot_device, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model) {    //Préparation de la mémoire    MemoryRegion *address_space_mem = get_system_memory();    uint16_t flash_size = stm32_board.f_size; //128KBits    uint16_t sram_size = 0x0010; //16 KBits            //Initialisation du processeur (+ mémoire)    qemu_irq* pic = armv7m_init(address_space_mem, flash_size, sram_size, kernel_filename, cpu_model);    stm32l_sys_init(0x1FF00000, pic[28], &stm32_board); //FIXME: Vérifier l'implémentation de la sys memory            //Structures GPIO    static const uint32_t gpio_addr[NB_GPIO] = {        0x40020000, //GPIO_A        0x40020400, //GPIO_B        0x40020800, //GPIO_C        0x40020C00, //GPIO_D        0x40021000, //GPIO_E        0x40021400  //GPIO_H    };//    static const int gpio_idIrqNVIC[NB_NVIC_IRQ] = {6,7,8,9,10};    DeviceState* gpio_dev[NB_GPIO];            //Création du bouton    DeviceState* button = sysbus_create_simple("stm32_button", -1, NULL);        //Création des leds    DeviceState* led_dev6 = sysbus_create_simple("stm32_led_blue", -1, NULL);    DeviceState* led_dev7 = sysbus_create_simple("stm32_led_green", -1, NULL);            //Initialisation du GPIO_A    gpio_dev[GPIO_A] = sysbus_create_varargs("stm32_gpio_A", gpio_addr[GPIO_A], NULL); //, pic[gpio_idIrqNVIC[0]], pic[gpio_idIrqNVIC[1]], pic[gpio_idIrqNVIC[2]], pic[gpio_idIrqNVIC[3]], pic[gpio_idIrqNVIC[4]], NULL);    qemu_irq entreeBouton = qdev_get_gpio_in(gpio_dev[GPIO_A], 0);    qdev_connect_gpio_out(button, 0, entreeBouton);        //Initialisation du GPIO_B    gpio_dev[GPIO_B] = sysbus_create_varargs("stm32_gpio_B", gpio_addr[GPIO_B], NULL); //, pic[gpio_idIrqNVIC[0]], pic[gpio_idIrqNVIC[1]], pic[gpio_idIrqNVIC[2]], pic[gpio_idIrqNVIC[3]], pic[gpio_idIrqNVIC[4]], NULL);    qemu_irq entreeLED6 = qdev_get_gpio_in(led_dev6, 0);    qdev_connect_gpio_out(gpio_dev[GPIO_B], 6, entreeLED6);    qemu_irq entreeLED7 = qdev_get_gpio_in(led_dev7, 0);    qdev_connect_gpio_out(gpio_dev[GPIO_B], 7, entreeLED7);    }

void pc_basic_device_init(qemu_irq *isa_irq,                          FDCtrl **floppy_controller,                          ISADevice **rtc_state){    int i;    DriveInfo *fd[MAX_FD];    PITState *pit;    qemu_irq rtc_irq = NULL;    qemu_irq *a20_line;    ISADevice *i8042;    qemu_irq *cpu_exit_irq;    register_ioport_write(0x80, 1, 1, ioport80_write, NULL);    register_ioport_write(0xf0, 1, 1, ioportF0_write, NULL);    if (!no_hpet) {        DeviceState *hpet = sysbus_create_simple("hpet", HPET_BASE, NULL);        for (i = 0; i < 24; i++) {            sysbus_connect_irq(sysbus_from_qdev(hpet), i, isa_irq[i]);        }        rtc_irq = qdev_get_gpio_in(hpet, 0);    }    *rtc_state = rtc_init(2000, rtc_irq);    qemu_register_boot_set(pc_boot_set, *rtc_state);    pit = pit_init(0x40, isa_reserve_irq(0));    pcspk_init(pit);    for(i = 0; i < MAX_SERIAL_PORTS; i++) {        if (serial_hds[i]) {            serial_isa_init(i, serial_hds[i]);        }    }    for(i = 0; i < MAX_PARALLEL_PORTS; i++) {        if (parallel_hds[i]) {            parallel_init(i, parallel_hds[i]);        }    }    a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 1);    i8042 = isa_create_simple("i8042");    i8042_setup_a20_line(i8042, a20_line);    vmmouse_init(i8042);    cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);    DMA_init(0, cpu_exit_irq);    for(i = 0; i < MAX_FD; i++) {        fd[i] = drive_get(IF_FLOPPY, 0, i);    }    *floppy_controller = fdctrl_init_isa(fd);}

/* Note: Must be called after VCPU initialization. */void kvmclock_create(void){    X86CPU *cpu = X86_CPU(first_cpu);    if (kvm_enabled() &&        cpu->env.features[FEAT_KVM] & ((1ULL << KVM_FEATURE_CLOCKSOURCE) |                                       (1ULL << KVM_FEATURE_CLOCKSOURCE2))) {        sysbus_create_simple(TYPE_KVM_CLOCK, -1, NULL);    }}

static voidpetalogix_s3adsp1800_init(QEMUMachineInitArgs *args){    ram_addr_t ram_size = args->ram_size;    const char *cpu_model = args->cpu_model;    DeviceState *dev;    MicroBlazeCPU *cpu;    CPUMBState *env;    DriveInfo *dinfo;    int i;    hwaddr ddr_base = MEMORY_BASEADDR;    MemoryRegion *phys_lmb_bram = g_new(MemoryRegion, 1);    MemoryRegion *phys_ram = g_new(MemoryRegion, 1);    qemu_irq irq[32], *cpu_irq;    MemoryRegion *sysmem = get_system_memory();    /* init CPUs */    if (cpu_model == NULL) {        cpu_model = "microblaze";    }    cpu = cpu_mb_init(cpu_model);    env = &cpu->env;    /* Attach emulated BRAM through the LMB.  */    memory_region_init_ram(phys_lmb_bram,                           "petalogix_s3adsp1800.lmb_bram", LMB_BRAM_SIZE);    vmstate_register_ram_global(phys_lmb_bram);    memory_region_add_subregion(sysmem, 0x00000000, phys_lmb_bram);    memory_region_init_ram(phys_ram, "petalogix_s3adsp1800.ram", ram_size);    vmstate_register_ram_global(phys_ram);    memory_region_add_subregion(sysmem, ddr_base, phys_ram);    dinfo = drive_get(IF_PFLASH, 0, 0);    pflash_cfi01_register(FLASH_BASEADDR,                          NULL, "petalogix_s3adsp1800.flash", FLASH_SIZE,                          dinfo ? dinfo->bdrv : NULL, (64 * 1024),                          FLASH_SIZE >> 16,                          1, 0x89, 0x18, 0x0000, 0x0, 1);    cpu_irq = microblaze_pic_init_cpu(env);    dev = xilinx_intc_create(INTC_BASEADDR, cpu_irq[0], 2);    for (i = 0; i < 32; i++) {        irq[i] = qdev_get_gpio_in(dev, i);    }    sysbus_create_simple("xlnx.xps-uartlite", UARTLITE_BASEADDR, irq[3]);    /* 2 timers at irq 2 @ 62 Mhz.  */    xilinx_timer_create(TIMER_BASEADDR, irq[0], 0, 62 * 1000000);    xilinx_ethlite_create(&nd_table[0], ETHLITE_BASEADDR, irq[1], 0, 0);    microblaze_load_kernel(cpu, ddr_base, ram_size,                           BINARY_DEVICE_TREE_FILE, machine_cpu_reset);}

static inline void zynq_init_zc70x_i2c(uint32_t base_addr, qemu_irq irq){    DeviceState *dev = sysbus_create_simple("cdns.i2c-r1p10", base_addr, irq);    I2CBus *i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c");    int i, bus;    dev = i2c_create_slave(i2c, "pca9548", 0);    for (bus = 2; bus <= 3; bus++) {        char bus_name[16];        snprintf(bus_name, sizeof(bus_name), "[email
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