自学教程：C++ sysbus_init_mmio函数代码示例

static int idreg_init1(SysBusDevice *dev){    IDRegState *s = MACIO_ID_REGISTER(dev);    memory_region_init_ram(&s->mem, OBJECT(s),                           "sun4m.idreg", sizeof(idreg_data), &error_fatal);    vmstate_register_ram_global(&s->mem);    memory_region_set_readonly(&s->mem, true);    sysbus_init_mmio(dev, &s->mem);    return 0;}

static int prom_init1(SysBusDevice *dev){    PROMState *s = OPENPROM(dev);    memory_region_init_ram(&s->prom, OBJECT(s), "sun4m.prom", PROM_SIZE_MAX,                           &error_fatal);    vmstate_register_ram_global(&s->prom);    memory_region_set_readonly(&s->prom, true);    sysbus_init_mmio(dev, &s->prom);    return 0;}

static void milkymist_uart_init(Object *obj){    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);    MilkymistUartState *s = MILKYMIST_UART(obj);    sysbus_init_irq(sbd, &s->irq);    memory_region_init_io(&s->regs_region, OBJECT(s), &uart_mmio_ops, s,                          "milkymist-uart", R_MAX * 4);    sysbus_init_mmio(sbd, &s->regs_region);}

static void xilinx_intc_init(SysBusDevice *dev){    struct xlx_pic *p = FROM_SYSBUS(typeof (*p), dev);    int pic_regs;    qdev_init_gpio_in(&dev->qdev, irq_handler, 32);    sysbus_init_irq(dev, &p->parent_irq);    pic_regs = cpu_register_io_memory(pic_read, pic_write, p);    sysbus_init_mmio(dev, R_MAX * 4, pic_regs);}

static int cs4231_init1(SysBusDevice *dev){    CSState *s = CS4231(dev);    memory_region_init_io(&s->iomem, OBJECT(s), &cs_mem_ops, s, "cs4321",                          CS_SIZE);    sysbus_init_mmio(dev, &s->iomem);    sysbus_init_irq(dev, &s->irq);    return 0;}

static int icp_pic_init(SysBusDevice *dev){    icp_pic_state *s = FROM_SYSBUS(icp_pic_state, dev);    qdev_init_gpio_in(&dev->qdev, icp_pic_set_irq, 32);    sysbus_init_irq(dev, &s->parent_irq);    sysbus_init_irq(dev, &s->parent_fiq);    memory_region_init_io(&s->iomem, &icp_pic_ops, s, "icp-pic", 0x00800000);    sysbus_init_mmio(dev, &s->iomem);    return 0;}

static int cs4231_init1(SysBusDevice *dev){    int io;    CSState *s = FROM_SYSBUS(CSState, dev);    io = cpu_register_io_memory(cs_mem_read, cs_mem_write, s);    sysbus_init_mmio(dev, CS_SIZE, io);    sysbus_init_irq(dev, &s->irq);    return 0;}

static int highbank_regs_init(SysBusDevice *dev){    HighbankRegsState *s = FROM_SYSBUS(HighbankRegsState, dev);    s->iomem = g_new(MemoryRegion, 1);    memory_region_init_io(s->iomem, &hb_mem_ops, s->regs, "highbank_regs",                          0x1000);    sysbus_init_mmio(dev, s->iomem);    return 0;}

static int puv3_pm_init(SysBusDevice *dev){    PUV3PMState *s = PUV3_PM(dev);    s->reg_PCGR = 0x0;    memory_region_init_io(&s->iomem, OBJECT(s), &puv3_pm_ops, s, "puv3_pm",            PUV3_REGS_OFFSET);    sysbus_init_mmio(dev, &s->iomem);    return 0;}

static void arm_sysctl_init(Object *obj){    DeviceState *dev = DEVICE(obj);    SysBusDevice *sd = SYS_BUS_DEVICE(obj);    arm_sysctl_state *s = FROM_SYSBUS(arm_sysctl_state, sd);    memory_region_init_io(&s->iomem, OBJECT(dev), &arm_sysctl_ops, s,                          "arm-sysctl", 0x1000);    sysbus_init_mmio(sd, &s->iomem);    qdev_init_gpio_in(dev, arm_sysctl_gpio_set, 2);    qdev_init_gpio_out(dev, &s->pl110_mux_ctrl, 1);}

static void aw_a10_pic_init(Object *obj){    AwA10PICState *s = AW_A10_PIC(obj);    SysBusDevice *dev = SYS_BUS_DEVICE(obj);     qdev_init_gpio_in(DEVICE(dev), aw_a10_pic_set_irq, AW_A10_PIC_INT_NR);     sysbus_init_irq(dev, &s->parent_irq);     sysbus_init_irq(dev, &s->parent_fiq);     memory_region_init_io(&s->iomem, OBJECT(s), &aw_a10_pic_ops, s,                           TYPE_AW_A10_PIC, 0x400);     sysbus_init_mmio(dev, &s->iomem);}

static int realview_i2c_init(SysBusDevice *dev){    RealViewI2CState *s = FROM_SYSBUS(RealViewI2CState, dev);    i2c_bus *bus;    bus = i2c_init_bus(&dev->qdev, "i2c");    s->bitbang = bitbang_i2c_init(bus);    memory_region_init_io(&s->iomem, &realview_i2c_ops, s,                          "realview-i2c", 0x1000);    sysbus_init_mmio(dev, &s->iomem);    return 0;}

static void aspeed_wdt_realize(DeviceState *dev, Error **errp){    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);    AspeedWDTState *s = ASPEED_WDT(dev);    s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, aspeed_wdt_timer_expired,                            dev);    memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_wdt_ops, s,                          TYPE_ASPEED_WDT, WDT_IO_REGION_SIZE);    sysbus_init_mmio(sbd, &s->iomem);}

static void xlx_iom_realize(DeviceState *dev, Error **errp){    XilinxUART *s = XILINX_IO_MODULE_UART(dev);    unsigned int i, rmap;    uint32_t *regmaps[3] = { &s->regs[0], &s->baud };    s->prefix = object_get_canonical_path(OBJECT(dev));    for (rmap = 0; rmap < ARRAY_SIZE(uart_reginfos); rmap++) {        for (i = 0; i < uart_reginfo_sizes[rmap]; ++i) {            DepRegisterInfo *r = &s->regs_infos[rmap][i];            *r = (DepRegisterInfo) {                .data = (uint8_t *)&regmaps[rmap][i],                .data_size = sizeof(uint32_t),                .access = &uart_reginfos[rmap][i],                .debug = XILINX_IO_MODULE_UART_ERR_DEBUG,                .prefix = s->prefix,                .opaque = s,            };            memory_region_init_io(&r->mem, OBJECT(dev), &iom_uart_ops, r,                                  r->access->name, 4);            memory_region_add_subregion(&s->iomem[rmap], i * 4, &r->mem);        }    }    if (s->cfg.use_rx || s->cfg.use_tx) {        qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx, uart_event,                                 NULL, s, NULL, true);    }}static void xlx_iom_init(Object *obj){    XilinxUART *s = XILINX_IO_MODULE_UART(obj);    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);    unsigned int i;    s->regs_infos[0] = s->regs_info0;    s->regs_infos[1] = s->regs_info1;    for (i = 0; i < ARRAY_SIZE(s->iomem); i++) {        char *region_name = g_strdup_printf("%s-%d", TYPE_XILINX_IO_MODULE_UART,                                            i);        memory_region_init_io(&s->iomem[i], obj, &iom_uart_ops, s,                              region_name, uart_reginfo_sizes[i] * 4);        g_free(region_name);        sysbus_init_mmio(sbd, &s->iomem[i]);    }    sysbus_init_irq(sbd, &s->irq_err);    sysbus_init_irq(sbd, &s->irq_tx);    sysbus_init_irq(sbd, &s->irq_rx);}

static int mpc8544_guts_initfn(SysBusDevice *dev){    GutsState *s;    s = FROM_SYSBUS(GutsState, SYS_BUS_DEVICE(dev));    memory_region_init_io(&s->iomem, &mpc8544_guts_ops, s,                          "mpc6544.guts", MPC8544_GUTS_MMIO_SIZE);    sysbus_init_mmio(dev, &s->iomem);    return 0;}

static void virtio_mmio_realizefn(DeviceState *d, Error **errp){    VirtIOMMIOProxy *proxy = VIRTIO_MMIO(d);    SysBusDevice *sbd = SYS_BUS_DEVICE(d);    qbus_create_inplace(&proxy->bus, sizeof(proxy->bus), TYPE_VIRTIO_MMIO_BUS,                        d, NULL);    sysbus_init_irq(sbd, &proxy->irq);    memory_region_init_io(&proxy->iomem, OBJECT(d), &virtio_mem_ops, proxy,                          TYPE_VIRTIO_MMIO, 0x200);    sysbus_init_mmio(sbd, &proxy->iomem);}

static void stm32f2xx_timer_init(Object *obj){    STM32F2XXTimerState *s = STM32F2XXTIMER(obj);    sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);    memory_region_init_io(&s->iomem, obj, &stm32f2xx_timer_ops, s,                          "stm32f2xx_timer", 0x4000);    sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem);    s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, stm32f2xx_timer_interrupt, s);}

static int strongarm_pic_initfn(SysBusDevice *dev){    StrongARMPICState *s = FROM_SYSBUS(StrongARMPICState, dev);    qdev_init_gpio_in(&dev->qdev, strongarm_pic_set_irq, SA_PIC_SRCS);    memory_region_init_io(&s->iomem, &strongarm_pic_ops, s, "pic", 0x1000);    sysbus_init_mmio(dev, &s->iomem);    sysbus_init_irq(dev, &s->irq);    sysbus_init_irq(dev, &s->fiq);    return 0;}

static int milkymist_vgafb_init(SysBusDevice *dev){    MilkymistVgafbState *s = FROM_SYSBUS(typeof(*s), dev);    memory_region_init_io(&s->regs_region, OBJECT(s), &vgafb_mmio_ops, s,            "milkymist-vgafb", R_MAX * 4);    sysbus_init_mmio(dev, &s->regs_region);    s->con = graphic_console_init(DEVICE(dev), &vgafb_ops, s);    return 0;}

static int arm_sysctl_init1(SysBusDevice *dev){    arm_sysctl_state *s = FROM_SYSBUS(arm_sysctl_state, dev);    int iomemtype;    iomemtype = cpu_register_io_memory(arm_sysctl_readfn,                                       arm_sysctl_writefn, s,                                       DEVICE_NATIVE_ENDIAN);    sysbus_init_mmio(dev, 0x1000, iomemtype);    /* ??? Save/restore.  */    return 0;}

static int ox820_sysctrl_mfa_init(SysBusDevice *dev){    ox820_sysctrl_mfa_state *s = FROM_SYSBUS(ox820_sysctrl_mfa_state, dev);    memory_region_init_io(&s->iomem0, &ox820_sysctrl_mfa0_ops, s, "ox820-sysctrl-mfa", 0x4);    memory_region_init_io(&s->iomem1, &ox820_sysctrl_mfa1_ops, s, "ox820-sysctrl-mfa", 0x4);    memory_region_init_io(&s->iomem2, &ox820_sysctrl_mfa2_ops, s, "ox820-sysctrl-mfa", 0x10);    sysbus_init_mmio(dev, &s->iomem0);    sysbus_init_mmio(dev, &s->iomem1);    sysbus_init_mmio(dev, &s->iomem2);    s->mfa_secsel_ctrl = 0;    s->mfa_tersel_ctrl = 0;    s->mfa_quatsel_ctrl = 0;    s->mfa_debugsel_ctrl = 0;    s->mfa_altsel_ctrl = 0;    s->mfa_pullup_ctrl = 0;    vmstate_register(&dev->qdev, -1, &vmstate_ox820_sysctrl_mfa, s);    return 0;}

static int apc_init1(SysBusDevice *dev){    APCState *s = FROM_SYSBUS(APCState, dev);    sysbus_init_irq(dev, &s->cpu_halt);    /* Power management (APC) XXX: not a Slavio device */    memory_region_init_io(&s->iomem, &apc_mem_ops, s,                          "apc", MISC_SIZE);    sysbus_init_mmio(dev, &s->iomem);    return 0;}

static int pl022_init(SysBusDevice *dev){    pl022_state *s = FROM_SYSBUS(pl022_state, dev);    memory_region_init_io(&s->iomem, &pl022_ops, s, "pl022", 0x1000);    sysbus_init_mmio(dev, &s->iomem);    sysbus_init_irq(dev, &s->irq);    s->ssi = ssi_create_bus(&dev->qdev, "ssi");    pl022_reset(s);    vmstate_register(&dev->qdev, -1, &vmstate_pl022, s);    return 0;}

static void a15mp_priv_initfn(Object *obj){    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);    A15MPPrivState *s = A15MPCORE_PRIV(obj);    memory_region_init(&s->container, obj, "a15mp-priv-container", 0x8000);    sysbus_init_mmio(sbd, &s->container);    sysbus_init_child_obj(obj, "gic", &s->gic, sizeof(s->gic),                          gic_class_name());    qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2);}

static int arm_mptimer_init(SysBusDevice *dev){    arm_mptimer_state *s = FROM_SYSBUS(arm_mptimer_state, dev);    int i;    if (s->num_cpu < 1 || s->num_cpu > MAX_CPUS) {        hw_error("%s: num-cpu must be between 1 and %d/n", __func__, MAX_CPUS);    }    /* We implement one timer and one watchdog block per CPU, and     * expose multiple MMIO regions:     *  * region 0 is "timer for this core"     *  * region 1 is "watchdog for this core"     *  * region 2 is "timer for core 0"     *  * region 3 is "watchdog for core 0"     *  * region 4 is "timer for core 1"     *  * region 5 is "watchdog for core 1"     * and so on.     * The outgoing interrupt lines are     *  * timer for core 0     *  * watchdog for core 0     *  * timer for core 1     *  * watchdog for core 1     * and so on.     */    memory_region_init_io(&s->iomem[0], &arm_thistimer_ops, s,                          "arm_mptimer_timer", 0x20);    sysbus_init_mmio(dev, &s->iomem[0]);    memory_region_init_io(&s->iomem[1], &arm_thiswdog_ops, s,                          "arm_mptimer_wdog", 0x20);    sysbus_init_mmio(dev, &s->iomem[1]);    for (i = 0; i < (s->num_cpu * 2); i++) {        timerblock *tb = &s->timerblock[i];        tb->timer = qemu_new_timer_ns(vm_clock, timerblock_tick, tb);        sysbus_init_irq(dev, &tb->irq);        memory_region_init_io(&tb->iomem, &timerblock_ops, tb,                              "arm_mptimer_timerblock", 0x20);        sysbus_init_mmio(dev, &tb->iomem);    }    return 0;}

void gic_init_irqs_and_mmio(GICState *s, qemu_irq_handler handler,                            const MemoryRegionOps *ops){    SysBusDevice *sbd = SYS_BUS_DEVICE(s);    int i = s->num_irq - GIC_INTERNAL;    /* For the GIC, also expose incoming GPIO lines for PPIs for each CPU.     * GPIO array layout is thus:     *  [0..N-1] SPIs     *  [N..N+31] PPIs for CPU 0     *  [N+32..N+63] PPIs for CPU 1     *   ...     */    if (s->revision != REV_NVIC) {        i += (GIC_INTERNAL * s->num_cpu);    }    qdev_init_gpio_in(DEVICE(s), handler, i);    for (i = 0; i < s->num_cpu; i++) {        sysbus_init_irq(sbd, &s->parent_irq[i]);    }    for (i = 0; i < s->num_cpu; i++) {        sysbus_init_irq(sbd, &s->parent_fiq[i]);    }    /* Distributor */    memory_region_init_io(&s->iomem, OBJECT(s), ops, s, "gic_dist", 0x1000);    sysbus_init_mmio(sbd, &s->iomem);    if (s->revision != REV_NVIC) {        /* This is the main CPU interface "for this core". It is always         * present because it is required by both software emulation and KVM.         * NVIC is not handled here because its CPU interface is different,         * neither it can use KVM.         */        memory_region_init_io(&s->cpuiomem[0], OBJECT(s), ops ? &ops[1] : NULL,                              s, "gic_cpu", s->revision == 2 ? 0x1000 : 0x100);        sysbus_init_mmio(sbd, &s->cpuiomem[0]);    }}

static void etsec_instance_init(Object *obj){    eTSEC        *etsec = ETSEC_COMMON(obj);    SysBusDevice *sbd   = SYS_BUS_DEVICE(obj);    memory_region_init_io(&etsec->io_area, OBJECT(etsec), &etsec_ops, etsec,                          "eTSEC", 0x1000);    sysbus_init_mmio(sbd, &etsec->io_area);    sysbus_init_irq(sbd, &etsec->tx_irq);    sysbus_init_irq(sbd, &etsec->rx_irq);    sysbus_init_irq(sbd, &etsec->err_irq);}

static void arm_sysctl_init1(SysBusDevice *dev){    arm_sysctl_state *s = FROM_SYSBUS(arm_sysctl_state, dev);    int iomemtype;    /* The MPcore bootloader uses these flags to start secondary CPUs.       We don't use a bootloader, so do this here.  */    s->flags = 3;    iomemtype = cpu_register_io_memory(arm_sysctl_readfn,                                       arm_sysctl_writefn, s);    sysbus_init_mmio(dev, 0x1000, iomemtype);    /* ??? Save/restore.  */}

static void imx_gpio_realize(DeviceState *dev, Error **errp){    IMXGPIOState *s = IMX_GPIO(dev);    memory_region_init_io(&s->iomem, OBJECT(s), &imx_gpio_ops, s,                          TYPE_IMX_GPIO, IMX_GPIO_MEM_SIZE);    qdev_init_gpio_in(DEVICE(s), imx_gpio_set, IMX_GPIO_PIN_COUNT);    qdev_init_gpio_out(DEVICE(s), s->output, IMX_GPIO_PIN_COUNT);    sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq);    sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);}

static int pl022_init(SysBusDevice *sbd){    DeviceState *dev = DEVICE(sbd);    PL022State *s = PL022(dev);    memory_region_init_io(&s->iomem, OBJECT(s), &pl022_ops, s, "pl022", 0x1000);    sysbus_init_mmio(sbd, &s->iomem);    sysbus_init_irq(sbd, &s->irq);    s->ssi = ssi_create_bus(dev, "ssi");    pl022_reset(s);    vmstate_register(dev, -1, &vmstate_pl022, s);    return 0;}