自学教程：C++ sysbus_mmio_map函数代码示例

static void init_cpus(const char *cpu_model, const char *privdev,                      hwaddr periphbase, qemu_irq *pic){    ObjectClass *cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model);    DeviceState *dev;    SysBusDevice *busdev;    int n;    if (!cpu_oc) {        fprintf(stderr, "Unable to find CPU definition/n");        exit(1);    }    /* Create the actual CPUs */    for (n = 0; n < smp_cpus; n++) {        Object *cpuobj = object_new(object_class_get_name(cpu_oc));        Error *err = NULL;        if (object_property_find(cpuobj, "reset-cbar", NULL)) {            object_property_set_int(cpuobj, periphbase,                                    "reset-cbar", &error_abort);        }        object_property_set_bool(cpuobj, true, "realized", &err);        if (err) {            error_report("%s", error_get_pretty(err));            exit(1);        }    }    /* Create the private peripheral devices (including the GIC);     * this must happen after the CPUs are created because a15mpcore_priv     * wires itself up to the CPU's generic_timer gpio out lines.     */    dev = qdev_create(NULL, privdev);    qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);    qdev_init_nofail(dev);    busdev = SYS_BUS_DEVICE(dev);    sysbus_mmio_map(busdev, 0, periphbase);    /* Interrupts [42:0] are from the motherboard;     * [47:43] are reserved; [63:48] are daughterboard     * peripherals. Note that some documentation numbers     * external interrupts starting from 32 (because there     * are internal interrupts 0..31).     */    for (n = 0; n < 64; n++) {        pic[n] = qdev_get_gpio_in(dev, n);    }    /* Connect the CPUs to the GIC */    for (n = 0; n < smp_cpus; n++) {        DeviceState *cpudev = DEVICE(qemu_get_cpu(n));        sysbus_connect_irq(busdev, n, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));    }}

static void openrisc_sim_net_init(hwaddr base, hwaddr descriptors,                                  int num_cpus, qemu_irq **cpu_irqs,                                  int irq_pin, NICInfo *nd){    DeviceState *dev;    SysBusDevice *s;    int i;    dev = qdev_create(NULL, "open_eth");    qdev_set_nic_properties(dev, nd);    qdev_init_nofail(dev);    s = SYS_BUS_DEVICE(dev);    for (i = 0; i < num_cpus; i++) {        sysbus_connect_irq(s, 0, cpu_irqs[i][irq_pin]);    }    sysbus_mmio_map(s, 0, base);    sysbus_mmio_map(s, 1, descriptors);}

/* Legacy helper function.  */void arm_sysctl_init(uint32_t base, uint32_t sys_id, uint32_t proc_id){    DeviceState *dev;    dev = qdev_create(NULL, "realview_sysctl");    qdev_prop_set_uint32(dev, "sys_id", sys_id);    qdev_init_nofail(dev);    qdev_prop_set_uint32(dev, "proc_id", proc_id);    sysbus_mmio_map(sysbus_from_qdev(dev), 0, base);}

static void slavio_timer_init_all(hwaddr addr, qemu_irq master_irq,                                  qemu_irq *cpu_irqs, unsigned int num_cpus){    DeviceState *dev;    SysBusDevice *s;    unsigned int i;    dev = qdev_create(NULL, "slavio_timer");    qdev_prop_set_uint32(dev, "num_cpus", num_cpus);    qdev_init_nofail(dev);    s = SYS_BUS_DEVICE(dev);    sysbus_connect_irq(s, 0, master_irq);    sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET);    for (i = 0; i < MAX_CPUS; i++) {        sysbus_mmio_map(s, i + 1, addr + (hwaddr)CPU_TIMER_OFFSET(i));        sysbus_connect_irq(s, i + 1, cpu_irqs[i]);    }}

static DeviceState *stm32_init_periph(DeviceState *dev, stm32_periph_t periph,                                        hwaddr addr, qemu_irq irq){    qdev_init_nofail(dev);    sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);    if (irq) {        sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq);    }    return dev;}

DeviceState *s5l8930_spi_init(target_phys_addr_t base, qemu_irq irq){    DeviceState *dev = qdev_create(NULL, "s5l8930.spi");    //fprintf(stderr, "%s: irq %x base 0x%08x/n", __FUNCTION__, print_irq(irq), base);    qdev_init_nofail(dev);    sysbus_mmio_map(sysbus_from_qdev(dev), 0, base);    sysbus_connect_irq(sysbus_from_qdev(dev), 0, irq);    return dev;}

/* SS-5 TCX AFX register */static void afx_init(hwaddr addr){    DeviceState *dev;    SysBusDevice *s;    dev = qdev_create(NULL, TYPE_TCX_AFX);    qdev_init_nofail(dev);    s = SYS_BUS_DEVICE(dev);    sysbus_mmio_map(s, 0, addr);}

static inline void zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq,                                         bool is_qspi){    DeviceState *dev;    SysBusDevice *busdev;    SSIBus *spi;    DeviceState *flash_dev;    int i, j;    int num_busses =  is_qspi ? NUM_QSPI_BUSSES : 1;    int num_ss = is_qspi ? NUM_QSPI_FLASHES : NUM_SPI_FLASHES;    dev = qdev_create(NULL, "xilinx,spips");    qdev_prop_set_uint8(dev, "num-txrx-bytes", is_qspi ? 4 : 1);    qdev_prop_set_uint8(dev, "num-ss-bits", num_ss);    qdev_prop_set_uint8(dev, "num-busses", num_busses);    qdev_init_nofail(dev);    busdev = sysbus_from_qdev(dev);    sysbus_mmio_map(busdev, 0, base_addr);    if (is_qspi) {        sysbus_mmio_map(busdev, 1, 0xFC000000);    }    sysbus_connect_irq(busdev, 0, irq);    for (i = 0; i < num_busses; ++i) {        char bus_name[16];        qemu_irq cs_line;        snprintf(bus_name, 16, "spi%d", i);        spi = (SSIBus *)qdev_get_child_bus(dev, bus_name);        for (j = 0; j < num_ss; ++j) {            flash_dev = ssi_create_slave_no_init(spi, "m25p80");            qdev_prop_set_string(flash_dev, "partname", "n25q128");            qdev_init_nofail(flash_dev);            cs_line = qdev_get_gpio_in(flash_dev, 0);            sysbus_connect_irq(busdev, i * num_ss + j + 1, cs_line);        }    }}

static void pl330_create(uint32_t base, qemu_irq irq, int nreq){    SysBusDevice *busdev;    DeviceState *dev;    dev = qdev_create(NULL, "pl330");    qdev_prop_set_uint8(dev, "num_periph_req",  nreq);    qdev_init_nofail(dev);    busdev = SYS_BUS_DEVICE(dev);    sysbus_mmio_map(busdev, 0, base);    sysbus_connect_irq(busdev, 0, irq);}

static inline DeviceState *moxie_intc_create(hwaddr base, qemu_irq irq, int kind_of_intr){    DeviceState *dev;    dev = qdev_create(NULL, "moxie,intc");    qdev_prop_set_uint32(dev, "kind-of-intr", kind_of_intr);    qdev_init_nofail(dev);    sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);    sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq);    return dev;}

static void xlnx_zynqmp_pmu_init(MachineState *machine){    XlnxZynqMPPMUSoCState *pmu = g_new0(XlnxZynqMPPMUSoCState, 1);    MemoryRegion *address_space_mem = get_system_memory();    MemoryRegion *pmu_rom = g_new(MemoryRegion, 1);    MemoryRegion *pmu_ram = g_new(MemoryRegion, 1);    XlnxZynqMPIPI *ipi[XLNX_ZYNQMP_PMU_NUM_IPIS];    qemu_irq irq[32];    int i;    /* Create the ROM */    memory_region_init_rom(pmu_rom, NULL, "xlnx-zynqmp-pmu.rom",                           XLNX_ZYNQMP_PMU_ROM_SIZE, &error_fatal);    memory_region_add_subregion(address_space_mem, XLNX_ZYNQMP_PMU_ROM_ADDR,                                pmu_rom);    /* Create the RAM */    memory_region_init_ram(pmu_ram, NULL, "xlnx-zynqmp-pmu.ram",                           machine->ram_size, &error_fatal);    memory_region_add_subregion(address_space_mem, XLNX_ZYNQMP_PMU_RAM_ADDR,                                pmu_ram);    /* Create the PMU device */    object_initialize(pmu, sizeof(XlnxZynqMPPMUSoCState), TYPE_XLNX_ZYNQMP_PMU_SOC);    object_property_add_child(OBJECT(machine), "pmu", OBJECT(pmu),                              &error_abort);    object_property_set_bool(OBJECT(pmu), true, "realized", &error_fatal);    for (i = 0; i < 32; i++) {        irq[i] = qdev_get_gpio_in(DEVICE(&pmu->intc), i);    }    /* Create and connect the IPI device */    for (i = 0; i < XLNX_ZYNQMP_PMU_NUM_IPIS; i++) {        ipi[i] = g_new0(XlnxZynqMPIPI, 1);        object_initialize(ipi[i], sizeof(XlnxZynqMPIPI), TYPE_XLNX_ZYNQMP_IPI);        qdev_set_parent_bus(DEVICE(ipi[i]), sysbus_get_default());    }    for (i = 0; i < XLNX_ZYNQMP_PMU_NUM_IPIS; i++) {        object_property_set_bool(OBJECT(ipi[i]), true, "realized",                                 &error_abort);        sysbus_mmio_map(SYS_BUS_DEVICE(ipi[i]), 0, ipi_addr[i]);        sysbus_connect_irq(SYS_BUS_DEVICE(ipi[i]), 0, irq[ipi_irq[i]]);    }    /* Load the kernel */    microblaze_load_kernel(&pmu->cpu, XLNX_ZYNQMP_PMU_RAM_ADDR,                           machine->ram_size,                           machine->initrd_filename,                           machine->dtb,                           NULL);}

static void mch_init_dmar(MCHPCIState *mch){    PCIBus *pci_bus = PCI_BUS(qdev_get_parent_bus(DEVICE(mch)));    mch->iommu = INTEL_IOMMU_DEVICE(qdev_create(NULL, TYPE_INTEL_IOMMU_DEVICE));    object_property_add_child(OBJECT(mch), "intel-iommu",                              OBJECT(mch->iommu), NULL);    qdev_init_nofail(DEVICE(mch->iommu));    sysbus_mmio_map(SYS_BUS_DEVICE(mch->iommu), 0, Q35_HOST_BRIDGE_IOMMU_ADDR);    pci_setup_iommu(pci_bus, q35_host_dma_iommu, mch->iommu);}

static void apc_init(hwaddr power_base, qemu_irq cpu_halt){    DeviceState *dev;    SysBusDevice *s;    dev = qdev_create(NULL, "apc");    qdev_init_nofail(dev);    s = SYS_BUS_DEVICE(dev);    /* Power management (APC) XXX: not a Slavio device */    sysbus_mmio_map(s, 0, power_base);    sysbus_connect_irq(s, 0, cpu_halt);}

static void digic_realize(DeviceState *dev, Error **errp){    DigicState *s = DIGIC(dev);    Error *err = NULL;    SysBusDevice *sbd;    int i;    object_property_set_bool(OBJECT(&s->cpu), true, "reset-hivecs", &err);    if (err != NULL) {        error_propagate(errp, err);        return;    }    object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);    if (err != NULL) {        error_propagate(errp, err);        return;    }    for (i = 0; i < DIGIC4_NB_TIMERS; i++) {        object_property_set_bool(OBJECT(&s->timer[i]), true, "realized", &err);        if (err != NULL) {            error_propagate(errp, err);            return;        }        sbd = SYS_BUS_DEVICE(&s->timer[i]);        sysbus_mmio_map(sbd, 0, DIGIC4_TIMER_BASE(i));    }    qdev_prop_set_chr(DEVICE(&s->uart), "chardev", serial_hds[0]);    object_property_set_bool(OBJECT(&s->uart), true, "realized", &err);    if (err != NULL) {        error_propagate(errp, err);        return;    }    sbd = SYS_BUS_DEVICE(&s->uart);    sysbus_mmio_map(sbd, 0, DIGIC_UART_BASE);}

static inline void zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq,                                         bool is_qspi){    DeviceState *dev;    SysBusDevice *busdev;    SSIBus *spi;    DeviceState *flash_dev;    int i, j;    int num_busses =  is_qspi ? NUM_QSPI_BUSSES : 1;    int num_ss = is_qspi ? NUM_QSPI_FLASHES : NUM_SPI_FLASHES;    dev = qdev_create(NULL, is_qspi ? "xlnx.ps7-qspi" : "cdns.spi-r1p6");    qdev_prop_set_uint8(dev, "num-txrx-bytes", is_qspi ? 4 : 1);    qdev_prop_set_uint8(dev, "num-ss-bits", num_ss);    qdev_prop_set_uint8(dev, "num-busses", num_busses);    qdev_init_nofail(dev);    busdev = SYS_BUS_DEVICE(dev);    sysbus_mmio_map(busdev, 0, base_addr);    if (is_qspi) {        sysbus_mmio_map(busdev, 1, 0xFC000000);    }    sysbus_connect_irq(busdev, 0, irq);    for (i = 0; i < num_busses; ++i) {        char bus_name[16];        qemu_irq cs_line;        snprintf(bus_name, 16, "spi%d", i);        spi = (SSIBus *)qdev_get_child_bus(dev, bus_name);        for (j = 0; j < num_ss; ++j) {            flash_dev = ssi_create_slave(spi, "n25q128");            cs_line = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0);            sysbus_connect_irq(busdev, i * num_ss + j + 1, cs_line);        }    }}

static void gem_init(NICInfo *nd, uint32_t base, qemu_irq irq){    DeviceState *dev;    SysBusDevice *s;    qemu_check_nic_model(nd, "cadence_gem");    dev = qdev_create(NULL, "cadence_gem");    qdev_set_nic_properties(dev, nd);    qdev_init_nofail(dev);    s = sysbus_from_qdev(dev);    sysbus_mmio_map(s, 0, base);    sysbus_connect_irq(s, 0, irq);}

/* Legacy helper function.  Should go away when machine config files are   implemented.  */void smc91c111_init(NICInfo *nd, uint32_t base, qemu_irq irq){    DeviceState *dev;    SysBusDevice *s;    qemu_check_nic_model(nd, "smc91c111");    dev = qdev_create(NULL, "smc91c111");    qdev_set_nic_properties(dev, nd);    qdev_init_nofail(dev);    s = SYS_BUS_DEVICE(dev);    sysbus_mmio_map(s, 0, base);    sysbus_connect_irq(s, 0, irq);}

/* Legacy helper function.  Should go away when machine config files are   implemented.  */void smc91c111_init(NICInfo *nd, uint32_t base, qemu_irq irq){    DeviceState *dev;    SysBusDevice *s;    qemu_check_nic_model(nd, "smc91c111");    dev = qdev_create(NULL, "smc91c111");    qdev_set_netdev(dev, nd);    qdev_init(dev);    s = sysbus_from_qdev(dev);    sysbus_mmio_map(s, 0, base);    sysbus_connect_irq(s, 0, irq);}

static void idreg_init(hwaddr addr){    DeviceState *dev;    SysBusDevice *s;    dev = qdev_create(NULL, TYPE_MACIO_ID_REGISTER);    qdev_init_nofail(dev);    s = SYS_BUS_DEVICE(dev);    sysbus_mmio_map(s, 0, addr);    cpu_physical_memory_write_rom(&address_space_memory,                                  addr, idreg_data, sizeof(idreg_data));}

FWCfgState *fw_cfg_init(uint32_t ctl_port, uint32_t data_port,                        hwaddr ctl_addr, hwaddr data_addr){    DeviceState *dev;    SysBusDevice *d;    FWCfgState *s;    dev = qdev_create(NULL, TYPE_FW_CFG);    qdev_prop_set_uint32(dev, "ctl_iobase", ctl_port);    qdev_prop_set_uint32(dev, "data_iobase", data_port);    d = SYS_BUS_DEVICE(dev);    s = FW_CFG(dev);    assert(!object_resolve_path(FW_CFG_PATH, NULL));    object_property_add_child(qdev_get_machine(), FW_CFG_NAME, OBJECT(s), NULL);    qdev_init_nofail(dev);    if (ctl_addr) {        sysbus_mmio_map(d, 0, ctl_addr);    }    if (data_addr) {        sysbus_mmio_map(d, 1, data_addr);    }    fw_cfg_add_bytes(s, FW_CFG_SIGNATURE, (char *)"QEMU", 4);    fw_cfg_add_bytes(s, FW_CFG_UUID, qemu_uuid, 16);    fw_cfg_add_i16(s, FW_CFG_NOGRAPHIC, (uint16_t)(display_type == DT_NOGRAPHIC));    fw_cfg_add_i16(s, FW_CFG_NB_CPUS, (uint16_t)smp_cpus);    fw_cfg_add_i16(s, FW_CFG_BOOT_MENU, (uint16_t)boot_menu);    fw_cfg_bootsplash(s);    fw_cfg_reboot(s);    s->machine_ready.notify = fw_cfg_machine_ready;    qemu_add_machine_init_done_notifier(&s->machine_ready);    return s;}

static void init_cpus(const char *cpu_type, const char *privdev,                      hwaddr periphbase, qemu_irq *pic, bool secure){    DeviceState *dev;    SysBusDevice *busdev;    int n;    /* Create the actual CPUs */    for (n = 0; n < smp_cpus; n++) {        Object *cpuobj = object_new(cpu_type);        if (!secure) {            object_property_set_bool(cpuobj, false, "has_el3", NULL);        }        if (object_property_find(cpuobj, "reset-cbar", NULL)) {            object_property_set_int(cpuobj, periphbase,                                    "reset-cbar", &error_abort);        }        object_property_set_bool(cpuobj, true, "realized", &error_fatal);    }    /* Create the private peripheral devices (including the GIC);     * this must happen after the CPUs are created because a15mpcore_priv     * wires itself up to the CPU's generic_timer gpio out lines.     */    dev = qdev_create(NULL, privdev);    qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);    qdev_init_nofail(dev);    busdev = SYS_BUS_DEVICE(dev);    sysbus_mmio_map(busdev, 0, periphbase);    /* Interrupts [42:0] are from the motherboard;     * [47:43] are reserved; [63:48] are daughterboard     * peripherals. Note that some documentation numbers     * external interrupts starting from 32 (because there     * are internal interrupts 0..31).     */    for (n = 0; n < 64; n++) {        pic[n] = qdev_get_gpio_in(dev, n);    }    /* Connect the CPUs to the GIC */    for (n = 0; n < smp_cpus; n++) {        DeviceState *cpudev = DEVICE(qemu_get_cpu(n));        sysbus_connect_irq(busdev, n, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));        sysbus_connect_irq(busdev, n + smp_cpus,                           qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));    }}

static int lm32_sys_init(SysBusDevice *dev){    LM32SysState *s = FROM_SYSBUS(typeof(*s), dev);    memory_region_init_io(&s->iomem, &sys_ops , s, "sys", R_MAX * 4);    sysbus_init_mmio(dev, &s->iomem);    /* Note: This device is not created in the board initialization,     * instead it has to be added with the -device parameter. Therefore,     * the device maps itself. */    sysbus_mmio_map(dev, 0, s->base);    return 0;}

static void *iommu_init(hwaddr addr, uint32_t version, qemu_irq irq){    DeviceState *dev;    SysBusDevice *s;    dev = qdev_create(NULL, "iommu");    qdev_prop_set_uint32(dev, "version", version);    qdev_init_nofail(dev);    s = SYS_BUS_DEVICE(dev);    sysbus_connect_irq(s, 0, irq);    sysbus_mmio_map(s, 0, addr);    return s;}

static void cg3_init(hwaddr addr, qemu_irq irq, int vram_size, int width,                     int height, int depth){    DeviceState *dev;    SysBusDevice *s;    dev = qdev_create(NULL, "cgthree");    qdev_prop_set_uint32(dev, "vram-size", vram_size);    qdev_prop_set_uint16(dev, "width", width);    qdev_prop_set_uint16(dev, "height", height);    qdev_prop_set_uint16(dev, "depth", depth);    qdev_prop_set_uint64(dev, "prom-addr", addr);    qdev_init_nofail(dev);    s = SYS_BUS_DEVICE(dev);    /* FCode ROM */    sysbus_mmio_map(s, 0, addr);    /* DAC */    sysbus_mmio_map(s, 1, addr + 0x400000ULL);    /* 8-bit plane */    sysbus_mmio_map(s, 2, addr + 0x800000ULL);    sysbus_connect_irq(s, 0, irq);}

static void ioapic_init(IsaIrqState *isa_irq_state){    DeviceState *dev;    SysBusDevice *d;    unsigned int i;    dev = qdev_create(NULL, "ioapic");    qdev_init_nofail(dev);    d = sysbus_from_qdev(dev);    sysbus_mmio_map(d, 0, 0xfec00000);    for (i = 0; i < IOAPIC_NUM_PINS; i++) {        isa_irq_state->ioapic[i] = qdev_get_gpio_in(dev, i);    }}

static void ram_init(target_phys_addr_t addr, ram_addr_t RAM_size){    DeviceState *dev;    SysBusDevice *s;    RamDevice *d;    /* allocate RAM */    dev = qdev_create(NULL, "memory");    s = sysbus_from_qdev(dev);    d = FROM_SYSBUS(RamDevice, s);    d->size = RAM_size;    qdev_init_nofail(dev);    sysbus_mmio_map(s, 0, addr);}

static void ram_init(hwaddr addr, ram_addr_t RAM_size){    DeviceState *dev;    SysBusDevice *s;    RamDevice *d;    /* allocate RAM */    dev = qdev_create(NULL, TYPE_SUN4U_MEMORY);    s = SYS_BUS_DEVICE(dev);    d = SUN4U_RAM(dev);    d->size = RAM_size;    qdev_init_nofail(dev);    sysbus_mmio_map(s, 0, addr);}

static void ram_init(hwaddr addr, ram_addr_t RAM_size){    DeviceState *dev;    SysBusDevice *s;    RamDevice *d;    /* allocate RAM */    dev = qdev_create(NULL, "memory");    s = SYS_BUS_DEVICE(dev);    d = FROM_SYSBUS(RamDevice, s);    d->size = RAM_size;    qdev_init_nofail(dev);    sysbus_mmio_map(s, 0, addr);}

static void openrisc_sim_ompic_init(hwaddr base, int num_cpus,                                    qemu_irq **cpu_irqs, int irq_pin){    DeviceState *dev;    SysBusDevice *s;    int i;    dev = qdev_create(NULL, "or1k-ompic");    qdev_prop_set_uint32(dev, "num-cpus", num_cpus);    qdev_init_nofail(dev);    s = SYS_BUS_DEVICE(dev);    for (i = 0; i < num_cpus; i++) {        sysbus_connect_irq(s, i, cpu_irqs[i][irq_pin]);    }    sysbus_mmio_map(s, 0, base);}