自学教程：C++ CLEAR_BIT函数代码示例

/**  * @brief  Disable the Debug Module during STANDBY mode         * @param  None  * @retval None  */void HAL_DisableDBGStandbyMode(void){  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);}

/**  * @brief Disables CORTEX M4 SEVONPEND bit.   * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes   *       WFE to wake up when an interrupt moves from inactive to pended.           * @retval None  */void HAL_PWR_DisableSEVOnPend(void){  /* Clear SEVONPEND bit of Cortex System Control Register */  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));}

/**  * @brief This function handles FLASH interrupt request.  * @retval None  */void HAL_FLASH_IRQHandler(void){  uint32_t addresstmp = 0;    /* Check FLASH operation error flags */  if( __HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR)     ||       __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR)     ||       __HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR)     || #if defined(FLASH_SR_RDERR)      __HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR)      || #endif /* FLASH_SR_RDERR */#if defined(FLASH_SR_OPTVERRUSR)      __HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERRUSR) || #endif /* FLASH_SR_OPTVERRUSR */      __HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) )  {    if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE)    {      /* Return the faulty sector */      addresstmp = pFlash.Page;      pFlash.Page = 0xFFFFFFFFU;    }    else    {      /* Return the faulty address */      addresstmp = pFlash.Address;    }    /* Save the Error code */    FLASH_SetErrorCode();        /* FLASH error interrupt user callback */    HAL_FLASH_OperationErrorCallback(addresstmp);    /* Stop the procedure ongoing */    pFlash.ProcedureOnGoing = FLASH_PROC_NONE;  }  /* Check FLASH End of Operation flag  */  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))  {    /* Clear FLASH End of Operation pending bit */    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);        /* Process can continue only if no error detected */    if(pFlash.ProcedureOnGoing != FLASH_PROC_NONE)    {      if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE)      {        /* Nb of pages to erased can be decreased */        pFlash.NbPagesToErase--;        /* Check if there are still pages to erase */        if(pFlash.NbPagesToErase != 0)        {          addresstmp = pFlash.Page;          /*Indicate user which sector has been erased */          HAL_FLASH_EndOfOperationCallback(addresstmp);          /*Increment sector number*/          addresstmp = pFlash.Page + FLASH_PAGE_SIZE;          pFlash.Page = addresstmp;          /* If the erase operation is completed, disable the ERASE Bit */          CLEAR_BIT(FLASH->PECR, FLASH_PECR_ERASE);          FLASH_PageErase(addresstmp);        }        else        {          /* No more pages to Erase, user callback can be called. */          /* Reset Sector and stop Erase pages procedure */          pFlash.Page = addresstmp = 0xFFFFFFFFU;          pFlash.ProcedureOnGoing = FLASH_PROC_NONE;          /* FLASH EOP interrupt user callback */          HAL_FLASH_EndOfOperationCallback(addresstmp);        }      }      else      {          /* If the program operation is completed, disable the PROG Bit */          CLEAR_BIT(FLASH->PECR, FLASH_PECR_PROG);          /* Program ended. Return the selected address */          /* FLASH EOP interrupt user callback */          HAL_FLASH_EndOfOperationCallback(pFlash.Address);                  /* Reset Address and stop Program procedure */          pFlash.Address = 0xFFFFFFFFU;          pFlash.ProcedureOnGoing = FLASH_PROC_NONE;      }    }  }    if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE)  {//.........这里部分代码省略.........

/**  * @brief  De-initialize registers of the selected ADC instance  *         to their default reset values.  * @note   To reset all ADC instances quickly (perform a hard reset),  *         use function @ref LL_ADC_CommonDeInit().  * @note   If this functions returns error status, it means that ADC instance  *         is in an unknown state.  *         In this case, perform a hard reset using high level  *         clock source RCC ADC reset.  *         Refer to function @ref LL_ADC_CommonDeInit().  * @param  ADCx ADC instance  * @retval An ErrorStatus enumeration value:  *          - SUCCESS: ADC registers are de-initialized  *          - ERROR: ADC registers are not de-initialized  */ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx){  ErrorStatus status = SUCCESS;    __IO uint32_t timeout_cpu_cycles = 0U;    /* Check the parameters */  assert_param(IS_ADC_ALL_INSTANCE(ADCx));    /* Disable ADC instance if not already disabled.                            */  if(LL_ADC_IsEnabled(ADCx) == 1U)  {    /* Set ADC group regular trigger source to SW start to ensure to not      */    /* have an external trigger event occurring during the conversion stop    */    /* ADC disable process.                                                   */    LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE);        /* Stop potential ADC conversion on going on ADC group regular.           */    if(LL_ADC_REG_IsConversionOngoing(ADCx) != 0U)    {      if(LL_ADC_REG_IsStopConversionOngoing(ADCx) == 0U)      {        LL_ADC_REG_StopConversion(ADCx);      }    }        /* Wait for ADC conversions are effectively stopped                       */    timeout_cpu_cycles = ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES;    while (LL_ADC_REG_IsStopConversionOngoing(ADCx) == 1U)    {      if(timeout_cpu_cycles-- == 0U)      {        /* Time-out error */        status = ERROR;      }    }        /* Disable the ADC instance */    LL_ADC_Disable(ADCx);        /* Wait for ADC instance is effectively disabled */    timeout_cpu_cycles = ADC_TIMEOUT_DISABLE_CPU_CYCLES;    while (LL_ADC_IsDisableOngoing(ADCx) == 1U)    {      if(timeout_cpu_cycles-- == 0U)      {        /* Time-out error */        status = ERROR;      }    }  }    /* Check whether ADC state is compliant with expected state */  if(READ_BIT(ADCx->CR,              (  ADC_CR_ADSTP | ADC_CR_ADSTART               | ADC_CR_ADDIS | ADC_CR_ADEN   )             )     == 0U)  {    /* ========== Reset ADC registers ========== */    /* Reset register IER */    CLEAR_BIT(ADCx->IER,              (  LL_ADC_IT_ADRDY               | LL_ADC_IT_EOC               | LL_ADC_IT_EOS               | LL_ADC_IT_OVR               | LL_ADC_IT_EOSMP               | LL_ADC_IT_AWD1 )             );        /* Reset register ISR */    SET_BIT(ADCx->ISR,            (  LL_ADC_FLAG_ADRDY             | LL_ADC_FLAG_EOC             | LL_ADC_FLAG_EOS             | LL_ADC_FLAG_OVR             | LL_ADC_FLAG_EOSMP             | LL_ADC_FLAG_AWD1 )           );        /* Reset register CR */    /* Bits ADC_CR_ADCAL, ADC_CR_ADSTP, ADC_CR_ADSTART are in access mode     */    /* "read-set": no direct reset applicable.                                */    /* No action on register CR */    //.........这里部分代码省略.........

/**  * @brief  Run the self calibration of the 3 OPAMPs in parallel.  * @note   Trimming values (PMOS & NMOS) are updated and user trimming is   *         enabled is calibration is succesful.  * @note   Calibration is performed in the mode specified in OPAMP init  *         structure (mode normal or low-power). To perform calibration for  *         both modes, repeat this function twice after OPAMP init structure  *         accordingly updated.  * @note   Calibration runs about 10 ms (5 dichotmy steps, repeated for P    *         and N transistors: 10 steps with 1 ms for each step).  * @param  hopamp1 handle  * @param  hopamp2 handle  * @param  hopamp3 handle  * @retval HAL status  */HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPAMP_HandleTypeDef *hopamp2, OPAMP_HandleTypeDef *hopamp3){  HAL_StatusTypeDef status = HAL_OK;    uint32_t* opamp1_trimmingvalue = 0;  uint32_t opamp1_trimmingvaluen = 0;  uint32_t opamp1_trimmingvaluep = 0;    uint32_t* opamp2_trimmingvalue = 0;  uint32_t opamp2_trimmingvaluen = 0;  uint32_t opamp2_trimmingvaluep = 0;    uint32_t* opamp3_trimmingvalue = 0;  uint32_t opamp3_trimmingvaluen = 0;  uint32_t opamp3_trimmingvaluep = 0;    uint32_t trimming_diff_pair = 0;          /* Selection of differential transistors pair high or low */  __IO uint32_t* tmp_opamp1_reg_trimming;   /* Selection of register of trimming depending on power mode: OTR or LPOTR */  __IO uint32_t* tmp_opamp2_reg_trimming;  __IO uint32_t* tmp_opamp3_reg_trimming;  uint32_t tmp_opamp1_otr_otuser = 0;       /* Selection of bit OPAMP_OTR_OT_USER depending on trimming register pointed: OTR or LPOTR */  uint32_t tmp_opamp2_otr_otuser = 0;  uint32_t tmp_opamp3_otr_otuser = 0;    uint32_t tmp_Opa1calout_DefaultSate = 0;  /* Bit OPAMP_CSR_OPA1CALOUT default state when trimming value is 00000b. Used to detect the bit toggling */  uint32_t tmp_Opa2calout_DefaultSate = 0;  /* Bit OPAMP_CSR_OPA2CALOUT default state when trimming value is 00000b. Used to detect the bit toggling */  uint32_t tmp_Opa3calout_DefaultSate = 0;  /* Bit OPAMP_CSR_OPA3CALOUT default state when trimming value is 00000b. Used to detect the bit toggling */  uint32_t tmp_OpaxSwitchesContextBackup = 0;    uint8_t trimming_diff_pair_iteration_count = 0;       /* For calibration loop algorithm: to repeat the calibration loop for both differential transistors pair high and low */  uint8_t delta = 0;                                    /* For calibration loop algorithm: Variable for dichotomy steps value */  uint8_t final_step_check = 0;                         /* For calibration loop algorithm: Flag for additional check of last trimming step */    /* Check the OPAMP handle allocation */  /* Check if OPAMP locked */  if((hopamp1 == NULL) || (hopamp1->State == HAL_OPAMP_STATE_BUSYLOCKED) ||     (hopamp2 == NULL) || (hopamp2->State == HAL_OPAMP_STATE_BUSYLOCKED) ||     (hopamp3 == NULL) || (hopamp3->State == HAL_OPAMP_STATE_BUSYLOCKED)   )   {    status = HAL_ERROR;  }  else  {      /* Check if OPAMP in calibration mode and calibration not yet enable */    if((hopamp1->State == HAL_OPAMP_STATE_READY) &&       (hopamp2->State == HAL_OPAMP_STATE_READY) &&       (hopamp3->State == HAL_OPAMP_STATE_READY)   )    {      /* Check the parameter */      assert_param(IS_OPAMP_ALL_INSTANCE(hopamp1->Instance));      assert_param(IS_OPAMP_ALL_INSTANCE(hopamp2->Instance));      assert_param(IS_OPAMP_ALL_INSTANCE(hopamp3->Instance));      assert_param(IS_OPAMP_POWERMODE(hopamp1->Init.PowerMode));      assert_param(IS_OPAMP_POWERMODE(hopamp2->Init.PowerMode));      assert_param(IS_OPAMP_POWERMODE(hopamp3->Init.PowerMode));            /* Update OPAMP state */      hopamp1->State = HAL_OPAMP_STATE_CALIBBUSY;      hopamp2->State = HAL_OPAMP_STATE_CALIBBUSY;      hopamp3->State = HAL_OPAMP_STATE_CALIBBUSY;            /* Backup of switches configuration to restore it at the end of the     */      /* calibration.                                                         */      tmp_OpaxSwitchesContextBackup = READ_BIT(OPAMP->CSR, OPAMP_CSR_ALL_SWITCHES_ALL_OPAMPS);            /* Open all switches on non-inverting input, inverting input and output */      /* feedback.                                                            */      CLEAR_BIT(OPAMP->CSR, OPAMP_CSR_ALL_SWITCHES_ALL_OPAMPS);            /* Set calibration mode to user programmed trimming values */      SET_BIT(OPAMP->OTR, OPAMP_OTR_OT_USER);            /* Select trimming settings depending on power mode */      if (hopamp1->Init.PowerMode == OPAMP_POWERMODE_NORMAL)      {        tmp_opamp1_otr_otuser = OPAMP_OTR_OT_USER;        tmp_opamp1_reg_trimming = &OPAMP->OTR;      }      else      {        tmp_opamp1_otr_otuser = 0x00000000;        tmp_opamp1_reg_trimming = &OPAMP->LPOTR;//.........这里部分代码省略.........

/**  * @brief  Initializes the OPAMP according to the specified  *         parameters in the OPAMP_InitTypeDef and initialize the associated handle.  * @note   If the selected opamp is locked, initialization can't be performed.  *         To unlock the configuration, perform a system reset.  * @param  hopamp: OPAMP handle  * @retval HAL status  */HAL_StatusTypeDef HAL_OPAMP_Init(OPAMP_HandleTypeDef *hopamp){   HAL_StatusTypeDef status = HAL_OK;  uint32_t updateotrlpotr = 0;  /* Check the OPAMP handle allocation and lock status */  /* Init not allowed if calibration is ongoing */  if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED)                      || (hopamp->State == HAL_OPAMP_STATE_CALIBBUSY))  {    return HAL_ERROR;  }  else  {    /* Check the parameter */    assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));           /* Set OPAMP parameters */    assert_param(IS_OPAMP_POWER_SUPPLY_RANGE(hopamp->Init.PowerSupplyRange));    assert_param(IS_OPAMP_POWERMODE(hopamp->Init.PowerMode));    assert_param(IS_OPAMP_FUNCTIONAL_NORMALMODE(hopamp->Init.Mode));    assert_param(IS_OPAMP_NONINVERTING_INPUT(hopamp->Init.NonInvertingInput));        if ((hopamp->Init.Mode) == OPAMP_STANDALONE_MODE)    {      assert_param(IS_OPAMP_INVERTING_INPUT_STANDALONE(hopamp->Init.InvertingInput));    }    if ((hopamp->Init.Mode) == OPAMP_PGA_MODE)          {      assert_param(IS_OPAMP_INVERTING_INPUT_PGA(hopamp->Init.InvertingInput));    }        if ((hopamp->Init.Mode) == OPAMP_PGA_MODE)    {      assert_param(IS_OPAMP_PGA_GAIN(hopamp->Init.PgaGain));    }        assert_param(IS_OPAMP_TRIMMING(hopamp->Init.UserTrimming));     if ((hopamp->Init.UserTrimming) == OPAMP_TRIMMING_USER)    {      if (hopamp->Init.PowerMode == OPAMP_POWERMODE_NORMAL)      {        assert_param(IS_OPAMP_TRIMMINGVALUE(hopamp->Init.TrimmingValueP));        assert_param(IS_OPAMP_TRIMMINGVALUE(hopamp->Init.TrimmingValueN));      }    else      {        assert_param(IS_OPAMP_TRIMMINGVALUE(hopamp->Init.TrimmingValuePLowPower));        assert_param(IS_OPAMP_TRIMMINGVALUE(hopamp->Init.TrimmingValueNLowPower));      }    }         if(hopamp->State == HAL_OPAMP_STATE_RESET)    {      /* Allocate lock resource and initialize it */      hopamp->Lock = HAL_UNLOCKED;    }    /* Call MSP init function */    HAL_OPAMP_MspInit(hopamp);    /* Set operating mode */    CLEAR_BIT(hopamp->Instance->CSR, OPAMP_CSR_CALON);                                                  if (hopamp->Init.Mode == OPAMP_PGA_MODE)    {      MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_INIT_MASK_PGA, /                                        hopamp->Init.PowerMode | /                                        hopamp->Init.Mode | /                                        hopamp->Init.PgaGain | /                                        hopamp->Init.InvertingInput    | /                                        hopamp->Init.NonInvertingInput | /                                        hopamp->Init.UserTrimming);    }        if (hopamp->Init.Mode == OPAMP_FOLLOWER_MODE)    {    /* In Follower mode InvertingInput is Not Applicable  */    MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_INIT_MASK_FOLLOWER, /                                        hopamp->Init.PowerMode | /                                        hopamp->Init.Mode | /                                        hopamp->Init.NonInvertingInput | /                                        hopamp->Init.UserTrimming);         }             if (hopamp->Init.Mode == OPAMP_STANDALONE_MODE)    {      MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_INIT_MASK_STANDALONE, /                                        hopamp->Init.PowerMode | /                                        hopamp->Init.Mode | /                                        hopamp->Init.InvertingInput    | ///.........这里部分代码省略.........

/**  * @brief Enable FIREWALL.   * @note Firewall is enabled in clearing FWDIS bit of SYSCFG CFGR1 register.  *       Once enabled, the Firewall cannot be disabled by software. Only a   *       system reset can set again FWDIS bit.             * @retval None  */void HAL_FIREWALL_EnableFirewall(void){  /* Clears FWDIS bit of SYSCFG CFGR1 register */  CLEAR_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_FWDISEN);  }

void SSE::remove(docid_t docName, double& duration){//	docName = "/Users/naveed/BStore/datasets/testdir/" + docName + ".";	double diskTime = 0;	clock_t startTime = clock();	uint64_t docHash = getDocNameHash(boost::lexical_cast<string>(docName));	uint64_t docID0 = docHash;	CLEAR_BIT(docID0, 0);	uint64_t docID1 = docHash;	SET_BIT(docID1, 0);	duration += (double)(clock()-startTime)/(double)CLOCKS_PER_SEC;	OnlineSession session;	session.resetDiskAccessTime();	clock_t ignoredStartTime = clock();	if(fstore.isFilePresent(boost::lexical_cast<string>(docID0))){		fstore.remove(boost::lexical_cast<string>(docID0));//		duration -= (double)(clock()-ignoredStartTime)/(double)CLOCKS_PER_SEC;		/* Entries from Index will be delete using lazy delete*/	}	else if (fstore.isFilePresent(boost::lexical_cast<string>(docID1))){//	else if (fstore.isFilePresent(boost::lexical_cast<string>(docID))){		byte* doc;		double SKETime = 0;//		size_t size = fstore.get("/Users/naveed/BStore/datasets/test4MB/allen-p/straw/8.", doc, SKETime);		size_t size = fstore.get(boost::lexical_cast<string>(docID1), doc, SKETime);		cout << "SKE took " << SKETime << " seconds." << endl;		unordered_set<string, stringhash> keywords;		getKeywords(doc, size, keywords);		duration -= (double)(clock()-ignoredStartTime)/(double)CLOCKS_PER_SEC;				for(unordered_set<string, stringhash>::iterator it = keywords.begin(); it != keywords.end(); ++it){			string keyword = boost::lexical_cast<string>(1) + *it;			OnlineSession session;			byte* docIDs = NULL;			size_t size = session.updateRead(keyword, docIDs, -sizeof(docid_t), diskTime);//			cout << "Updating keyword " << keyword << endl;//			cout << "Number of files containing keyword /"" << keyword << "/" are " << size << endl << " " << size - sizeof(docid_t) << endl;//			uint32_t docIDtoRemove = findDocID(docIDs, size, docID1);			uint32_t docIDtoRemove = findDocID(docIDs, size, docName);			if(docIDtoRemove == -1){				std::cerr << "File present in filestore but is not present in BStore." << endl;				std::cerr << "This is probably due to the files stored from previoius runs. Try again after deleting files from previous runs." << endl;				exit(1);			}			deleteDocID(docIDs, size, docIDtoRemove);//			cout << "DocID to remove " << docIDtoRemove << endl;			session.updateWrite(keyword, docIDs, size, diskTime);			delete[] docIDs;			docIDs = NULL;		}			delete[] doc;		duration += (double)(clock()-startTime)/(double)CLOCKS_PER_SEC - diskTime;		cout << "Disk operations took " << session.getDiskAccessTime() << " seconds." << endl;		fstore.remove(boost::lexical_cast<string>(docID1));	}	else{		cout << "File not found!" << endl;	}	// TODO: delete docNameHash(document) from DocumentStore}

/**  * @brief  De-initialize the DMA registers to their default reset values.  * @param  DMAx DMAx Instance  * @param  Channel This parameter can be one of the following values:  *         @arg @ref LL_DMA_CHANNEL_1  *         @arg @ref LL_DMA_CHANNEL_2  *         @arg @ref LL_DMA_CHANNEL_3  *         @arg @ref LL_DMA_CHANNEL_4  *         @arg @ref LL_DMA_CHANNEL_5  *         @arg @ref LL_DMA_CHANNEL_6  *         @arg @ref LL_DMA_CHANNEL_7  *         @arg @ref LL_DMA_CHANNEL_ALL  * @retval An ErrorStatus enumeration value:  *          - SUCCESS: DMA registers are de-initialized  *          - ERROR: DMA registers are not de-initialized  */uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel){  DMA_Channel_TypeDef *tmp = (DMA_Channel_TypeDef *)DMA1_Channel1;  ErrorStatus status = SUCCESS;  /* Check the DMA Instance DMAx and Channel parameters*/  assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel) || (Channel == LL_DMA_CHANNEL_ALL));  if (Channel == LL_DMA_CHANNEL_ALL)  {    if (DMAx == DMA1)    {      /* Force reset of DMA clock */      LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA1);      /* Release reset of DMA clock */      LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA1);    }#if defined(DMA2)    else if (DMAx == DMA2)    {      /* Force reset of DMA clock */      LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA2);      /* Release reset of DMA clock */      LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA2);    }#endif    else    {      status = ERROR;    }  }  else  {    tmp = (DMA_Channel_TypeDef *)(__LL_DMA_GET_CHANNEL_INSTANCE(DMAx, Channel));    /* Disable the selected DMAx_Channely */    CLEAR_BIT(tmp->CCR, DMA_CCR_EN);    /* Reset DMAx_Channely control register */    LL_DMA_WriteReg(tmp, CCR, 0U);    /* Reset DMAx_Channely remaining bytes register */    LL_DMA_WriteReg(tmp, CNDTR, 0U);    /* Reset DMAx_Channely peripheral address register */    LL_DMA_WriteReg(tmp, CPAR, 0U);    /* Reset DMAx_Channely memory address register */    LL_DMA_WriteReg(tmp, CMAR, 0U);    /* Reset Request register field for DMAx Channel */    LL_DMA_SetPeriphRequest(DMAx, Channel, LL_DMA_REQUEST_0);    if (Channel == LL_DMA_CHANNEL_1)    {      /* Reset interrupt pending bits for DMAx Channel1 */      LL_DMA_ClearFlag_GI1(DMAx);    }    else if (Channel == LL_DMA_CHANNEL_2)    {      /* Reset interrupt pending bits for DMAx Channel2 */      LL_DMA_ClearFlag_GI2(DMAx);    }    else if (Channel == LL_DMA_CHANNEL_3)    {      /* Reset interrupt pending bits for DMAx Channel3 */      LL_DMA_ClearFlag_GI3(DMAx);    }    else if (Channel == LL_DMA_CHANNEL_4)    {      /* Reset interrupt pending bits for DMAx Channel4 */      LL_DMA_ClearFlag_GI4(DMAx);    }    else if (Channel == LL_DMA_CHANNEL_5)    {      /* Reset interrupt pending bits for DMAx Channel5 */      LL_DMA_ClearFlag_GI5(DMAx);    }    else if (Channel == LL_DMA_CHANNEL_6)    {      /* Reset interrupt pending bits for DMAx Channel6 *///.........这里部分代码省略.........

/* Register an event handler and unmask the port */void register_event(evtchn_port_t port, evtchn_handler_t handler){	handlers[port] = handler;	CLEAR_BIT(shared_info.evtchn_mask, port);}

/**  * @brief  Disables the Clock Security System.  * @retval None  */void HAL_RCC_DisableCSS(void){  CLEAR_BIT(RCC->CR, RCC_CR_CSSON);}

/**  * @brief  Initializes the SmartCard mode according to the specified  *         parameters in the SMARTCARD_HandleTypeDef and create the associated handle.  * @param  hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains  *              the configuration information for the specified SMARTCARD module.  * @retval HAL status  */HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsc){  /* Check the SMARTCARD handle allocation */  if(hsc == NULL)  {    return HAL_ERROR;  }  /* Check Wordlength, Parity and Stop bits parameters */  if (  (!(IS_SMARTCARD_WORD_LENGTH(hsc->Init.WordLength)))      ||(!(IS_SMARTCARD_STOPBITS(hsc->Init.StopBits)))      ||(!(IS_SMARTCARD_PARITY(hsc->Init.Parity)))  )  {    return HAL_ERROR;  }  /* Check the parameters */  assert_param(IS_SMARTCARD_INSTANCE(hsc->Instance));  assert_param(IS_SMARTCARD_NACK_STATE(hsc->Init.NACKState));  assert_param(IS_SMARTCARD_PRESCALER(hsc->Init.Prescaler));  if(hsc->State == HAL_SMARTCARD_STATE_RESET)  {      /* Allocate lock resource and initialize it */    hsc->Lock = HAL_UNLOCKED;        /* Init the low level hardware */    HAL_SMARTCARD_MspInit(hsc);  }    hsc->State = HAL_SMARTCARD_STATE_BUSY;  /* Disable the Peripheral */  __HAL_SMARTCARD_DISABLE(hsc);    /* Set the Prescaler */  MODIFY_REG(hsc->Instance->GTPR, USART_GTPR_PSC, hsc->Init.Prescaler);  /* Set the Guard Time */  MODIFY_REG(hsc->Instance->GTPR, USART_GTPR_GT, ((hsc->Init.GuardTime)<<8));  /* Set the Smartcard Communication parameters */  SMARTCARD_SetConfig(hsc);  /* In SmartCard mode, the following bits must be kept cleared:   - LINEN bit in the USART_CR2 register  - HDSEL and IREN bits in the USART_CR3 register.*/  CLEAR_BIT(hsc->Instance->CR2, USART_CR2_LINEN);  CLEAR_BIT(hsc->Instance->CR3, (USART_CR3_IREN | USART_CR3_HDSEL));  /* Enable the Peripharal */  __HAL_SMARTCARD_ENABLE(hsc);  /* Configure the Smartcard NACK state */  MODIFY_REG(hsc->Instance->CR3, USART_CR3_NACK, hsc->Init.NACKState);  /* Enable the SC mode by setting the SCEN bit in the CR3 register */  SET_BIT(hsc->Instance->CR3, USART_CR3_SCEN);  /* Initialize the SMARTCARD state*/  hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;  hsc->State= HAL_SMARTCARD_STATE_READY;  return HAL_OK;}

//.........这里部分代码省略.........    if(pFlash.ProcedureOnGoing == FLASH_PROC_SECTERASE)    {      /*return the faulty sector*/      addresstmp = pFlash.Sector;      pFlash.Sector = 0xFFFFFFFF;    }    else if(pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE)    {      /*return the faulty bank*/      addresstmp = pFlash.Bank;    }    else    {      /*return the faulty address*/      addresstmp = pFlash.Address;    }        /*Save the Error code*/    FLASH_SetErrorCode();        /* FLASH error interrupt user callback */    HAL_FLASH_OperationErrorCallback(addresstmp);        /*Stop the procedure ongoing*/    pFlash.ProcedureOnGoing = FLASH_PROC_NONE;  }    /* Check FLASH End of Operation flag  */  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP) != RESET)  {    /* Clear FLASH End of Operation pending bit */    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);        if(pFlash.ProcedureOnGoing == FLASH_PROC_SECTERASE)    {      /*Nb of sector to erased can be decreased*/      pFlash.NbSectorsToErase--;            /* Check if there are still sectors to erase*/      if(pFlash.NbSectorsToErase != 0)      {        addresstmp = pFlash.Sector;        /*Indicate user which sector has been erased*/        HAL_FLASH_EndOfOperationCallback(addresstmp);                /*Increment sector number*/        pFlash.Sector++;        addresstmp = pFlash.Sector;        FLASH_Erase_Sector(addresstmp, pFlash.VoltageForErase);      }      else      {        /*No more sectors to Erase, user callback can be called.*/        /*Reset Sector and stop Erase sectors procedure*/        pFlash.Sector = addresstmp = 0xFFFFFFFF;        pFlash.ProcedureOnGoing = FLASH_PROC_NONE;                /* Flush the caches to be sure of the data consistency */        FLASH_FlushCaches() ;                        /* FLASH EOP interrupt user callback */        HAL_FLASH_EndOfOperationCallback(addresstmp);      }    }    else     {      if(pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE)       {        /* MassErase ended. Return the selected bank */        /* Flush the caches to be sure of the data consistency */        FLASH_FlushCaches() ;        /* FLASH EOP interrupt user callback */        HAL_FLASH_EndOfOperationCallback(pFlash.Bank);      }      else      {        /*Program ended. Return the selected address*/        /* FLASH EOP interrupt user callback */        HAL_FLASH_EndOfOperationCallback(pFlash.Address);      }      pFlash.ProcedureOnGoing = FLASH_PROC_NONE;    }  }    if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE)  {    /* Operation is completed, disable the PG, SER, SNB and MER Bits */    CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_SER | FLASH_CR_SNB | FLASH_MER_BIT));    /* Disable End of FLASH Operation interrupt */    __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP);        /* Disable Error source interrupt */    __HAL_FLASH_DISABLE_IT(FLASH_IT_ERR);        /* Process Unlocked */    __HAL_UNLOCK(&pFlash);  }}

/**  * @brief Disable SRAM2 content retention in Standby mode.  * @note  When RRS bit is reset, SRAM2 is powered off in Standby mode   *        and its content is lost.        * @retval None  */void HAL_PWREx_DisableSRAM2ContentRetention(void){  CLEAR_BIT(PWR->CR3, PWR_CR3_RRS);}

//.........这里部分代码省略.........        MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep2<<OPAMP_INPUT_NONINVERTING);                       /* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */         /* Offset trim time: during calibration, minimum time needed between */        /* two steps to have 1 mV accuracy */        HAL_Delay(2U);        if (hopamp1->Instance->CSR & OPAMP_CSR_OUTCAL)         {           /* OPAMP_CSR_OUTCAL is HIGH try higher trimming */          trimmingvaluep1 += delta;        }        else        {          trimmingvaluep1 -= delta;        }                 if (hopamp2->Instance->CSR & OPAMP_CSR_OUTCAL)         {           /* OPAMP_CSR_OUTCAL is HIGH try higher trimming */          trimmingvaluep2 += delta;        }        else        {          trimmingvaluep2 -= delta;        }                              delta >>= 1U;      }            // Still need to check if righ calibration is current value or un step below      // Indeed the first value that causes the OUTCAL bit to change from 1 to 0       /* Set candidate trimming */      MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep1<<OPAMP_INPUT_NONINVERTING);      MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep2<<OPAMP_INPUT_NONINVERTING);       /* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */        /* Offset trim time: during calibration, minimum time needed between */       /* two steps to have 1 mV accuracy */       HAL_Delay(2U);            if (hopamp1->Instance->CSR & OPAMP_CSR_OUTCAL)         {           /* OPAMP_CSR_OUTCAL is actually one value more */          trimmingvaluep1++;          /* Set right trimming */          MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep1<<OPAMP_INPUT_NONINVERTING);        }          if (hopamp2->Instance->CSR & OPAMP_CSR_OUTCAL)         {           /* OPAMP_CSR_OUTCAL is actually one value more */          trimmingvaluep2++;          /* Set right trimming */          MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep2<<OPAMP_INPUT_NONINVERTING);        }      /* Disable calibration */      CLEAR_BIT (hopamp1->Instance->CSR, OPAMP_CSR_CALON);      CLEAR_BIT (hopamp2->Instance->CSR, OPAMP_CSR_CALON);      /* Disable the OPAMPs */      CLEAR_BIT (hopamp1->Instance->CSR, OPAMP_CSR_OPAMPxEN);      CLEAR_BIT (hopamp2->Instance->CSR, OPAMP_CSR_OPAMPxEN);      /* Set operating mode back */      CLEAR_BIT(hopamp1->Instance->CSR, OPAMP_CSR_FORCEVP);      CLEAR_BIT(hopamp2->Instance->CSR, OPAMP_CSR_FORCEVP);            /* Self calibration is successful  */      /* Store calibration(user timming) results in init structure. */      /* Select user timming mode */      /* Write calibration result N */      hopamp1->Init.TrimmingValueN = trimmingvaluen1;      hopamp2->Init.TrimmingValueN = trimmingvaluen2;           /* Write calibration result P */      hopamp1->Init.TrimmingValueP = trimmingvaluep1;      hopamp2->Init.TrimmingValueP = trimmingvaluep2;                  /* Calibration */      hopamp1->Init.UserTrimming = OPAMP_TRIMMING_USER;      hopamp2->Init.UserTrimming = OPAMP_TRIMMING_USER;          /* Select user timming mode */            /* And updated with calibrated settings */      hopamp1->Init.UserTrimming = OPAMP_TRIMMING_USER;      hopamp2->Init.UserTrimming = OPAMP_TRIMMING_USER;            MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen1<<OPAMP_INPUT_INVERTING);      MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen2<<OPAMP_INPUT_INVERTING);           MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep1<<OPAMP_INPUT_NONINVERTING);      MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep2<<OPAMP_INPUT_NONINVERTING);                    }        else    {

/**  * @brief Disable the Power Voltage Monitoring 4:  VDDA versus 2.2V.  * @retval None  */void HAL_PWREx_DisablePVM4(void){  CLEAR_BIT(PWR->CR2, PWR_PVM_4);    }

//.........这里部分代码省略.........      /* SHSR1 can be written when BWST1  equals RESET */      while (((hdac->Instance->SR) & DAC_SR_BWST1)!= RESET)      {        /* Check for the Timeout */        if((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG)        {          /* Update error code */          SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT);          /* Change the DMA state */          hdac->State = HAL_DAC_STATE_TIMEOUT;          return HAL_TIMEOUT;        }      }      HAL_Delay(1);      hdac->Instance->SHSR1 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime;    }    else /* Channel 2 */    {      /* SHSR2 can be written when BWST2 equals RESET */      while (((hdac->Instance->SR) & DAC_SR_BWST2)!= RESET)      {        /* Check for the Timeout */        if((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG)        {          /* Update error code */          SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT);          /* Change the DMA state */          hdac->State = HAL_DAC_STATE_TIMEOUT;          return HAL_TIMEOUT;        }      }      HAL_Delay(1);      hdac->Instance->SHSR2 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime;    }    /* HoldTime */    hdac->Instance->SHHR = (sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime)<<Channel;    /* RefreshTime */    hdac->Instance->SHRR = (sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime)<<Channel;  }      if(sConfig->DAC_UserTrimming == DAC_TRIMMING_USER)  /* USER TRIMMING */  {  /* Get the DAC CCR value */  tmpreg1 = hdac->Instance->CCR;  /* Clear trimming value */  tmpreg1 &= ~(((uint32_t)(DAC_CCR_OTRIM1)) << Channel);  /* Configure for the selected trimming offset */  tmpreg2 = sConfig->DAC_TrimmingValue;  /* Calculate CCR register value depending on DAC_Channel */  tmpreg1 |= tmpreg2 << Channel;  /* Write to DAC CCR */  hdac->Instance->CCR = tmpreg1;  }  /* else factory trimming is used (factory setting are available at reset)*/  /* SW Nothing has nothing to do */    /* Get the DAC MCR value */  tmpreg1 = hdac->Instance->MCR;  /* Clear DAC_MCR_MODE2_0, DAC_MCR_MODE2_1 and DAC_MCR_MODE2_2 bits */  tmpreg1 &= ~(((uint32_t)(DAC_MCR_MODE1)) << Channel);   /* Configure for the selected DAC channel: mode, buffer output & on chip peripheral connect */  tmpreg2 = (sConfig->DAC_SampleAndHold | sConfig->DAC_OutputBuffer | sConfig->DAC_ConnectOnChipPeripheral);  /* Calculate MCR register value depending on DAC_Channel */  tmpreg1 |= tmpreg2 << Channel;  /* Write to DAC MCR */  hdac->Instance->MCR = tmpreg1;    /* DAC in normal operating mode hence clear DAC_CR_CENx bit */  CLEAR_BIT (hdac->Instance->CR, DAC_CR_CEN1 << Channel);    /* Get the DAC CR value */  tmpreg1 = hdac->Instance->CR;  /* Clear TENx, TSELx, WAVEx and MAMPx bits */  tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1)) << Channel);   /* Configure for the selected DAC channel: trigger */  /* Set TSELx and TENx bits according to DAC_Trigger value */  tmpreg2 = (sConfig->DAC_Trigger);  /* Calculate CR register value depending on DAC_Channel */  tmpreg1 |= tmpreg2 << Channel;  /* Write to DAC CR */  hdac->Instance->CR = tmpreg1;        /* Disable wave generation */  hdac->Instance->CR &= ~(DAC_CR_WAVE1 << Channel);    /* Change DAC state */  hdac->State = HAL_DAC_STATE_READY;    /* Process unlocked */  __HAL_UNLOCK(hdac);    /* Return function status */  return HAL_OK;}

HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef *hopamp){   HAL_StatusTypeDef status = HAL_OK;    uint32_t trimmingvaluen = 0;  uint32_t trimmingvaluep = 0;  uint32_t delta;  uint32_t opampmode;    __IO uint32_t* tmp_opamp_reg_trimming;   /* Selection of register of trimming depending on power mode: OTR or LPOTR */      /* Check the OPAMP handle allocation */  /* Check if OPAMP locked */  if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED))  {    status = HAL_ERROR;  }  else  {    /* Check if OPAMP in calibration mode and calibration not yet enable */    if(hopamp->State ==  HAL_OPAMP_STATE_READY)    {      /* Check the parameter */      assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));      assert_param(IS_OPAMP_POWERMODE(hopamp->Init.PowerMode));      /* Save OPAMP mode as in                                       */      /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx */      /* the calibration is not working in PGA mode                  */      opampmode = READ_BIT(hopamp->Instance->CSR,OPAMP_CSR_OPAMODE);            /* Use of standalone mode */       MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_OPAMODE, OPAMP_STANDALONE_MODE);       /*  user trimming values are used for offset calibration */      SET_BIT(hopamp->Instance->CSR, OPAMP_CSR_USERTRIM);            /* Select trimming settings depending on power mode */      if (hopamp->Init.PowerMode == OPAMP_POWERMODE_NORMAL)      {        tmp_opamp_reg_trimming = &hopamp->Instance->OTR;      }      else      {        tmp_opamp_reg_trimming = &hopamp->Instance->LPOTR;      }            /* Enable calibration */      SET_BIT (hopamp->Instance->CSR, OPAMP_CSR_CALON);        /* 1st calibration - N */      CLEAR_BIT (hopamp->Instance->CSR, OPAMP_CSR_CALSEL);            /* Enable the selected opamp */      SET_BIT (hopamp->Instance->CSR, OPAMP_CSR_OPAMPxEN);            /* Init trimming counter */          /* Medium value */      trimmingvaluen = 16;       delta = 8;                 while (delta != 0)      {        /* Set candidate trimming */        /* OPAMP_POWERMODE_NORMAL */        MODIFY_REG(*tmp_opamp_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen);                /* OFFTRIMmax delay 1 ms as per datasheet (electrical characteristics */         /* Offset trim time: during calibration, minimum time needed between */        /* two steps to have 1 mV accuracy */        HAL_Delay(OPAMP_TRIMMING_DELAY);        if (READ_BIT(hopamp->Instance->CSR, OPAMP_CSR_CALOUT) != RESET)        {           /* OPAMP_CSR_CALOUT is HIGH try higher trimming */          trimmingvaluen -= delta;        }        else        {          /* OPAMP_CSR_CALOUT is LOW try lower trimming */          trimmingvaluen += delta;        }        /* Divide range by 2 to continue dichotomy sweep */               delta >>= 1;      }      /* Still need to check if right calibration is current value or one step below */      /* Indeed the first value that causes the OUTCAL bit to change from 0 to 1  */      /* Set candidate trimming */      MODIFY_REG(*tmp_opamp_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen);                 /* OFFTRIMmax delay 1 ms as per datasheet (electrical characteristics */       /* Offset trim time: during calibration, minimum time needed between */      /* two steps to have 1 mV accuracy */      HAL_Delay(OPAMP_TRIMMING_DELAY);            if ((READ_BIT(hopamp->Instance->CSR, OPAMP_CSR_CALOUT)) == 0)      {         /* Trimming value is actually one value more *///.........这里部分代码省略.........

/**  * @brief Disable battery charging.    * @retval None  */void HAL_PWREx_DisableBatteryCharging(void){  CLEAR_BIT(PWR->CR4, PWR_CR4_VBE); }  

/**  * @brief Disable FIREWALL pre arm.  * @note When FPA bit is reset, any code executed outside the protected segment   *       when the Firewall is opened will generate a system reset.  * @note This API provides the same service as __HAL_FIREWALL_PREARM_DISABLE() macro  *       but can't be executed inside a code area protected by the Firewall.  * @note When the Firewall is disabled, user can resort to HAL_FIREWALL_EnablePreArmFlag() API any time.     * @note When the Firewall is enabled and NVDSL register is equal to 0 (that is,   *          when the non volatile data segment is not defined),  *          **  this API can be executed when the Firewall is closed  *          **  when the Firewall is opened, user should resort to   *              __HAL_FIREWALL_PREARM_DISABLE() macro instead  * @note When the Firewall is enabled and  NVDSL register is different from 0  *          (that is, when the non volatile data segment is defined)  *          **  FW_CR register can be accessed only when the Firewall is opened:   *              user should resort to  __HAL_FIREWALL_PREARM_DISABLE() macro instead.                           * @retval None  */void HAL_FIREWALL_DisablePreArmFlag(void){  /* Clear FPA bit */  CLEAR_BIT(FIREWALL->CR, FW_CR_FPA);}

/**  * @brief Disable VDDUSB supply.   * @retval None  */void HAL_PWREx_DisableVddUSB(void){  CLEAR_BIT(PWR->CR2, PWR_CR2_USV);}

int CreateOverlaySurface(volatile STG4000REG * pSTGReg,			 u32 inWidth,			 u32 inHeight,			 int bLinear,			 u32 ulOverlayOffset,			 u32 * retStride, u32 * retUVStride){	u32 tmp;	u32 ulStride;	if (inWidth > STG4000_OVRL_MAX_WIDTH ||	    inHeight > STG4000_OVRL_MAX_HEIGHT) {		return -EINVAL;	}	/* Stride in 16 byte words - 16Bpp */	if (bLinear) {		/* Format is 16bits so num 16 byte words is width/8 */		if ((inWidth & 0x7) == 0) {	/* inWidth % 8 */			ulStride = (inWidth / 8);		} else {			/* Round up to next 16byte boundary */			ulStride = ((inWidth + 8) / 8);		}	} else {		/* Y component is 8bits so num 16 byte words is width/16 */		if ((inWidth & 0xf) == 0) {	/* inWidth % 16 */			ulStride = (inWidth / 16);		} else {			/* Round up to next 16byte boundary */			ulStride = ((inWidth + 16) / 16);		}	}	/* Set Overlay address and Format mode */	tmp = STG_READ_REG(DACOverlayAddr);	CLEAR_BITS_FRM_TO(0, 20);	if (bLinear) {		CLEAR_BIT(31);	/* Overlay format to Linear */	} else {		tmp |= SET_BIT(31);	/* Overlay format to Planer */	}	/* Only bits 24:4 of the Overlay address */	tmp |= (ulOverlayOffset >> 4);	STG_WRITE_REG(DACOverlayAddr, tmp);	if (!bLinear) {		u32 uvSize =		    (inWidth & 0x1) ? (inWidth + 1 / 2) : (inWidth / 2);		u32 uvStride;		u32 ulOffset;		/* Y component is 8bits so num 32 byte words is width/32 */		if ((uvSize & 0xf) == 0) {	/* inWidth % 16 */			uvStride = (uvSize / 16);		} else {			/* Round up to next 32byte boundary */			uvStride = ((uvSize + 16) / 16);		}		ulOffset = ulOverlayOffset + (inHeight * (ulStride * 16));		/* Align U,V data to 32byte boundary */		if ((ulOffset & 0x1f) != 0)			ulOffset = (ulOffset + 32L) & 0xffffffE0L;		tmp = STG_READ_REG(DACOverlayUAddr);		CLEAR_BITS_FRM_TO(0, 20);		tmp |= (ulOffset >> 4);		STG_WRITE_REG(DACOverlayUAddr, tmp);		ulOffset += (inHeight / 2) * (uvStride * 16);		/* Align U,V data to 32byte boundary */		if ((ulOffset & 0x1f) != 0)			ulOffset = (ulOffset + 32L) & 0xffffffE0L;		tmp = STG_READ_REG(DACOverlayVAddr);		CLEAR_BITS_FRM_TO(0, 20);		tmp |= (ulOffset >> 4);		STG_WRITE_REG(DACOverlayVAddr, tmp);		*retUVStride = uvStride * 16;	}

/**  * @brief Disable VDDIO2 supply.   * @retval None  */void HAL_PWREx_DisableVddIO2(void){  CLEAR_BIT(PWR->CR2, PWR_CR2_IOSV);}

/**  * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode.   * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor   *       re-enters SLEEP mode when an interruption handling is over.            * @retval None  */void HAL_PWR_DisableSleepOnExit(void){  /* Clear SLEEPONEXIT bit of Cortex System Control Register */  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));}

/**  * @brief Disable Internal Wake-up Line.   * @retval None  */void HAL_PWREx_DisableInternalWakeUpLine(void){  CLEAR_BIT(PWR->CR3, PWR_CR3_EIWF);}

void init_spi()/******************************************************************************   Function : See module specification (.h-file).*****************************************************************************/{	INT8U dummy;			// Pin setup	// Enable port A.	SYSCTL_RCGC2_R |= SYSCTL_RCGC2_GPIOA;	dummy = SYSCTL_RCGC2_R;		// HW control, Set pins in GPIO_PORTA_AFSEL_R	SET_BIT(GPIO_PORTA_AFSEL_R, SSI_CLK);	SET_BIT(GPIO_PORTA_AFSEL_R, SSI_SS);	SET_BIT(GPIO_PORTA_AFSEL_R, SSI_RX);	SET_BIT(GPIO_PORTA_AFSEL_R, SSI_TX);		// Configure PAD: 	2mA drive: set pins in GPIO_PORTA_DR2R_R	SET_BIT(GPIO_PORTA_DR2R_R, SSI_CLK);	SET_BIT(GPIO_PORTA_DR2R_R, SSI_SS);	SET_BIT(GPIO_PORTA_DR2R_R, SSI_RX);	SET_BIT(GPIO_PORTA_DR2R_R, SSI_TX);	//					Clear pins in GPIO_PORTA_ODR_R	CLEAR_BIT(GPIO_PORTA_ODR_R, SSI_CLK);	CLEAR_BIT(GPIO_PORTA_ODR_R, SSI_SS);	CLEAR_BIT(GPIO_PORTA_ODR_R, SSI_RX);	CLEAR_BIT(GPIO_PORTA_ODR_R, SSI_TX);	//					Clear pins in GPIO_PORTA_PUR_R	CLEAR_BIT(GPIO_PORTA_PUR_R, SSI_CLK);	CLEAR_BIT(GPIO_PORTA_PUR_R, SSI_SS);	CLEAR_BIT(GPIO_PORTA_PUR_R, SSI_RX);	CLEAR_BIT(GPIO_PORTA_PUR_R, SSI_TX);	//					Clear pins in GPIO_PORTA_PDR_R	CLEAR_BIT(GPIO_PORTA_PDR_R, SSI_CLK);	CLEAR_BIT(GPIO_PORTA_PDR_R, SSI_SS);	CLEAR_BIT(GPIO_PORTA_PDR_R, SSI_RX);	CLEAR_BIT(GPIO_PORTA_PDR_R, SSI_TX);	//					Set pins in GPIO_PORTA_DEN_R	SET_BIT(GPIO_PORTA_DEN_R, SSI_CLK);	SET_BIT(GPIO_PORTA_DEN_R, SSI_SS);	SET_BIT(GPIO_PORTA_DEN_R, SSI_RX);	SET_BIT(GPIO_PORTA_DEN_R, SSI_TX);		SET_BIT(GPIO_PORTA_DIR_R, SSI_CLK);	SET_BIT(GPIO_PORTA_DIR_R, SSI_SS);	SET_BIT(GPIO_PORTA_DIR_R, SSI_RX);	SET_BIT(GPIO_PORTA_DIR_R, SSI_TX);			// SSI setup		// SYSCTL_RCGC1_R 	== RCGC1	// SSI0_CR1_R 		== SSICR1	// SSI0_CPSR_R 		== SSICPSR	// SSI0_CR0_R		== SSICR0		// Enable SSI Clock	SYSCTL_RCGC1_R = SYSCTL_RCGC1_SSI0;		// 1 Disable SSI		// Clear SSI bit in SSICR1	spi_disable();		// 2 Select master or slave		// For master operations, set the SSICR1 register to 0x0000.0000	SSI0_CR1_R = 0x00000000;		// 3 Configure clock		// 50*10^6/(4*(1+12))		// SysClock * 10^6 / (CPSDVSR * (1 + SCR))		// (50 * (10^6)) / (4 * (1 + 9)) = 1 250 000 bit/sec					// SSICPSR = CPSDVSR = 0x4	SSI0_CPSR_R = 0x4;			// 4 Write to SSICR0:		// SCR: 	[15:8] SSI Serial Clock Rate		// SPH: 	[7] SSI Serial Clock Phase		// SPO:		[6]	SSI Serial Clock Polarity		// FRF:		[5:4] FrameFormat, 0x0 for Freescale		// DSS:		[3:0] Datasize		// SSI0_CR0_R = 0b00000000 0 0 00 0000	SSI0_CR0_R = 0b0000100111001000;				 //0b00000100 1 1 00 1111				// 5 Enable SSI			// Set SSI bit in SSICR1	spi_enable();}

/**  * @brief Disable pull-up and pull-down configuration.  * @note  When APC bit is cleared, the I/O pull-up and pull-down configurations defined in   *        PWR_PUCRx and PWR_PDCRx registers are not applied in Standby and Shutdown modes.       * @retval None  */void HAL_PWREx_DisablePullUpPullDownConfig(void){  CLEAR_BIT(PWR->CR3, PWR_CR3_APC);}

/**  * @brief  Enables ADC DMA request after last transfer (Multi-ADC mode) and enables ADC peripheral  *   * @note   Caution: This function must be used only with the ADC master.    *  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains  *         the configuration information for the specified ADC.  * @param  pData:   Pointer to buffer in which transferred from ADC peripheral to memory will be stored.   * @param  Length:  The length of data to be transferred from ADC peripheral to memory.    * @retval HAL status  */HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length){  __IO uint32_t counter = 0;    /* Check the parameters */  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));  assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));    /* Process locked */  __HAL_LOCK(hadc);    /* Check if ADC peripheral is disabled in order to enable it and wait during      Tstab time the ADC's stabilization */  if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)  {      /* Enable the Peripheral */    __HAL_ADC_ENABLE(hadc);        /* Delay for temperature sensor stabilization time */    /* Compute number of CPU cycles to wait for */    counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));    while(counter != 0)    {      counter--;    }  }    /* Start conversion if ADC is effectively enabled */  if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))  {    /* Set ADC state                                                          */    /* - Clear state bitfield related to regular group conversion results     */    /* - Set state bitfield related to regular group operation                */    ADC_STATE_CLR_SET(hadc->State,                      HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,                      HAL_ADC_STATE_REG_BUSY);        /* If conversions on group regular are also triggering group injected,    */    /* update ADC state.                                                      */    if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)    {      ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);      }        /* State machine update: Check if an injected conversion is ongoing */    if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))    {      /* Reset ADC error code fields related to conversions on group regular */      CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));             }    else    {      /* Reset ADC all error code fields */      ADC_CLEAR_ERRORCODE(hadc);    }        /* Process unlocked */    /* Unlock before starting ADC conversions: in case of potential           */    /* interruption, to let the process to ADC IRQ Handler.                   */    __HAL_UNLOCK(hadc);        /* Set the DMA transfer complete callback */    hadc->DMA_Handle->XferCpltCallback = ADC_MultiModeDMAConvCplt;        /* Set the DMA half transfer complete callback */    hadc->DMA_Handle->XferHalfCpltCallback = ADC_MultiModeDMAHalfConvCplt;        /* Set the DMA error callback */    hadc->DMA_Handle->XferErrorCallback = ADC_MultiModeDMAError ;        /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC     */    /* start (in case of SW start):                                           */        /* Clear regular group conversion flag and overrun flag */    /* (To ensure of no unknown state from potential previous ADC operations) */    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);    /* Enable ADC overrun interrupt */    __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);        if (hadc->Init.DMAContinuousRequests != DISABLE)    {      /* Enable the selected ADC DMA request after last transfer */      ADC->CCR |= ADC_CCR_DDS;    }    else    {      /* Disable the selected ADC EOC rising on each regular channel conversion *///.........这里部分代码省略.........

/**  * @brief  Disable the Debug Module during STOP mode         * @param  None  * @retval None  */void HAL_DisableDBGStopMode(void){  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);}