自学教程：C++ CLEAR_CBUS_REG_MASK函数代码示例

void early_pll_switch(int flag){    int i;    if (flag) {        for (i = EARLY_PLL_COUNT - 1; i >= 0; i--) {            if (early_pll_flag[i]) {                if ((early_plls[i]==HHI_VID_PLL_CNTL)||(early_plls[i]==HHI_VIID_PLL_CNTL)){                    CLEAR_CBUS_REG_MASK(early_plls[i], (1 << 30));                    early_pll_flag[i] = 0;                }                else{                    CLEAR_CBUS_REG_MASK(early_plls[i], (1 << 15));                    early_pll_flag[i] = 0;                }                printf("late pll %s(%x) on/n", early_plls_name[i], early_plls[i]);            }        }        udelay(1000);    } else {        for (i = 0; i < EARLY_PLL_COUNT; i++) {            if ((early_plls[i]==HHI_VID_PLL_CNTL)||(early_plls[i]==HHI_VIID_PLL_CNTL))                early_pll_flag[i] = READ_CBUS_REG_BITS(early_plls[i], 30, 1) ? 0 : 1;            else                early_pll_flag[i] = READ_CBUS_REG_BITS(early_plls[i], 15, 1) ? 0 : 1;            if (early_pll_flag[i]) {                printf("early pll %s(%x) off/n", early_plls_name[i], early_plls[i]);                if ((early_plls[i]==HHI_VID_PLL_CNTL)||(early_plls[i]==HHI_VIID_PLL_CNTL))                    SET_CBUS_REG_MASK(early_plls[i], (1 << 30));                else                    SET_CBUS_REG_MASK(early_plls[i], (1 << 15));            }        }    }}

void power_off_backlight(void){    //BL_PWM -> GPIOD_18: 0#if 0    set_gpio_val(GPIOA_bank_bit(7), GPIOA_bit_bit0_14(7), 0);    set_gpio_mode(GPIOA_bank_bit(7), GPIOA_bit_bit0_14(7), GPIO_OUTPUT_MODE);#else    	set_gpio_val(GPIOD_bank_bit2_24(18), GPIOD_bit_bit2_24(18), 0);	set_gpio_mode(GPIOD_bank_bit2_24(18), GPIOD_bit_bit2_24(18), GPIO_OUTPUT_MODE);	CLEAR_CBUS_REG_MASK(PERIPHS_PIN_MUX_2, (1<<31));	CLEAR_CBUS_REG_MASK(PWM_MISC_REG_AB, (1 << 0));	set_gpio_val(GPIOA_bank_bit(7), GPIOA_bit_bit0_14(7), 0);	set_gpio_mode(GPIOA_bank_bit(7), GPIOA_bit_bit0_14(7), GPIO_OUTPUT_MODE);#endif    printf("test lcd power and backlight off/n");    //test    *((unsigned long*)0xC1108048) &= ~(1<<16);  //GPIOD18 backlight enable    *((unsigned long*)0xC110804c) &= (1<<16);  //GPIOD18 backlight enable    *((unsigned long*)0xC1108030) &= ~(1<<11);  //GPIOA7 backlight pwm    *((unsigned long*)0xC1108034) &= (1<<11);  //GPIOA7 backlight pwm    *((unsigned long*)0xC1108048) &= ~(1<<10);  //GPIOD12 lcd power    *((unsigned long*)0xC110804c) &= ~(1<<10);  //GPIOD12  lcd power    *((unsigned long*)0xC1108048) &= ~(1<<11);  //GPIOD13 lcd vcc    *((unsigned long*)0xC110804c) |= ~(1<<11);  //GPIOD13  lcd vcc}

/*************************************************  * Amlogic Ethernet controller operation  *  * Note: The LAN chip LAN8720 need to be reset  *  *************************************************/static void setup_net_chip(void){	//m8 only use externel clock	/* setup ethernet clk */#ifdef IP101PHY	WRITE_CBUS_REG(HHI_ETH_CLK_CNTL, 0xf00); // clock Input 50 inverted : bit14 =1 Div : 6:0 = 0 En : bit8 = 1  Sel : bit 11:9 = 7#else	WRITE_CBUS_REG(HHI_ETH_CLK_CNTL, 0x4f00); // clock Input 50 inverted : bit14 =1 Div : 6:0 = 0 En : bit8 = 1  Sel : bit 11:9 = 7#endif	/* setup ethernet pinmux use gpioz(5-14) */#ifdef KSZ8091	WRITE_CBUS_REG(HHI_ETH_CLK_CNTL, 0xf00); // clock Input 50 inverted : bit14 =1 Div : 6:0 = 0 En : bit8 = 1  Sel : bit 11:9 = 7	SET_CBUS_REG_MASK(PERIPHS_PIN_MUX_6, (1<<15)|(1 << 14) | (1 << 13) | (1 << 12) |	(1 << 11) | (1 << 8 ) | (1 << 7 ) | (1 << 10 ) | (1 << 6 ) | (1 << 5 ));#else	SET_CBUS_REG_MASK(PERIPHS_PIN_MUX_6, (1 << 14) | (1 << 13) | (1 << 12) |	(1 << 11) | (1 << 8 ) | (1 << 7 ) | (1 << 10 ) | (1 << 6 ) | (1 << 5 ));#endif	/* setup ethernet mode */	WRITE_CBUS_REG(PREG_ETHERNET_ADDR0, 0x241);//bit6-4 :001 rmii mode	CLEAR_CBUS_REG_MASK(HHI_MEM_PD_REG0, (1 << 3) | (1<<2));	/* hardware reset ethernet phy : gpioz14 connect phyreset pin*/	CLEAR_CBUS_REG_MASK(PREG_PAD_GPIO1_EN_N, 1 << 31);	CLEAR_CBUS_REG_MASK(PREG_PAD_GPIO1_O, 1 << 31);	udelay(10000);	SET_CBUS_REG_MASK(PREG_PAD_GPIO1_O, 1 << 31);}

int aml_sd_init(struct mmc *mmc){	//int ret;	struct aml_card_sd_info *sdio=mmc->priv;	//setting io pin mux	//FIXME M2 socket board#ifdef CONFIG_BOARD_M2_SOCKET	CLEAR_CBUS_REG_MASK(PREG_EGPIO_EN_N,(0x1<<8));	CLEAR_CBUS_REG_MASK(PREG_EGPIO_O,(0x1<<8));#endif    if(sdio->inited_flag)    {       	        #ifdef AML_CARD_SD_INFO_DETAILED              sdio->sdio_init(sdio->sdio_port,sdio);        #else        sdio->sdio_init(sdio->sdio_port);        #endif                 if((sdio->sdio_port == SDIO_PORT_B)&&(sdio_debug_1bit_flag)){       		clrbits_le32(P_PERIPHS_PIN_MUX_2,7<<12);   	 	}   	 	       mmc->set_ios(mmc);        return 0;    }        	if (sd_inand_check_insert(mmc)) {		sd_inand_staff_init(mmc);		return 0;	} else		return 1;}

/*************************************************  * Amlogic Ethernet controller operation  *  * Note: The LAN chip LAN8720 need to be reset by GPIOY_15  *  *************************************************/static void setup_net_chip(void){#ifdef CONFIG_NET_RGMII	/* setup ethernet clk */	WRITE_CBUS_REG(HHI_ETH_CLK_CNTL, 0x309);	/* setup ethernet pinmux */	SET_CBUS_REG_MASK(PERIPHS_PIN_MUX_6, 0x4007ffe0);	/* setup ethernet mode */	WRITE_CBUS_REG(PREG_ETHERNET_ADDR0, 0x211);#elif defined(CONFIG_NET_RMII_CLK_EXTERNAL)	/* setup ethernet clk */	WRITE_CBUS_REG(HHI_ETH_CLK_CNTL, 0x130);	/* setup ethernet pinmux */	SET_CBUS_REG_MASK(PERIPHS_PIN_MUX_6, 0x8007ffe0);	/* setup ethernet mode */	WRITE_CBUS_REG(PREG_ETHERNET_ADDR0, 0x241);#else	/* setup ethernet clk */	WRITE_CBUS_REG(HHI_ETH_CLK_CNTL, 0x702);	/* setup ethernet pinmux */	SET_CBUS_REG_MASK(PERIPHS_PIN_MUX_6, 0x4007ffe0);	/* setup ethernet mode */	WRITE_CBUS_REG(PREG_ETHERNET_ADDR0, 0x241);#endif	/* setup ethernet interrupt */	SET_CBUS_REG_MASK(SYS_CPU_0_IRQ_IN0_INTR_MASK, 1 << 8);	SET_CBUS_REG_MASK(SYS_CPU_0_IRQ_IN1_INTR_STAT, 1 << 8);	/* hardware reset ethernet phy */	CLEAR_CBUS_REG_MASK(PREG_PAD_GPIO5_EN_N, 1 << 15);	CLEAR_CBUS_REG_MASK(PREG_PAD_GPIO5_O, 1 << 15);	udelay(2000);	SET_CBUS_REG_MASK(PREG_PAD_GPIO5_O, 1 << 15);}

static void oneshot_event(void){    shot_time = 0;    if(pwmSwitch == 0)    {        //strcat(logbuf, "open/n");        pwmSwitch = 1;        SET_CBUS_REG_MASK(PWM_MISC_REG_AB, ((1<<15)|(0<<8)|(1<<0)));//on    }    else    {        //strcat(logbuf, "close/n");        pwmSwitch = 0;        CLEAR_CBUS_REG_MASK(PWM_MISC_REG_AB, ((1<<15)|(0<<8)|(1<<0)));//off    }        //set next window timer    send_idx++;    if(send_idx < send_win.winNum)    {        //dbg("delay time[%d] and trgger next event/n", send_win.winArray[send_idx]);        set_timer_b_event(send_win.winArray[send_idx]);    }    else //pwm should be off    {        //dbg("off pwm/n");        CLEAR_CBUS_REG_MASK(PWM_MISC_REG_AB, ((1<<15)|(0<<8)|(1<<0)));        pwmSwitch = 0;    }}

// -----------------------------------------// clk_util_clk_msr// -----------------------------------------// from twister_core.v//// .clk0           ( am_ring_osc_clk_out[0]    ),// .clk1           ( am_ring_osc_clk_out[1]    ),// .clk2           ( ext_clk_to_msr_i          ),// .clk3           ( cts_a9_clk                ),// .clk4           ( cts_a9_periph_clk         ),// .clk5           ( cts_a9_axi_clk            ),// .clk6           ( cts_a9_at_clk             ),// .clk7           ( cts_a9_apb_clk            ),// .clk8           ( cts_arc625_clk            ),// .clk9           ( sys_pll_div3              ),// .clk10          ( ddr_pll_clk               ),// .clk11          ( other_pll_clk             ),// .clk12          ( aud_pll_clk               ),// .clk13          ( demod_pll_clk240          ),// .clk14          ( demod_pll_adc_clk         ),// .clk15          ( demod_pll_wifi_adc_clk    ),// .clk16          ( demod_pll_adc_clk_57      ),// .clk17          ( demod_pll_clk400          ),// .clk18          ( demod_pll_wifi_dac_clk    ),// .clk19          ( vid_pll_clk               ),// .clk20          ( vid_pll_ref_clk           ),// .clk21          ( HDMI_CH0_TMDSCLK          ),//// For Example//// unsigend long    clk81_clk   = clk_util_clk_msr( 2,      // mux select 2//                                                  50 );   // measure for 50uS//// returns a value in "clk81_clk" in Hz//// The "uS_gate_time" can be anything between 1uS and 65535 uS, but the limitation is// the circuit will only count 65536 clocks.  Therefore the uS_gate_time is limited by////   uS_gate_time <= 65535/(expect clock frequency in MHz)//// For example, if the expected frequency is 400Mhz, then the uS_gate_time should// be less than 163.//// Your measurement resolution is:////    100% / (uS_gate_time * measure_val )////unsigned int clk_util_clk_msr_rl(unsigned int clk_mux){    unsigned int regval = 0;    WRITE_CBUS_REG(MSR_CLK_REG0, 0);    // Set the measurement gate to 64uS    CLEAR_CBUS_REG_MASK(MSR_CLK_REG0, 0xffff);    SET_CBUS_REG_MASK(MSR_CLK_REG0, (64 - 1)); //64uS is enough for measure the frequence?    // Disable continuous measurement    // disable interrupts    CLEAR_CBUS_REG_MASK(MSR_CLK_REG0, ((1 << 18) | (1 << 17)));    CLEAR_CBUS_REG_MASK(MSR_CLK_REG0, (0x1f << 20));    SET_CBUS_REG_MASK(MSR_CLK_REG0, (clk_mux << 20) | // Select MUX                                    (1 << 19) |       // enable the clock									(1 << 16));       //enable measuring    // Wait for the measurement to be done    regval = READ_CBUS_REG(MSR_CLK_REG0);    do {        regval = READ_CBUS_REG(MSR_CLK_REG0);    } while (regval & (1 << 31));    // disable measuring    CLEAR_CBUS_REG_MASK(MSR_CLK_REG0, (1 << 16));    regval = (READ_CBUS_REG(MSR_CLK_REG2) + 31) & 0x000FFFFF;    // Return value in MHz*measured_val    return (regval >> 6);}

int board_eth_init(bd_t *bis){    /*    @todo implement this function    */            //  	eth_clk_set(ETH_CLKSRC_SYS_D3,900*CLK_1M/3,50*CLK_1M);	//eth_clk_set(ETH_CLKSRC_SYS_D3,get_cpu_clk()*2/3,50*CLK_1M);	eth_clk_set(ETH_CLKSRC_APLL_CLK,400*CLK_1M,50*CLK_1M);	///GPIOD15-24 for 8626M;	///GPIOD12	nRst;	///GPIOD13    n_int;	eth_set_pinmux(ETH_BANK2_GPIOD15_D23,ETH_CLK_OUT_GPIOD24_REG5_1,0);	/*disalbe*/	//reset:LCD_G5	writel(readl(ETH_PLL_CNTL) & ~(1 << 0), ETH_PLL_CNTL); // Disable the Ethernet clocks     	// ---------------------------------------------	// Test 50Mhz Input Divide by 2	// ---------------------------------------------	// Select divide by 2	writel(readl(ETH_PLL_CNTL) | (0 << 3), ETH_PLL_CNTL); // desc endianess "same order"   	writel(readl(ETH_PLL_CNTL) | (0 << 2), ETH_PLL_CNTL); // data endianess "little"    	writel(readl(ETH_PLL_CNTL) | (1 << 1), ETH_PLL_CNTL); // divide by 2 for 100M     	writel(readl(ETH_PLL_CNTL) | (1 << 0), ETH_PLL_CNTL);  // enable Ethernet clocks   	udelay(100);	/*reset*/	CLEAR_CBUS_REG_MASK(PREG_GGPIO_EN_N,1<<12);	CLEAR_CBUS_REG_MASK(PREG_GGPIO_O,1<<12);	udelay(100);	SET_CBUS_REG_MASK(PREG_GGPIO_O,1<<12);	udelay(10);	//waiting reset end;	aml_eth_init(bis);	return 0;}

static int __init clk81_clock_setup(char *ptr){    int clock = clkparse(ptr,0);    int divider = 4;    if (clock<100000000)        divider = 8;    if (other_pll_setting(0, clock*divider) == 0) {        /* todo: uart baudrate depends on clk81, assume 115200 baudrate */        int baudrate = (clock / (115200 * 4)) - 1;        clk_other_pll.rate = clock * divider;        clk81.rate = clock;        WRITE_MPEG_REG(HHI_MPEG_CLK_CNTL,   // MPEG clk81 set to other/4                  (1 << 12) |               // select other PLL                  ((divider - 1) << 0 ) |         // div1                  (1 << 7 ) |               // cntl_hi_mpeg_div_en, enable gating                  (1 << 8 ));               // Connect clk81 to the PLL divider output        CLEAR_CBUS_REG_MASK(UART0_CONTROL, (1 << 19) | 0xFFF);        SET_CBUS_REG_MASK(UART0_CONTROL, (baudrate & 0xfff));        CLEAR_CBUS_REG_MASK(UART1_CONTROL, (1 << 19) | 0xFFF);        SET_CBUS_REG_MASK(UART1_CONTROL, (baudrate & 0xfff));    }    return 0;}

//#define NET_EXT_CLK 1static void __init eth_pinmux_init(void){	   CLEAR_CBUS_REG_MASK(PERIPHS_PIN_MUX_6,(3<<17));//reg6[17/18]=0   #ifdef NET_EXT_CLK       eth_set_pinmux(ETH_BANK0_GPIOY1_Y9, ETH_CLK_IN_GPIOY0_REG6_18, 0);   #else       eth_set_pinmux(ETH_BANK0_GPIOY1_Y9, ETH_CLK_OUT_GPIOY0_REG6_17, 0);   #endif	    //power hold    //setbits_le32(P_PREG_AGPIO_O,(1<<8));    //clrbits_le32(P_PREG_AGPIO_EN_N,(1<<8));    //set_gpio_mode(GPIOA_bank_bit(4),GPIOA_bit_bit0_14(4),GPIO_OUTPUT_MODE);    //set_gpio_val(GPIOA_bank_bit(4),GPIOA_bit_bit0_14(4),1);    CLEAR_CBUS_REG_MASK(PREG_ETHERNET_ADDR0, 1);           // Disable the Ethernet clocks	// ---------------------------------------------	// Test 50Mhz Input Divide by 2	// ---------------------------------------------	// Select divide by 2    CLEAR_CBUS_REG_MASK(PREG_ETHERNET_ADDR0, (1<<3));     // desc endianess "same order"     CLEAR_CBUS_REG_MASK(PREG_ETHERNET_ADDR0, (1<<2));     // ata endianess "little"    SET_CBUS_REG_MASK(PREG_ETHERNET_ADDR0, (1 << 1));     // divide by 2 for 100M    SET_CBUS_REG_MASK(PREG_ETHERNET_ADDR0, 1);            // enable Ethernet clocks    udelay(100);    // ethernet reset    set_gpio_mode(GPIOD_bank_bit0_9(7), GPIOD_bit_bit0_9(7), GPIO_OUTPUT_MODE);    set_gpio_val(GPIOD_bank_bit0_9(7), GPIOD_bit_bit0_9(7), 0);    mdelay(100);    set_gpio_val(GPIOD_bank_bit0_9(7), GPIOD_bit_bit0_9(7), 1);}

void set_usb_ctl_por(int index, int por_flag){    int msk = PREI_USB_PHY_A_POR;    char * msg;    char * ctl;    char * state;    if (index == USB_CTL_INDEX_B) {        msk = PREI_USB_PHY_B_POR;        ctl = "B";        state = &usb_ctl_b_state;    } else if (index == USB_CTL_INDEX_A) {        msk = PREI_USB_PHY_A_POR;        ctl = "A";        state = &usb_ctl_a_state;    } else {        printf("error usb_ctl index %d/n", index);        return;    }    switch (por_flag) {    case USB_CTL_POR_ON:        if (*state > USB_CTL_POR_ENABLE) {            return;        }        msg = "on";        CLEAR_CBUS_REG_MASK(PREI_USB_PHY_REG, msk);        break;    case USB_CTL_POR_OFF:        if (*state > USB_CTL_POR_ENABLE) {            return;        }        msg = "off";        SET_CBUS_REG_MASK(PREI_USB_PHY_REG, msk);        break;    case USB_CTL_POR_ENABLE:        msg = "enable";        CLEAR_CBUS_REG_MASK(PREI_USB_PHY_REG, msk);        *state = USB_CTL_POR_ENABLE;        break;    case USB_CTL_POR_DISABLE:        msg = "disable";        SET_CBUS_REG_MASK(PREI_USB_PHY_REG, msk);        *state = USB_CTL_POR_DISABLE;        break;    default:        printf("error usb_ctl por_flag %d/n", por_flag);        return;    }    printf("usb controller %s %s/n", ctl, msg);}

_mali_osk_errcode_t mali_platform_power_mode_change(mali_power_mode power_mode){    /* turn off MALI clock gating */    unsigned long flags;    unsigned cpu_divider, mali_divider;    unsigned ddr_pll_setting, sys_pll_setting;    unsigned cpu_freq, ddr_freq;    int mali_flag;    switch (power_mode) {        case MALI_POWER_MODE_LIGHT_SLEEP:            /* turn on MALI clock gating */			CLEAR_CBUS_REG_MASK(HHI_MALI_CLK_CNTL, 1 << 8);			break;	    case MALI_POWER_MODE_DEEP_SLEEP:            /* turn on MALI clock gating */            CLEAR_CBUS_REG_MASK(HHI_MALI_CLK_CNTL, 1 << 8);            break;        case MALI_POWER_MODE_ON:            /* turn off MALI clock gating */			local_irq_save(flags);			CLEAR_CBUS_REG_MASK(HHI_MALI_CLK_CNTL, 1 << 8);			sys_pll_setting = READ_MPEG_REG(HHI_SYS_PLL_CNTL);			cpu_freq = ((sys_pll_setting&0x1ff)*24)>>(sys_pll_setting>>16); // assume 24M xtal			cpu_divider = READ_MPEG_REG_BITS(HHI_SYS_CPU_CLK_CNTL, 2, 2);			if (cpu_divider == 3)				cpu_divider = 2; // now fix at /4			cpu_freq >>= cpu_divider;			ddr_pll_setting = READ_MPEG_REG(HHI_DDR_PLL_CNTL);			ddr_freq = ((ddr_pll_setting&0x1ff)*24)>>((ddr_pll_setting>>16)&3);			mali_divider = 1;			while ((mali_divider * cpu_freq < ddr_freq) || (264 * mali_divider < ddr_freq)) // assume mali max 264M				mali_divider++;			mali_flag = ((mali_divider-1) != (READ_MPEG_REG(HHI_MALI_CLK_CNTL)&0x7f));			if (mali_flag){				WRITE_CBUS_REG(HHI_MALI_CLK_CNTL,					(3 << 9)    |                   // select ddr pll as clock source					((mali_divider-1) << 0)); // ddr clk / divider				READ_CBUS_REG(HHI_MALI_CLK_CNTL); // delay			}			SET_CBUS_REG_MASK(HHI_MALI_CLK_CNTL, 1 << 8);			local_irq_restore(flags);			if (mali_flag)				printk("(CTS_MALI_CLK) = %d/%d = %dMHz --- when mali gate on/n", ddr_freq, mali_divider, ddr_freq/mali_divider);            mali_meson_poweron();            break;    }    last_power_mode = power_mode;    MALI_SUCCESS;}

void power_init_off(void){#if 0    CLEAR_CBUS_REG_MASK(HHI_DEMOD_CLK_CNTL, (1 << 8));    CLEAR_CBUS_REG_MASK(HHI_SATA_CLK_CNTL, (1 << 8));    CLEAR_CBUS_REG_MASK(HHI_ETH_CLK_CNTL, (1 << 8));    CLEAR_CBUS_REG_MASK(HHI_WIFI_CLK_CNTL, (1 << 0));    SET_CBUS_REG_MASK(HHI_DEMOD_PLL_CNTL, (1 << 15));#endif}

void set_usb_phy_clock(amlogic_usb_config_t * usb_cfg){    int clk_sel = usb_cfg->clk_selecter;	// ------------------------------------------------------------	//  CLK_SEL: These bits select the source for the 12Mhz: 	// 0 = XTAL input (24, 25, 27Mhz)	// 1 = XTAL input divided by 2	// 2 = other PLL output	// 3 = DDR pll clock (typically 400mhz)	// 4 = demod 240Mhz PLL output	CLEAR_CBUS_REG_MASK(PREI_USB_PHY_REG, PREI_USB_PHY_CLK_SEL);	//clk_sel = 0; // 24M CLK 	//clk_sel = 1; // 12M, Phy default setting is 12Mhz	//clk_sel = 2; // other PLL, 540M	//clk_sel = 3; // DDR, 369M	//clk_sel = 4; // demod, 240M		printf("usb clk_sel: %s/n",clock_src_name[clk_sel]);	SET_CBUS_REG_MASK(PREI_USB_PHY_REG, (clk_sel<<5 ));	CLEAR_CBUS_REG_MASK(PREI_USB_PHY_REG,PREI_USB_PHY_CLK_DIV);	switch(clk_sel)	{		case USB_PHY_CLOCK_SEL_XTAL:			//XTAL 24M, Divide by 2			SET_CBUS_REG_MASK(PREI_USB_PHY_REG, (1 << 24));			break;					case USB_PHY_CLOCK_SEL_XTAL_DIV2:			//XTAL 24M, Divide by 1			SET_CBUS_REG_MASK(PREI_USB_PHY_REG, (0 << 24));			break;					case USB_PHY_CLOCK_SEL_OTHER_PLL:			//Other PLL running at 540M (540/(44+1)=12)			SET_CBUS_REG_MASK(PREI_USB_PHY_REG, (44 << 24));			break;					case USB_PHY_CLOCK_SEL_DDR_PLL:			//DDR runing 396MHz (396/(32+1)=12)			SET_CBUS_REG_MASK(PREI_USB_PHY_REG, (32 << 24));			break;					case USB_PHY_CLOCK_SEL_DEMOD_PLL:			// demod 240M (240/(19+1) = 12)			SET_CBUS_REG_MASK(PREI_USB_PHY_REG, (19 << 24));			break;	}	// Open clock gate, to enable CLOCK to usb phy 	SET_CBUS_REG_MASK(PREI_USB_PHY_REG, PREI_USB_PHY_CLK_GATE);}

static int  sdio_init(unsigned port){    if(port == SDIO_PORT_B1){        printf("iNand Reset (GPIOE_17)/n");        CLEAR_CBUS_REG_MASK(PREG_HGPIO_O,1<<17);        CLEAR_CBUS_REG_MASK(PREG_HGPIO_EN_N,1<<17);        mdelay(150);        SET_CBUS_REG_MASK(PREG_HGPIO_O,1<<17);        mdelay(50);        }    return cpu_sdio_init(port);}

void power_off_backlight(void){    //EIO -> PP1: 0  //EIO -> OD4: 1#ifdef CONFIG_SN7325    configIO(1, 0);  //configIO(0, 0);    setIO_level(1, 1, 1);  //setIO_level(0, 1, 4);#endif    CLEAR_CBUS_REG_MASK(PERIPHS_PIN_MUX_2, (1<<31));    CLEAR_CBUS_REG_MASK(PWM_MISC_REG_AB, (1 << 0));    set_gpio_val(GPIOA_bank_bit(7), GPIOA_bit_bit0_14(7), 0);    set_gpio_mode(GPIOA_bank_bit(7), GPIOA_bit_bit0_14(7), GPIO_OUTPUT_MODE);}

static void set_bat_off(void){    //BL_PWM power off    CLEAR_CBUS_REG_MASK(PERIPHS_PIN_MUX_2, (1<<31));    CLEAR_CBUS_REG_MASK(PWM_MISC_REG_AB, (1 << 0));    //set_gpio_val(GPIOA_bank_bit(7), GPIOA_bit_bit0_14(7), 0);    //set_gpio_mode(GPIOA_bank_bit(7), GPIOA_bit_bit0_14(7), GPIO_OUTPUT_MODE);    //VCCx2 power down#if defined(CONFIG_SUSPEND)    set_vccx2(0);#endif}

/*************************************************  * Amlogic Ethernet controller operation  *   * Note: The LAN chip LAN8720 need to be reset by GPIOA_23  *  *************************************************/static void setup_net_chip(void){	//disable all other pins which share the GPIOA_23    CLEAR_CBUS_REG_MASK(PERIPHS_PIN_MUX_0,(1<<6)); //LCDin_B7 R0[6]    CLEAR_CBUS_REG_MASK(PERIPHS_PIN_MUX_7,(1<<11));//ENC_11 R7[11]	//GPIOA_23 -> 0    CLEAR_CBUS_REG_MASK(PREG_EGPIO_O,1<<23);    //RST -> 0    //GPIOA_23 output enable    CLEAR_CBUS_REG_MASK(PREG_EGPIO_EN_N,1<<23); //OUTPUT enable	    udelay(2000);	//GPIOA_23 -> 1    SET_CBUS_REG_MASK(PREG_EGPIO_O,1<<23);      //RST -> 1    udelay(2000);	}

static void init_pwm_a(void){    CLEAR_CBUS_REG_MASK(PWM_MISC_REG_AB, ((1<<15)|(0<<8)|(1<<0)));//close PWM_A by default    msleep(100);    //GPIOC_0    CLEAR_CBUS_REG_MASK(PERIPHS_PIN_MUX_0, (1<<21));//dis VGA_HS	CLEAR_CBUS_REG_MASK(PERIPHS_PIN_MUX_1, (1<<27));// dis VGHL_PWM    SET_CBUS_REG_MASK(PERIPHS_PIN_MUX_2, (1<<0));// enable pwma    msleep(100);	WRITE_CBUS_REG_BITS(PWM_PWM_A, pwm_level, 0, 16);  //low    WRITE_CBUS_REG_BITS(PWM_PWM_A, pwm_level, 16, 16);  //hi}

int board_eth_init(bd_t *bis){    /*    @todo implement this function    */    //eth_clk_set(ETH_CLKSRC_SYS_D3,900*CLK_1M/3,50*CLK_1M);    eth_clk_set(ETH_CLKSRC_SYS_D3,get_cpu_clk()*2/3,50*CLK_1M);    // GPIOX59-X67 for M2_socket    // GPIOE_57/NA nRst;    eth_set_pinmux(ETH_BANK1_GPIOX59_X67,ETH_CLK_OUT_GPIOX68_REG3_14,0);    CLEAR_CBUS_REG_MASK(PREG_ETHERNET_ADDR0, 1);    SET_CBUS_REG_MASK(PREG_ETHERNET_ADDR0, (1 << 1));    SET_CBUS_REG_MASK(PREG_ETHERNET_ADDR0, 1);    udelay(100);    /*reset*/    set_gpio_val(GPIOX_bank_bit32_63(57), GPIOX_bit_bit32_63(57), 0);    set_gpio_mode(GPIOX_bank_bit32_63(57), GPIOX_bit_bit32_63(57), GPIO_OUTPUT_MODE);    udelay(100);    set_gpio_val(GPIOX_bank_bit32_63(57), GPIOX_bit_bit32_63(57), 1);    set_gpio_mode(GPIOX_bank_bit32_63(57), GPIOX_bit_bit32_63(57), GPIO_OUTPUT_MODE);    udelay(10);    //waiting reset end;    aml_eth_init(bis);    return 0;}

static void __init meson_clockevent_init(void){	CLEAR_CBUS_REG_MASK(ISA_TIMER_MUX, TIMER_A_INPUT_MASK | TIMER_C_INPUT_MASK);	SET_CBUS_REG_MASK(ISA_TIMER_MUX, 		(TIMER_UNIT_1us << TIMER_A_INPUT_BIT) |		(TIMER_UNIT_1us << TIMER_C_INPUT_BIT));	//WRITE_CBUS_REG(ISA_TIMERA, 9999);	WRITE_CBUS_REG(ISA_TIMERA, 9999);		clockevent_meson_1mhz.mult =		div_sc(1000000, NSEC_PER_SEC, clockevent_meson_1mhz.shift);	clockevent_meson_1mhz.max_delta_ns =		clockevent_delta2ns(0xfffe, &clockevent_meson_1mhz);	clockevent_meson_1mhz.min_delta_ns =		clockevent_delta2ns(1, &clockevent_meson_1mhz);	clockevent_meson_1mhz.cpumask = cpumask_of(0);	clockevents_register_device(&clockevent_meson_1mhz);	printk("meson_clockevent_init : mult = %ld, max = %ld, min = %ld/r/n"			,clockevent_meson_1mhz.mult			,clockevent_meson_1mhz.max_delta_ns,			clockevent_meson_1mhz.min_delta_ns);		/* Set up the IRQ handler */	setup_irq(INT_TIMER_A, &meson_timer_irq);	//setup_irq(INT_TIMER_C, &meson_timer_irq);}

int board_init(void){#ifdef CONFIG_UART_A_FUNCTION_ADD	unsigned a_uart = (159375000/(115200*4) -1)        | UART_STP_BIT         | UART_PRTY_BIT        | UART_CHAR_LEN         | UART_CNTL_MASK_TX_EN        | UART_CNTL_MASK_RX_EN        | UART_CNTL_MASK_RST_TX        | UART_CNTL_MASK_RST_RX        | UART_CNTL_MASK_CLR_ERR ;  serial_init_uart_a(a_uart);#endif#if KSZ8091	CLEAR_CBUS_REG_MASK(PREG_PAD_GPIO1_EN_N, 1 << 31);	CLEAR_CBUS_REG_MASK(PREG_PAD_GPIO1_O, 1 << 31);#endif	gd->bd->bi_arch_number=MACH_TYPE_MESON6_SKT;	gd->bd->bi_boot_params=BOOT_PARAMS_OFFSET;#if CONFIG_JERRY_NAND_TEST //temp test    nand_init();#endif    // LED    clrbits_le32(P_AO_GPIO_O_EN_N, (1 << 15));    clrbits_le32(P_AO_GPIO_O_EN_N, (1 << 31));#ifdef CONFIG_AML_I2C	board_i2c_init();#endif /*CONFIG_AML_I2C*/#ifdef CONFIG_IR_REMOTE	board_ir_init();#endif#ifdef CONFIG_USB_DWC_OTG_HCD	board_usb_init(&g_usb_config_m6_skt_b,BOARD_USB_MODE_HOST);	board_usb_init(&g_usb_config_m6_skt_h,BOARD_USB_MODE_CHARGER);#endif /*CONFIG_USB_DWC_OTG_HCD*/#ifdef CONFIG_NET_WIFI	wifi_power_init();#endif        key_init();	return 0;}

static set_vbus_valid_ext_fun(unsigned int id,char val){	unsigned int  reg = (PREI_USB_PHY_A_REG1 + id);	if(val == 1)		SET_CBUS_REG_MASK(reg,1<<0);	else		CLEAR_CBUS_REG_MASK(reg,1<<0);}

static void enable_vsync_interrupt(void){    printk("enable_vsync_interrupt/n");    CLEAR_CBUS_REG_MASK(HHI_MPEG_CLK_CNTL, 1<<11);    if (READ_MPEG_REG(ENCP_VIDEO_EN) & 1) {        WRITE_MPEG_REG(VENC_INTCTRL, 0x200);#ifdef CONFIG_ARCH_MESON1        while ((READ_MPEG_REG(VENC_INTFLAG) & 0x200) == 0) {            u32 line1, line2;            line1 = line2 = READ_MPEG_REG(VENC_ENCP_LINE);            while (line1 >= line2) {                line2 = line1;                line1 = READ_MPEG_REG(VENC_ENCP_LINE);            }            READ_MPEG_REG(VENC_INTFLAG);            READ_MPEG_REG(VENC_INTFLAG);            READ_MPEG_REG(VENC_INTFLAG);            READ_MPEG_REG(VENC_INTFLAG);            if (READ_MPEG_REG(VENC_INTFLAG) & 0x200) {                break;            }            WRITE_MPEG_REG(ENCP_VIDEO_EN, 0);            READ_MPEG_REG(VENC_INTFLAG);            READ_MPEG_REG(VENC_INTFLAG);            READ_MPEG_REG(VENC_INTFLAG);            READ_MPEG_REG(VENC_INTFLAG);            READ_MPEG_REG(VENC_INTFLAG);            WRITE_MPEG_REG(ENCP_VIDEO_EN, 1);            READ_MPEG_REG(VENC_INTFLAG);            READ_MPEG_REG(VENC_INTFLAG);            READ_MPEG_REG(VENC_INTFLAG);            READ_MPEG_REG(VENC_INTFLAG);            READ_MPEG_REG(VENC_INTFLAG);        }#else        while ((READ_MPEG_REG(VENC_INTFLAG) & 0x200) == 0) {            mdelay(50);            WRITE_MPEG_REG(ENCP_VIDEO_EN, 0);            READ_MPEG_REG(VENC_INTFLAG);            WRITE_MPEG_REG(ENCP_VIDEO_EN, 1);            printk("recycle TV encoder/n");        }#endif    }    else{        WRITE_MPEG_REG(VENC_INTCTRL, 0x2);    }    printk("Enable vsync done/n");}

static void init_timer_b(void){    printk(KERN_INFO "init_timer_b/n");    CLEAR_CBUS_REG_MASK(ISA_TIMER_MUX, TIMER_B_INPUT_MASK);    SET_CBUS_REG_MASK(ISA_TIMER_MUX, TIMER_UNIT_10us << TIMER_B_INPUT_BIT);        /* Set up the fiq handler */    request_fiq(INT_TIMER_B, &timer_b_interrupt);}

void clk_switch(int flag){    int i;    if (flag) {        for (i = CLK_COUNT - 1; i >= 0; i--) {            if (clk_flag[i]) {                if ((clks[i] == HHI_VID_CLK_CNTL)||(clks[i] == HHI_VIID_CLK_CNTL)) {                    WRITE_CBUS_REG_BITS(clks[i], clk_flag[i], 19, 2);                } else if (clks[i] == HHI_MPEG_CLK_CNTL) {                    udelay(1000);                    SET_CBUS_REG_MASK(clks[i], (1 << 8)); // normal                    CLEAR_CBUS_REG_MASK(UART0_CONTROL, (1 << 19) | 0xFFF);                    SET_CBUS_REG_MASK(UART0_CONTROL, (((uart_rate_backup / (115200 * 4)) - 1) & 0xfff));                    CLEAR_CBUS_REG_MASK(UART1_CONTROL, (1 << 19) | 0xFFF);                    SET_CBUS_REG_MASK(UART1_CONTROL, (((uart_rate_backup / (115200 * 4)) - 1) & 0xfff));                    CLEAR_AOBUS_REG_MASK(AO_UART_CONTROL, (1 << 19) | 0xFFF);                    WRITE_AOBUS_REG_BITS(AO_UART_CONTROL, ((uart_rate_backup / (115200 * 4)) - 1) & 0xfff, 0, 12);                } else {                    SET_CBUS_REG_MASK(clks[i], (1 << 8));                }                clk_flag[i] = 0;                printf("clk %s(%x) on/n", clks_name[i], clks[i]);            }        }    } else {        for (i = 0; i < CLK_COUNT; i++) {            if ((clks[i] == HHI_VID_CLK_CNTL)||(clks[i] == HHI_VIID_CLK_CNTL)) {                clk_flag[i] = READ_CBUS_REG_BITS(clks[i], 19, 2);                if (clk_flag[i]) {                    CLEAR_CBUS_REG_MASK(clks[i], (1<<19)|(1<<20));                }            } else if (clks[i] == HHI_MPEG_CLK_CNTL) {                if (READ_CBUS_REG(clks[i]) & (1 << 8)) {                    clk_flag[i] = 1;                    udelay(1000);                    CLEAR_CBUS_REG_MASK(clks[i], (1 << 8)); // 24M                    CLEAR_CBUS_REG_MASK(UART0_CONTROL, (1 << 19) | 0xFFF);                    SET_CBUS_REG_MASK(UART0_CONTROL, (((xtal_uart_rate_backup / (115200 * 4)) - 1) & 0xfff));                    CLEAR_CBUS_REG_MASK(UART1_CONTROL, (1 << 19) | 0xFFF);                    SET_CBUS_REG_MASK(UART1_CONTROL, (((xtal_uart_rate_backup / (115200 * 4)) - 1) & 0xfff));                    CLEAR_AOBUS_REG_MASK(AO_UART_CONTROL, (1 << 19) | 0xFFF);                    WRITE_AOBUS_REG_BITS(AO_UART_CONTROL, ((xtal_uart_rate_backup / (115200 * 4)) - 1) & 0xfff, 0, 12);                }            } else {                clk_flag[i] = READ_CBUS_REG_BITS(clks[i], 8, 1) ? 1 : 0;                if (clk_flag[i]) {                    CLEAR_CBUS_REG_MASK(clks[i], (1 << 8));                }            }            if (clk_flag[i]) {                printf("clk %s(%x) off/n", clks_name[i], clks[i]);            }        }    }}

/*out_freq=crystal_req*m/nout_freq=crystal_req*m/n-->n=crystal_req*m/out_freqm=out_freq*n/crystal_req*/int demod_apll_setting(unsigned crystal_req,unsigned out_freq){    int n,m;    unsigned long crys_M,out_M,middle_freq;    if(!crystal_req)  crystal_req=get_xtal_clock();    crys_M=crystal_req/1000000;    out_M=out_freq/1000000;    middle_freq=get_max_common_divisor(crys_M,out_M);    n=crys_M/middle_freq;    m=out_M/(middle_freq);    if(n>(1<<5)-1)    {        printk(KERN_ERR "demod_apll_setting setting error, n is too bigger n=%d,crys_M=%ldM,out_M=%ldM/n",        n,crys_M,out_M);        return -1;    }    if(m>(1<<9)-1)    {        printk(KERN_ERR "demod_apll_setting setting error, m is too bigger m=%d,crys_M=%ldM,out_M=%ldM/n",        m,crys_M,out_M);        return -2;    }    printk("demod_apll_setting crystal_req=%ld,out_freq=%ld,n=%d,m=%dM/n",crys_M,out_M,n,m);    /*==========Set Demod PLL, should be in system setting===========*/    SET_CBUS_REG_MASK(HHI_DEMOD_PLL_CNTL, 1 << 15); //power down Demod PLL    //Set 400M PLL    CLEAR_CBUS_REG_MASK(HHI_DEMOD_PLL_CNTL2,0xFFFFFFFF);    SET_CBUS_REG_MASK(HHI_DEMOD_PLL_CNTL2,0x65e31ff);    CLEAR_CBUS_REG_MASK(HHI_DEMOD_PLL_CNTL3,0xFFFFFFFF);    SET_CBUS_REG_MASK(HHI_DEMOD_PLL_CNTL3,0x1649a941);    //Set 1.2G PLL    CLEAR_CBUS_REG_MASK(HHI_DEMOD_PLL_CNTL,0xFFFF7FFF);    SET_CBUS_REG_MASK(HHI_DEMOD_PLL_CNTL,n<<9 | m<< 0);    CLEAR_CBUS_REG_MASK(HHI_DEMOD_PLL_CNTL, 1 << 15); //power on Demod PLL    WRITE_CBUS_REG(0x1106, 0x08);    return 0;}

static void init_pwm_d(void){    CLEAR_CBUS_REG_MASK(PWM_MISC_REG_CD, (1 << 1));//close PWM_D by default    msleep(100);    SET_CBUS_REG_MASK(PERIPHS_PIN_MUX_2, (1<<3));    msleep(100);	WRITE_CBUS_REG_BITS(PWM_PWM_D, pwm_level, 0, 16);  //low    WRITE_CBUS_REG_BITS(PWM_PWM_D, pwm_level, 16, 16);  //hi}

/*************************************************  * Amlogic Ethernet controller operation  *   * Note: The LAN chip LAN8720 need to be reset  *  *************************************************/static void setup_net_chip(void){	//m8 only use externel clock	/* setup ethernet clk */	WRITE_CBUS_REG(HHI_ETH_CLK_CNTL, 0x4f00); // clock Input 50 inverted : bit14 =1 Div : 6:0 = 0 En : bit8 = 1  Sel : bit 11:9 = 7	/* setup ethernet pinmux use gpioz(5-14) */	SET_CBUS_REG_MASK(PERIPHS_PIN_MUX_6, (1 << 14) | (1 << 13) | (1 << 12) |	(1 << 11) | (1 << 8 ) | (1 << 7 ) | (1 << 9 ) | (1 << 6 ) | (1 << 5 ));	/* setup ethernet mode */	WRITE_CBUS_REG(PREG_ETHERNET_ADDR0, 0x211);//bit6-4 :001 rmii mode	/* setup ethernet interrupt use num 8 */	//SET_CBUS_REG_MASK(MEDIA_CPU_INTR_MASK, 1 << 8);	//SET_CBUS_REG_MASK(MEDIA_CPU_INTR_STAT, 1 << 8);	/* hardware reset ethernet phy : gpioz14 connect phyreset pin*/	CLEAR_CBUS_REG_MASK(PREG_PAD_GPIO1_EN_N, 1 << 31);	CLEAR_CBUS_REG_MASK(PREG_PAD_GPIO1_O, 1 << 31);	udelay(2000);	SET_CBUS_REG_MASK(PREG_PAD_GPIO1_O, 1 << 31);}