自学教程：C++ CLK_SetHCLK函数代码示例

void SYS_Init(void){    /*---------------------------------------------------------------------------------------------------------*/    /* Init System Clock                                                                                       */    /*---------------------------------------------------------------------------------------------------------*/    /* Unlock protected registers */    SYS_UnlockReg();    /* Enable External XTAL (4~24 MHz) */    CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk);    /* Waiting for 12MHz clock ready */    CLK_WaitClockReady( CLK_STATUS_HXTSTB_Msk);    /* Switch HCLK clock source to HXT */    CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HXT,CLK_CLKDIV0_HCLK(1));    /* Set PLL to power down mode and PLL_STB bit in CLKSTATUS register will be cleared by hardware.*/    CLK->PLLCTL |= CLK_PLLCTL_PD_Msk;    /* Set PLL frequency */    CLK->PLLCTL = CLK_PLLCTL_84MHz_HXT;    /* Waiting for clock ready */    CLK_WaitClockReady(CLK_STATUS_PLLSTB_Msk);    /* Switch HCLK clock source to PLL */    CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_PLL,CLK_CLKDIV0_HCLK(1));    /* Enable IP clock */    CLK_EnableModuleClock(UART0_MODULE);    CLK_EnableModuleClock(TMR0_MODULE);    CLK_EnableModuleClock(SPI0_MODULE);    CLK_EnableModuleClock(SPI1_MODULE);    /* Select IP clock source */    CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UARTSEL_HXT, CLK_CLKDIV0_UART(1));    CLK_SetModuleClock(TMR0_MODULE, CLK_CLKSEL1_TMR0SEL_HXT, 0);    /* Update System Core Clock */    /* User can use SystemCoreClockUpdate() to calculate SystemCoreClock. */    SystemCoreClockUpdate();    /*---------------------------------------------------------------------------------------------------------*/    /* Init I/O Multi-function                                                                                 */    /*---------------------------------------------------------------------------------------------------------*/    /* Set GPG multi-function pins for UART0 RXD and TXD */    SYS->GPG_MFPL = SYS_GPG_MFPL_PG1MFP_UART0_RXD | SYS_GPG_MFPL_PG2MFP_UART0_TXD ;    /* SPI0: GPE4=SS0, GPE3=MOSI0, GPE2=MISO0, GPE5=CLK */    SYS->GPE_MFPL = (SYS_GPE_MFPL_PE2MFP_SPI0_MISO0 | SYS_GPE_MFPL_PE3MFP_SPI0_MOSI0 | SYS_GPE_MFPL_PE4MFP_SPI0_SS0 | SYS_GPE_MFPL_PE5MFP_SPI0_CLK);    /* SPI1: GPC12=SS0, GPC15=MOSI0, GPD0=MISO0, GPD1=CLK */    SYS->GPC_MFPH |= (SYS_GPC_MFPH_PC12MFP_SPI1_SS0 | SYS_GPC_MFPH_PC15MFP_SPI1_MOSI0);    SYS->GPD_MFPL = (SYS_GPD_MFPL_PD0MFP_SPI1_MISO0 | SYS_GPD_MFPL_PD1MFP_SPI1_CLK);    /* Lock protected registers */    SYS_LockReg();}

void SYS_Init(void){    /*---------------------------------------------------------------------------------------------------------*/    /* Init System Clock                                                                                       */    /*---------------------------------------------------------------------------------------------------------*/    /* Enable Internal RC clock */    CLK_EnableXtalRC(CLK_PWRCON_OSC22M_EN_Msk);    /* Waiting for IRC22M clock ready */    CLK_WaitClockReady(CLK_CLKSTATUS_OSC22M_STB_Msk);    /* Switch HCLK clock source to Internal RC and HCLK source divide 1 */    CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_HIRC, CLK_CLKDIV_HCLK(1));    /* Enable external 12MHz XTAL, internal 22.1184MHz */    CLK_EnableXtalRC(CLK_PWRCON_XTL12M_EN_Msk | CLK_PWRCON_OSC22M_EN_Msk);    /* Enable PLL and Set PLL frequency */    CLK_SetCoreClock(PLLCON_SETTING);    /* Waiting for clock ready */    CLK_WaitClockReady(CLK_CLKSTATUS_PLL_STB_Msk | CLK_CLKSTATUS_XTL12M_STB_Msk | CLK_CLKSTATUS_OSC22M_STB_Msk);    /* Switch HCLK clock source to PLL, STCLK to HCLK/2 */    CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_PLL, CLK_CLKDIV_HCLK(2));    /* Enable UART module clock */    CLK_EnableModuleClock(UART0_MODULE);    /* Enable PWM module clock */    CLK_EnableModuleClock(PWM01_MODULE);    CLK_EnableModuleClock(PWM23_MODULE);    /* Select UART module clock source */    CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UART_S_HXT, CLK_CLKDIV_UART(1));    /* Select PWM module clock source */    CLK_SetModuleClock(PWM01_MODULE, CLK_CLKSEL1_PWM01_S_HXT, 0);    CLK_SetModuleClock(PWM23_MODULE, CLK_CLKSEL1_PWM23_S_HXT, 0);    /* Reset PWMA channel0~channel3 */    SYS_ResetModule(PWM03_RST);    /* Update System Core Clock */    /* User can use SystemCoreClockUpdate() to calculate PllClock, SystemCoreClock and CycylesPerUs automatically. */    //SystemCoreClockUpdate();    PllClock        = PLL_CLOCK;            // PLL    SystemCoreClock = PLL_CLOCK / 1;        // HCLK    CyclesPerUs     = PLL_CLOCK / 1000000;  // For SYS_SysTickDelay()    /*---------------------------------------------------------------------------------------------------------*/    /* Init I/O Multi-function                                                                                 */    /*---------------------------------------------------------------------------------------------------------*/    /* Set P3 multi-function pins for UART0 RXD and TXD  */    SYS->P3_MFP = SYS_MFP_P30_RXD0 | SYS_MFP_P31_TXD0;    /* Set P2 multi-function pins for PWMA Channel0~3 */    SYS->P2_MFP = SYS_MFP_P20_PWM0 | SYS_MFP_P21_PWM1 | SYS_MFP_P22_PWM2 | SYS_MFP_P23_PWM3;}

void SYS_Init(void){    /*---------------------------------------------------------------------------------------------------------*/    /* Init System Clock                                                                                       */    /*---------------------------------------------------------------------------------------------------------*/    /* Unlock protected registers */    SYS_UnlockReg();    /* Enable External XTAL (4~24 MHz) */    CLK_EnableXtalRC(CLK_PWRCON_HXT_EN_Msk);    /* Waiting for 12MHz clock ready */    CLK_WaitClockReady(CLK_CLKSTATUS_HXT_STB_Msk);    /* Switch HCLK clock source to HXT */    CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_HXT,CLK_CLKDIV0_HCLK(1));    /* Set PLL to power down mode and PLL_STB bit in CLKSTATUS register will be cleared by hardware.*/    CLK->PLLCON |= CLK_PLLCON_PD_Msk;    /* Set PLL frequency */    CLK->PLLCON = PLLCON_SETTING;    /* Waiting for clock ready */    CLK_WaitClockReady(CLK_CLKSTATUS_PLL_STB_Msk);    /* Switch HCLK clock source to PLL */    CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_PLL,CLK_CLKDIV0_HCLK(1));    /* Enable IP clock */    CLK_EnableModuleClock(UART0_MODULE);    CLK_EnableModuleClock(PDMA_MODULE);    /* Select IP clock source */    CLK_SetModuleClock(UART0_MODULE,CLK_CLKSEL1_UART_S_HXT,CLK_CLKDIV0_UART(1));    /* Update System Core Clock */    /* User can use SystemCoreClockUpdate() to calculate SystemCoreClock. */    SystemCoreClockUpdate();    /*---------------------------------------------------------------------------------------------------------*/    /* Init I/O Multi-function                                                                                 */    /*---------------------------------------------------------------------------------------------------------*/    /* Set GPG multi-function pins for UART0 RXD and TXD */    SYS->GPG_MFPL &= ~(SYS_GPG_MFPL_PG1_MFP_Msk|SYS_GPG_MFPL_PG2_MFP_Msk);    SYS->GPG_MFPL |= SYS_GPG_MFPL_PG1_MFP_UART0_RXD | SYS_GPG_MFPL_PG2_MFP_UART0_TXD ;    /* Set GPG multi-function pins for CKO */    SYS->GPC_MFPL = (SYS->GPC_MFPL & ~SYS_GPC_MFPL_PC5_MFP_Msk) | SYS_GPC_MFPL_PC5_MFP_CLK_O ;    /* Lock protected registers */    SYS_LockReg();}

/*---------------------------------------------------------------------------------------------------------*/void SYS_Init(void){    /* Unlock protected registers */    SYS_UnlockReg();    /* Set HCLK source form HXT and HCLK source divide 1  */    CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_HXT,CLK_HCLK_CLK_DIVIDER(1));    /* Enable external 12MHz HXT, 32KHz LXT and HIRC */    CLK_EnableXtalRC(CLK_PWRCTL_HXT_EN_Msk | CLK_PWRCTL_LXT_EN_Msk | CLK_PWRCTL_HIRC_EN_Msk);    /*  Set HCLK frequency 12MHz */    CLK_SetCoreClock(12000000);    /* Enable IP clock */    CLK_EnableModuleClock(UART0_MODULE);    /* Select IP clock source */    CLK_SetModuleClock(UART0_MODULE,CLK_CLKSEL1_UART_S_HIRC,CLK_UART_CLK_DIVIDER(1));    /*---------------------------------------------------------------------------------------------------------*/    /* Init I/O Multi-function                                                                                 */    /*---------------------------------------------------------------------------------------------------------*/    /* Set PA multi-function pins for UART0 RXD and TXD */    SYS->PA_H_MFP &= ~( SYS_PA_H_MFP_PA15_MFP_Msk | SYS_PA_H_MFP_PA14_MFP_Msk);    SYS->PA_H_MFP |= (SYS_PA_H_MFP_PA15_MFP_UART0_TX|SYS_PA_H_MFP_PA14_MFP_UART0_RX);    /* Set PB multi-function pins for Clock Output */    SYS->PB_H_MFP = ( SYS->PB_H_MFP & ~SYS_PB_H_MFP_PB12_MFP_Msk ) |  SYS_PB_H_MFP_PB12_MFP_CKO;    /* Lock protected registers */    SYS_LockReg();}

/** * This function will initial Clock tree. */static void clock_init(void){    /* Unlock protected registers */    SYS_UnlockReg();    SystemInit();    /* Set XT1_OUT(PF.2) and XT1_IN(PF.3) to input mode */    PF->MODE &= ~(GPIO_MODE_MODE2_Msk | GPIO_MODE_MODE3_Msk);    /* Enable External XTAL (4~24 MHz) */    CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk);    /* Waiting for 12MHz clock ready */    CLK_WaitClockReady( CLK_STATUS_HXTSTB_Msk);    /* Switch HCLK clock source to HXT */    CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HXT,CLK_CLKDIV0_HCLK(1));    /* Set core clock as PLL_CLOCK from PLL */    CLK_SetCoreClock(FREQ_192MHZ);    /* Set both PCLK0 and PCLK1 as HCLK/4 */    CLK->PCLKDIV = CLK_PCLKDIV_PCLK0DIV4 | CLK_PCLKDIV_PCLK1DIV4;    SystemCoreClockUpdate();    /* Lock protected registers */    SYS_LockReg();}

void setupSystemClock(){	SYS_UnlockReg();  /*---------------------------------------------------------------------------------------------------------*/  /* Init System Clock                                                                                       */  /*---------------------------------------------------------------------------------------------------------*/	/* Enable HIRC clock */	CLK_EnableXtalRC(CLK_PWRCTL_HIRCEN_Msk);	/* Waiting for HIRC clock ready */	CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);	/* Switch HCLK clock source to HIRC */	CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HIRC, CLK_CLKDIV0_HCLK(1));	/* Enable external XTAL 12MHz clock */	//CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk);	/* Waiting for external XTAL clock ready */	//CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk);	/* Set core clock as PLL_CLOCK from PLL and SysTick source to HCLK/2*/	CLK_SetCoreClock(SYSTEM_CLOCK);	CLK_SetSysTickClockSrc(CLK_CLKSEL0_STCLKSEL_HCLK_DIV2);	/* Waiting for PLL clock ready */	CLK_WaitClockReady(CLK_STATUS_PLLSTB_Msk);	SYS_LockReg();}

void SYS_Init(void){    /*---------------------------------------------------------------------------------------------------------*/    /* Init System Clock                                                                                       */    /*---------------------------------------------------------------------------------------------------------*/    /* Unlock protected registers */    SYS_UnlockReg();    /* Set HCLK source form HXT and HCLK source divide 1  */    CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HXT, CLK_CLKDIV0_HCLK(1));    /*  Set HCLK frequency 42MHz */    CLK_SetCoreClock(42000000);    /* Select IP clock source */    CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UARTSEL_HIRC, CLK_CLKDIV0_UART(1));    /* Enable IP clock */    CLK_EnableModuleClock(UART0_MODULE);    /* Update System Core Clock */    /* User can use SystemCoreClockUpdate() to calculate PllClock, SystemCoreClock and CycylesPerUs automatically. */    SystemCoreClockUpdate();    /*---------------------------------------------------------------------------------------------------------*/    /* Init I/O Multi-function                                                                                 */    /*---------------------------------------------------------------------------------------------------------*/    /* Set PD multi-function pins for UART0 RXD(PD.0) and TXD(PD.1) */    SYS->GPD_MFPL &= ~(SYS_GPD_MFPL_PD0MFP_Msk | SYS_GPD_MFPL_PD1MFP_Msk);    SYS->GPD_MFPL |= (SYS_GPD_MFPL_PD0MFP_UART0_RXD | SYS_GPD_MFPL_PD1MFP_UART0_TXD);    /* Lock protected registers */    SYS_LockReg();}

void SYS_Init(void){    /*---------------------------------------------------------------------------------------------------------*/    /* Init System Clock                                                                                       */    /*---------------------------------------------------------------------------------------------------------*/    /* Enable Internal RC 22.1184MHz clock */    CLK_EnableXtalRC(CLK_PWRCON_OSC22M_EN_Msk);    /* Waiting for Internal RC clock ready */    CLK_WaitClockReady(CLK_CLKSTATUS_OSC22M_STB_Msk);    /* Switch HCLK clock source to Internal RC and HCLK source divide 1 */    CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_HIRC, CLK_CLKDIV_HCLK(1));    /* Enable external XTAL 12MHz clock */    CLK_EnableXtalRC(CLK_PWRCON_XTL12M_EN_Msk);    /* Waiting for clock ready */    CLK_WaitClockReady(CLK_CLKSTATUS_XTL12M_STB_Msk);    /* Set core clock as PLL_CLOCK from PLL */    CLK_SetCoreClock(PLL_CLOCK);        /* Enable UART module clock */    CLK_EnableModuleClock(UART0_MODULE);            /* Select UART module clock source */    CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UART_S_HXT, CLK_CLKDIV_UART(1));    /* Enable Timer 0~3 module clock */    CLK_EnableModuleClock(TMR0_MODULE);        CLK_EnableModuleClock(TMR2_MODULE);        CLK_EnableModuleClock(TMR3_MODULE);        /* Select Timer 0~3 module clock source */    CLK_SetModuleClock(TMR0_MODULE, CLK_CLKSEL1_TMR0_S_HXT, NULL);    CLK_SetModuleClock(TMR2_MODULE, CLK_CLKSEL1_TMR2_S_HCLK, NULL);    CLK_SetModuleClock(TMR3_MODULE, CLK_CLKSEL1_TMR3_S_HXT, NULL);    /*---------------------------------------------------------------------------------------------------------*/    /* Init I/O Multi-function                                                                                 */    /*---------------------------------------------------------------------------------------------------------*/    /* Set PB multi-function pins for UART0 RXD, TXD */    SYS->GPB_MFP &= ~(SYS_GPB_MFP_PB0_Msk | SYS_GPB_MFP_PB1_Msk);    SYS->GPB_MFP |= (SYS_GPB_MFP_PB0_UART0_RXD | SYS_GPB_MFP_PB1_UART0_TXD);    /* Set PB multi-function pins for TM0, TM2, TM3 and TM2_EXT */    SYS->GPB_MFP &= ~(SYS_GPB_MFP_PB8_Msk | SYS_GPB_MFP_PB10_Msk |                       SYS_GPB_MFP_PB11_Msk | SYS_GPB_MFP_PB2_Msk);    SYS->GPB_MFP |= (SYS_GPB_MFP_PB8_TM0 | SYS_GPB_MFP_PB10_TM2 |                      SYS_GPB_MFP_PB11_TM3 | SYS_GPB_MFP_PB2_TM2_EXT);    SYS->ALT_MFP  &= ~( SYS_ALT_MFP_PB8_Msk | SYS_ALT_MFP_PB10_Msk | SYS_ALT_MFP_PB11_Msk |                        SYS_ALT_MFP_PB2_Msk);    SYS->ALT_MFP  |= (SYS_ALT_MFP_PB8_TM0 | SYS_ALT_MFP_PB10_TM2 |SYS_ALT_MFP_PB11_TM3 |                      SYS_ALT_MFP_PB2_TM2_EXT);    SYS->ALT_MFP2 &= ~SYS_ALT_MFP2_PB2_TM2_Msk;    SYS->ALT_MFP2 |= SYS_ALT_MFP2_PB2_TM2_EXT;}

/** * Initializes the system. * System control registers must be unlocked. */void SYS_Init() {	// TODO: why is SYS_UnlockReg() needed? Should be already unlocked.	SYS_UnlockReg();	// HIRC clock (internal RC 22.1184MHz)	CLK_EnableXtalRC(CLK_PWRCTL_HIRCEN_Msk);	CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);		// HCLK clock source: HIRC, HCLK source divider: 1	CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HIRC, CLK_CLKDIV0_HCLK(1));		// HXT clock (external XTAL 12MHz)	CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk);	CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk);		// Enable 72MHz optimization	FMC_EnableFreqOptimizeMode(FMC_FTCTL_OPTIMIZE_72MHZ);		// Core clock: PLL	CLK_SetCoreClock(PLL_CLOCK);	CLK_WaitClockReady(CLK_STATUS_PLLSTB_Msk);		// SPI0 clock: PCLK0	CLK_SetModuleClock(SPI0_MODULE, CLK_CLKSEL2_SPI0SEL_PCLK0, 0);	CLK_EnableModuleClock(SPI0_MODULE);		// TMR0 clock: HXT	CLK_SetModuleClock(TMR0_MODULE, CLK_CLKSEL1_TMR0SEL_HXT, 0);	CLK_EnableModuleClock(TMR0_MODULE);	// USBD clock	CLK_SetModuleClock(USBD_MODULE, 0, CLK_CLKDIV0_USB(3));	CLK_EnableModuleClock(USBD_MODULE);		// Enable USB 3.3V LDO	SYS->USBPHY = SYS_USBPHY_LDO33EN_Msk;	// EADC clock: 72Mhz / 8	CLK_SetModuleClock(EADC_MODULE, 0, CLK_CLKDIV0_EADC(8));	CLK_EnableModuleClock(EADC_MODULE);		// Enable BOD (reset, 2.2V)	SYS_EnableBOD(SYS_BODCTL_BOD_RST_EN, SYS_BODCTL_BODVL_2_2V);		// Update system core clock	SystemCoreClockUpdate();	// Initialize dataflash	Dataflash_Init();	// Initialize I/O	Display_SetupSPI();	Button_Init();	ADC_Init();	// Initialize display	Display_Init();}

void SYS_Init(void){    /*---------------------------------------------------------------------------------------------------------*/    /* Init System Clock                                                                                       */    /*---------------------------------------------------------------------------------------------------------*/    /* Enable HIRC clock (Internal RC 22.1184MHz) */    CLK_EnableXtalRC(CLK_PWRCTL_HIRCEN_Msk);    /* Wait for HIRC clock ready */    CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);    /* Select HCLK clock source as HIRC and and HCLK source divider as 1 */    CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HIRC, CLK_CLKDIV0_HCLK(1));    /* Set PLL to Power-down mode and PLLSTB bit in CLK_STATUS register will be cleared by hardware.*/    CLK_DisablePLL();    /* Enable HXT clock (external XTAL 12MHz) */    CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk);    /* Wait for HXT clock ready */    CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk);    /* Set core clock as PLL_CLOCK from PLL */    CLK_SetCoreClock(PLL_CLOCK);    /* Enable UART module clock */    CLK_EnableModuleClock(UART0_MODULE);    /* Select UART module clock source as HXT and UART module clock divider as 1 */    CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UARTSEL_HXT, CLK_CLKDIV0_UART(1));    /* Enable EADC module clock */    CLK_EnableModuleClock(EADC_MODULE);    /* EADC clock source is 72MHz, set divider to 8, ADC clock is 72/8 MHz */    CLK_SetModuleClock(EADC_MODULE, 0, CLK_CLKDIV0_EADC(8));    /*---------------------------------------------------------------------------------------------------------*/    /* Init I/O Multi-function                                                                                 */    /*---------------------------------------------------------------------------------------------------------*/    /* Set PD multi-function pins for UART0 RXD and TXD */    SYS->GPD_MFPL &= ~(SYS_GPD_MFPL_PD0MFP_Msk | SYS_GPD_MFPL_PD1MFP_Msk);    SYS->GPD_MFPL |= (SYS_GPD_MFPL_PD0MFP_UART0_RXD | SYS_GPD_MFPL_PD1MFP_UART0_TXD);    /* Configure the GPB0 - GPB3 ADC analog input pins.  */    SYS->GPB_MFPL &= ~(SYS_GPB_MFPL_PB0MFP_Msk | SYS_GPB_MFPL_PB1MFP_Msk |                       SYS_GPB_MFPL_PB2MFP_Msk | SYS_GPB_MFPL_PB3MFP_Msk);    SYS->GPB_MFPL |= (SYS_GPB_MFPL_PB0MFP_EADC_CH0 | SYS_GPB_MFPL_PB1MFP_EADC_CH1 |                      SYS_GPB_MFPL_PB2MFP_EADC_CH2 | SYS_GPB_MFPL_PB3MFP_EADC_CH3);    /* Disable the GPB0 - GPB3 digital input path to avoid the leakage current. */    GPIO_DISABLE_DIGITAL_PATH(PB, 0xF);}

/*---------------------------------------------------------------------------------------------------------*/void SysInit(void){    /* Unlock protected registers */    SYS_UnlockReg();    /* Set HCLK source form HXT and HCLK source divide 1  */    CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_HXT,CLK_HCLK_CLK_DIVIDER(1));    /* Enable external 12MHz HXT, 32KHz LXT and HIRC */    CLK_EnableXtalRC(CLK_PWRCTL_HXT_EN_Msk | CLK_PWRCTL_LXT_EN_Msk | CLK_PWRCTL_HIRC_EN_Msk);    /* Waiting for clock ready */    CLK_WaitClockReady(CLK_CLKSTATUS_HXT_STB_Msk | CLK_CLKSTATUS_LXT_STB_Msk | CLK_CLKSTATUS_HIRC_STB_Msk);#if 1    SYS->PB_H_MFP &= ~( SYS_PB_H_MFP_PB14_MFP_Msk | SYS_PB_H_MFP_PB13_MFP_Msk);    SYS->PB_H_MFP |= (SYS_PB_H_MFP_PB14_MFP_UART0_TX | SYS_PB_H_MFP_PB13_MFP_UART0_RX );    UART0->BAUD = 0x67;              /* Baud Rate:115200  OSC:12MHz */    //UART0->BAUD = 0x60;            /* Baud Rate:115200  OSC:11.0592 MHz */    UART0->TLCTL = (UART0->TLCTL & ~0x3) | 0x3; /* character len is 8 bits */    UART0->TLCTL |= (1<<2);#endif    /*  Set HCLK frequency 32MHz */    CLK_SetCoreClock(32000000);    /* Enable IP clock */    CLK_EnableModuleClock(UART0_MODULE);    /* Enable PWM clock */    CLK_EnableModuleClock(PWM0_CH01_MODULE);    CLK_EnableModuleClock(PWM0_CH23_MODULE);    /* Select IP clock source */    CLK_SetModuleClock(UART0_MODULE,CLK_CLKSEL1_UART_S_HIRC,CLK_UART_CLK_DIVIDER(1));    /* Set HCLK as PWM clock source */    CLK_SetModuleClock(PWM0_CH01_MODULE, CLK_CLKSEL1_PWM0_CH01_S_HCLK, 0);    CLK_SetModuleClock(PWM0_CH23_MODULE, CLK_CLKSEL1_PWM0_CH23_S_HCLK, 0);    /*---------------------------------------------------------------------------------------------------------*/    /* Init I/O Multi-function                                                                                 */    /*---------------------------------------------------------------------------------------------------------*/    /* Set PA multi-function pins for UART0 RXD and TXD */    SYS->PB_L_MFP &= ~( SYS_PB_L_MFP_PB0_MFP_Msk | SYS_PB_L_MFP_PB1_MFP_Msk);    SYS->PB_L_MFP |= (SYS_PB_L_MFP_PB0_MFP_UART0_TX | SYS_PB_L_MFP_PB1_MFP_UART0_RX );    /* Set PB multi-function pins for Clock Output */    SYS->PB_H_MFP = ( SYS->PB_H_MFP & ~SYS_PB_H_MFP_PB12_MFP_Msk ) |  SYS_PB_H_MFP_PB12_MFP_CKO0;    /* Set PB and PE multi-function pins for PWM */    SYS->PB_H_MFP = (SYS->PB_H_MFP & ~(SYS_PB_H_MFP_PB8_MFP_Msk | SYS_PB_H_MFP_PB9_MFP_Msk)) | SYS_PB_H_MFP_PB8_MFP_PWM0_CH0 | SYS_PB_H_MFP_PB9_MFP_PWM0_CH1;    SYS->PE_H_MFP = (SYS->PE_H_MFP & ~(SYS_PE_H_MFP_PE8_MFP_Msk | SYS_PE_H_MFP_PE9_MFP_Msk)) | SYS_PE_H_MFP_PE8_MFP_PWM0_CH2 | SYS_PE_H_MFP_PE9_MFP_PWM0_CH3;    /* Lock protected registers */    SYS_LockReg();}

void SYS_PLL_Test(void){    int32_t  i;    /*---------------------------------------------------------------------------------------------------------*/    /* PLL clock configuration test                                                                             */    /*---------------------------------------------------------------------------------------------------------*/    printf("/n-------------------------[ Test PLL ]-----------------------------/n");         for(i = 0; i < sizeof(g_au32PllSetting) / sizeof(g_au32PllSetting[0]) ; i++) {        /* Switch HCLK clock source to HXT and HCLK source divide 1 */        CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_HXT, CLK_CLKDIV_HCLK(1));        /* Set PLL to power down mode and PLL_STB bit in CLKSTATUS register will be cleared by hardware. */        CLK_DisablePLL();        /* Set PLL frequency */        CLK->PLLCON = g_au32PllSetting[i];        /* Waiting for PLL clock ready */        CLK_WaitClockReady(CLK_CLKSTATUS_PLL_STB_Msk);        /* Switch HCLK clock source to PLL */        CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_PLL, CLK_CLKDIV_HCLK(1));        printf("  Change system clock to %d Hz ...................... ", SystemCoreClock);        /* Output selected clock to CKO, CKO Clock = HCLK / 2^(1 + 1) */        CLK_EnableCKO(CLK_CLKSEL2_FRQDIV_S_HCLK, 1, 0);        /* The delay loop is used to check if the CPU speed is increasing */        Delay(0x400000);        if(pi()) {            printf("[FAIL]/n");        } else {            printf("[OK]/n");        }        /* Disable CKO clock */        CLK_DisableCKO();    }}

/*---------------------------------------------------------------------------------------------------------*/void SysInit(void){    /* Unlock protected registers */    SYS_UnlockReg();    /* Set HCLK source form HXT and HCLK source divide 1  */    CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_HXT,CLK_HCLK_CLK_DIVIDER(1));    /* Enable external 12MHz HXT, 32KHz LXT and HIRC */    CLK_EnableXtalRC(CLK_PWRCTL_HXT_EN_Msk | CLK_PWRCTL_LXT_EN_Msk | CLK_PWRCTL_HIRC_EN_Msk);    /* Waiting for clock ready */    CLK_WaitClockReady(CLK_CLKSTATUS_HXT_STB_Msk | CLK_CLKSTATUS_LXT_STB_Msk | CLK_CLKSTATUS_HIRC_STB_Msk);#if 1    SYS->PB_H_MFP &= ~( SYS_PB_H_MFP_PB14_MFP_Msk | SYS_PB_H_MFP_PB13_MFP_Msk);    SYS->PB_H_MFP |= (SYS_PB_H_MFP_PB14_MFP_UART0_TX | SYS_PB_H_MFP_PB13_MFP_UART0_RX );    UART0->BAUD = 0x67;              /* Baud Rate:115200  OSC:12MHz */    //UART0->BAUD = 0x60;            /* Baud Rate:115200  OSC:11.0592 MHz */    UART0->TLCTL = (UART0->TLCTL & ~0x3) | 0x3; /* character len is 8 bits */    UART0->TLCTL |= (1<<2);#endif    /*  Set HCLK frequency 32MHz */    CLK_SetCoreClock(32000000);    /* Enable IP clock */    CLK_EnableModuleClock(UART0_MODULE);    /* Select IP clock source */    CLK_SetModuleClock(UART0_MODULE,CLK_CLKSEL1_UART_S_HIRC,CLK_UART_CLK_DIVIDER(1));    /*---------------------------------------------------------------------------------------------------------*/    /* Init I/O Multi-function                                                                                 */    /*---------------------------------------------------------------------------------------------------------*/    /* Set PA multi-function pins for UART0 RXD and TXD */    SYS->PB_L_MFP &= ~( SYS_PB_L_MFP_PB0_MFP_Msk | SYS_PB_L_MFP_PB1_MFP_Msk);    SYS->PB_L_MFP |= (SYS_PB_L_MFP_PB0_MFP_UART0_TX | SYS_PB_L_MFP_PB1_MFP_UART0_RX );    /* Set PB multi-function pins for Clock Output */    SYS->PB_H_MFP = ( SYS->PB_H_MFP & ~SYS_PB_H_MFP_PB12_MFP_Msk ) |  SYS_PB_H_MFP_PB12_MFP_CKO0;    /* Set PA multi-function pins for ADC */    SYS->PA_L_MFP &= ~(SYS_PA_L_MFP_PA0_MFP_Msk | SYS_PA_L_MFP_PA1_MFP_Msk | SYS_PA_L_MFP_PA2_MFP_Msk);    SYS->PA_L_MFP |= SYS_PA_L_MFP_PA0_MFP_ADC_CH0 | SYS_PA_L_MFP_PA1_MFP_ADC_CH1 | SYS_PA_L_MFP_PA2_MFP_ADC_CH2;    /* Disable digital input path */    PA->OFFD = PA->OFFD | ((ADC_CH_0_MASK | ADC_CH_1_MASK | ADC_CH_2_MASK)<< 16);    /* Enable ADC clock */    CLK_EnableModuleClock(ADC_MODULE);    /* Lock protected registers */    SYS_LockReg();}

/**  * @brief  This function set HCLK frequency. The frequency unit is Hz. The range of u32Hclk is 16 ~ 32 MHz  * @param  u32Hclk is HCLK frequency  * @return None  */uint32_t CLK_SetCoreClock(uint32_t u32Hclk){    if(CLK->PWRCTL & CLK_PWRCTL_HXT_EN) {        CLK_EnablePLL( CLK_PLLCTL_PLL_SRC_HXT,u32Hclk);    } else {        CLK_EnablePLL( CLK_PLLCTL_PLL_SRC_HIRC,u32Hclk);    }    CLK_WaitClockReady(CLK_CLKSTATUS_PLL_STB_Msk);    CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_PLL,CLK_HCLK_CLK_DIVIDER(1));    return SystemCoreClock;}

void SYS_Init(void){    /*---------------------------------------------------------------------------------------------------------*/    /* Init System Clock                                                                                       */    /*---------------------------------------------------------------------------------------------------------*/    /* Unlock protected registers */    SYS_UnlockReg();    /* Enable HIRC clock (Internal RC 22.1184MHz) */    CLK_EnableXtalRC(CLK_PWRCTL_HIRCEN_Msk);    /* Wait for HIRC clock ready */    CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);    /* Select HCLK clock source as HIRC and and HCLK source divider as 1 */    CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HIRC, CLK_CLKDIV_HCLK(1));    /* Set P5 multi-function pins for crystal output/input */    SYS->P5_MFP &= ~(SYS_MFP_P50_Msk | SYS_MFP_P51_Msk);    SYS->P5_MFP |= (SYS_MFP_P50_XT1_IN | SYS_MFP_P51_XT1_OUT);    /* Enable HXT clock (external XTAL 12MHz) */    CLK_EnableXtalRC(CLK_PWRCTL_XTLEN_HXT);    /* Wait for HXT clock ready */    CLK_WaitClockReady(CLK_STATUS_XTLSTB_Msk);    /* Set core clock as PLL_CLOCK from PLL */    CLK_SetCoreClock(PLL_CLOCK);    /* Enable UART module clock */    CLK_EnableModuleClock(UART0_MODULE);    /* Select UART module clock source as HXT and UART module clock divider as 1 */    CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UARTSEL_XTAL, CLK_CLKDIV_UART(1));    /* Lock protected registers */    SYS_LockReg();    /*---------------------------------------------------------------------------------------------------------*/    /* Init I/O Multi-function                                                                                 */    /*---------------------------------------------------------------------------------------------------------*/    /* Set P0 multi-function pins for UART RXD and TXD */    SYS->P1_MFP &= ~(SYS_MFP_P12_Msk | SYS_MFP_P13_Msk);    SYS->P1_MFP |= (SYS_MFP_P12_UART0_RXD | SYS_MFP_P13_UART0_TXD);    //SYS->P0_MFP &= ~(SYS_MFP_P01_Msk | SYS_MFP_P00_Msk);    //SYS->P0_MFP |= (SYS_MFP_P01_UART0_RXD | SYS_MFP_P00_UART0_TXD);    /* Set P3 multi-function pins for Clock Output */    SYS->P3_MFP = SYS_MFP_P36_CLKO;}

/*---------------------------------------------------------------------------------------------------------*/void SYS_Init(void){    /* Unlock protected registers */    SYS_UnlockReg();    /* Set HCLK source form HXT and HCLK source divide 1  */    CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_HXT,CLK_HCLK_CLK_DIVIDER(1));    /* Enable external 12MHz HXT, 32KHz LXT and HIRC */    CLK_EnableXtalRC(CLK_PWRCTL_HXT_EN_Msk | CLK_PWRCTL_LXT_EN_Msk | CLK_PWRCTL_HIRC_EN_Msk);    /* Waiting for clock ready */    CLK_WaitClockReady(CLK_CLKSTATUS_HXT_STB_Msk | CLK_CLKSTATUS_LXT_STB_Msk | CLK_CLKSTATUS_HIRC_STB_Msk);    /*  Set HCLK frequency 32MHz */    CLK_SetCoreClock(32000000);    CLK->AHBCLK |= CLK_AHBCLK_DMA_EN_Msk;    /* Enable IP clock */    CLK_EnableModuleClock(UART0_MODULE);    /* Enable ADC clock */    CLK_EnableModuleClock(ADC_MODULE);    /* Select IP clock source */    CLK_SetModuleClock(UART0_MODULE,CLK_CLKSEL1_UART_S_HXT,CLK_UART_CLK_DIVIDER(1));    /*---------------------------------------------------------------------------------------------------------*/    /* Init I/O Multi-function                                                                                 */    /*---------------------------------------------------------------------------------------------------------*/    /* Set PA multi-function pins for UART0 RXD and TXD */    SYS->PB_L_MFP &= ~( SYS_PB_L_MFP_PB0_MFP_Msk | SYS_PB_L_MFP_PB1_MFP_Msk);    SYS->PB_L_MFP |= (SYS_PB_L_MFP_PB0_MFP_UART0_RX | SYS_PB_L_MFP_PB1_MFP_UART0_TX );    /* Set PB multi-function pins for Clock Output */    SYS->PB_H_MFP = ( SYS->PB_H_MFP & ~SYS_PB_H_MFP_PB12_MFP_Msk ) |  SYS_PB_H_MFP_PB12_MFP_CKO;    /* Set PA.0,PA.1,PA.2,PA.3 multi-function pin for ADC channel 0,1,2,3 */    SYS->PA_L_MFP = (SYS->PA_L_MFP & ~SYS_PA_L_MFP_PA0_MFP_Msk) | SYS_PA_L_MFP_PA0_MFP_ADC_CH0;    SYS->PA_L_MFP = (SYS->PA_L_MFP & ~SYS_PA_L_MFP_PA1_MFP_Msk) | SYS_PA_L_MFP_PA1_MFP_ADC_CH1;    SYS->PA_L_MFP = (SYS->PA_L_MFP & ~SYS_PA_L_MFP_PA2_MFP_Msk) | SYS_PA_L_MFP_PA2_MFP_ADC_CH2;    SYS->PA_L_MFP = (SYS->PA_L_MFP & ~SYS_PA_L_MFP_PA3_MFP_Msk) | SYS_PA_L_MFP_PA3_MFP_ADC_CH3;    /* Disable PA.0 digital input path */    PA->OFFD |= ((1 << 0) << GP_OFFD_OFFD_Pos);    /* Lock protected registers */    SYS_LockReg();}

/** * This function will initial Clock tree. */void clock_init(void){    /*---------------------------------------------------------------------------------------------------------*/    /* Init System Clock                                                                                       */    /*---------------------------------------------------------------------------------------------------------*/    /* Unlock protected registers */    SYS_UnlockReg();    /* Enable External XTAL (4~24 MHz) */    CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk);    /* Waiting for 12MHz clock ready */    CLK_WaitClockReady( CLK_STATUS_HXTSTB_Msk);    /* Switch HCLK clock source to HXT */    CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HXT,CLK_CLKDIV0_HCLK(1));    /* Set PLL to power down mode and PLL_STB bit in CLKSTATUS register will be cleared by hardware.*/    CLK->PLLCTL |= CLK_PLLCTL_PD_Msk;    /* Set PLL frequency */    CLK->PLLCTL = CLK_PLLCTL_84MHz_HXT;    /* Waiting for clock ready */    CLK_WaitClockReady(CLK_STATUS_PLLSTB_Msk);    /* Switch HCLK clock source to PLL */    CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_PLL,CLK_CLKDIV0_HCLK(1));    /* Update System Core Clock */    /* User can use SystemCoreClockUpdate() to calculate SystemCoreClock. */    SystemCoreClockUpdate();    /* Lock protected registers */    SYS_LockReg();}

void SysInit(void){    /*---------------------------------------------------------------------------------------------------------*/    /* Init System Clock                                                                                       */    /*---------------------------------------------------------------------------------------------------------*/    /* Unlock protected registers */    SYS_UnlockReg();    /* Enable External XTAL (4~24 MHz) */    CLK_EnableXtalRC(CLK_PWRCTL_HXT_EN_Msk);    /* Waiting for 12MHz clock ready */    CLK_WaitClockReady( CLK_CLKSTATUS_HXT_STB_Msk);    /* Switch HCLK clock source to HXT */    CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_HXT,CLK_HCLK_CLK_DIVIDER(1));    /* Enable IP clock */    CLK_EnableModuleClock(UART0_MODULE);    CLK_EnableModuleClock(TMR0_MODULE);    CLK_EnableModuleClock(TMR1_MODULE);    /* Select IP clock source */    CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UART_S_HXT, CLK_UART_CLK_DIVIDER(1));    CLK_SetModuleClock(TMR0_MODULE, CLK_CLKSEL1_TMR0_S_HXT, CLK_TMR0_CLK_DIVIDER(1));    CLK_SetModuleClock(TMR0_MODULE, CLK_CLKSEL1_TMR1_S_HXT, CLK_TMR1_CLK_DIVIDER(1));    /* Update System Core Clock */    /* User can use SystemCoreClockUpdate() to calculate SystemCoreClock. */    SystemCoreClockUpdate();    /*---------------------------------------------------------------------------------------------------------*/    /* Init I/O Multi-function                                                                                 */    /*---------------------------------------------------------------------------------------------------------*/    /* Set GPB multi-function pins for UART0 RXD and TXD */    SYS->PB_L_MFP &= ~(SYS_PB_L_MFP_PB0_MFP_Msk | SYS_PB_L_MFP_PB1_MFP_Msk);    SYS->PB_L_MFP |= (SYS_PB_L_MFP_PB0_MFP_UART0_TX | SYS_PB_L_MFP_PB1_MFP_UART0_RX);    /* Set Timer0 event counting/toggle out pin */    SYS->PB_H_MFP &= ~SYS_PB_H_MFP_PB8_MFP_Msk;    SYS->PB_H_MFP |= SYS_PB_H_MFP_PB8_MFP_TMR0_EXT;    /* Lock protected registers */    SYS_LockReg();}

void SYS_Init(void){    /*---------------------------------------------------------------------------------------------------------*/    /* Init System Clock                                                                                       */    /*---------------------------------------------------------------------------------------------------------*/    /* Enable Internal RC 22.1184MHz clock */    CLK_EnableXtalRC(CLK_PWRCON_OSC22M_EN_Msk);    /* Waiting for Internal RC clock ready */    CLK_WaitClockReady(CLK_CLKSTATUS_OSC22M_STB_Msk);    /* Switch HCLK clock source to Internal RC and HCLK source divide 1 */    CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_HIRC, CLK_CLKDIV_HCLK(1));    /* Enable external XTAL 12MHz clock */    CLK_EnableXtalRC(CLK_PWRCON_XTL12M_EN_Msk);    /* Waiting for external XTAL clock ready */    CLK_WaitClockReady(CLK_CLKSTATUS_XTL12M_STB_Msk);    /* Set core clock as PLL_CLOCK from PLL */    CLK_SetCoreClock(PLL_CLOCK);    /* Enable UART0 and UART1 module clock */    CLK_EnableModuleClock(UART0_MODULE);    CLK_EnableModuleClock(UART1_MODULE);    CLK_EnableModuleClock(TMR0_MODULE);    /* Select UART0 and UART1 module clock source */    CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UART_S_HXT, CLK_CLKDIV_UART(1));    CLK_SetModuleClock(UART1_MODULE, CLK_CLKSEL1_UART_S_HXT, CLK_CLKDIV_UART(1));    CLK_SetModuleClock(TMR0_MODULE, CLK_CLKSEL1_TMR0_S_HXT, 0);	    /*---------------------------------------------------------------------------------------------------------*/    /* Init I/O Multi-function                                                                                 */    /*---------------------------------------------------------------------------------------------------------*/    /* Set P3 multi-function pins for UART0 RXD and TXD */    SYS->P3_MFP &= ~(SYS_MFP_P30_Msk | SYS_MFP_P31_Msk);    SYS->P3_MFP |= (SYS_MFP_P30_RXD0 | SYS_MFP_P31_TXD0);				/* Set P0 multi-function pins for UART1 RXD and TXD */    SYS->P0_MFP &= ~(SYS_MFP_P00_Msk | SYS_MFP_P01_Msk);    SYS->P0_MFP |= (SYS_MFP_P00_TXD1 | SYS_MFP_P01_RXD1);}

/**  * @brief  This function set HCLK frequency. The frequency unit is Hz. The range of u32Hclk is 16 ~ 32 MHz  * @param  u32Hclk is HCLK frequency  * @return HCLK frequency  */uint32_t CLK_SetCoreClock(uint32_t u32Hclk){    if(u32Hclk > FREQ_50MHZ)        u32Hclk = FREQ_50MHZ;    else if(u32Hclk < FREQ_25MHZ)        u32Hclk = FREQ_25MHZ;    if(CLK->PWRCON & CLK_PWRCON_XTL12M_EN_Msk)        u32Hclk = CLK_EnablePLL(CLK_PLLCON_PLL_SRC_HXT, u32Hclk);    else        u32Hclk = CLK_EnablePLL(CLK_PLLCON_PLL_SRC_HIRC, u32Hclk);    CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_PLL, CLK_CLKDIV_HCLK(1));    return u32Hclk;}