自学教程：C++ CLK_SetModuleClock函数代码示例

/*--------------------------------------------------------------------------*/void SYS_Init(void){    /* Unlock protected registers */    SYS_UnlockReg();    /* Enable external 12MHz HXT */    CLK_EnableXtalRC(CLK_PWRCTL_HXT_EN_Msk);    CLK_EnablePLL(CLK_PLLCTL_PLL_SRC_HXT, 96000000);    /* Waiting for clock ready */    CLK_WaitClockReady(CLK_CLKSTATUS_HXT_STB_Msk | CLK_CLKSTATUS_PLL_STB_Msk);    CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_PLL, CLK_HCLK_CLK_DIVIDER(3));    /* Select IP clock source */    CLK_SetModuleClock(USBD_MODULE, 0, CLK_USB_CLK_DIVIDER(2));    /* Enable IP clock */    CLK_EnableModuleClock(USBD_MODULE);    /* Select IP clock source */    CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UART_S_HXT, CLK_UART_CLK_DIVIDER(1));    /* Enable IP clock */    CLK_EnableModuleClock(UART0_MODULE);    /*---------------------------------------------------------------------------------------------------------*/    /* Init I/O Multi-function                                                                                 */    /*---------------------------------------------------------------------------------------------------------*/    /* Set PA multi-function pins for UART0 RXD and TXD */    SYS->PA_H_MFP &= ~( SYS_PA_H_MFP_PA15_MFP_Msk | SYS_PA_H_MFP_PA14_MFP_Msk);    SYS->PA_H_MFP |= (SYS_PA_H_MFP_PA15_MFP_UART0_TX|SYS_PA_H_MFP_PA14_MFP_UART0_RX);    /* Lock protected registers */    SYS_LockReg();}

void SYS_Init(void){    /*---------------------------------------------------------------------------------------------------------*/    /* Init System Clock                                                                                       */    /*---------------------------------------------------------------------------------------------------------*/    /* Unlock protected registers */    SYS_UnlockReg();    /* Enable External XTAL (4~24 MHz) */    CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk);    /* Waiting for 12MHz clock ready */    CLK_WaitClockReady( CLK_STATUS_HXTSTB_Msk);    /* Switch HCLK clock source to HXT */    CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HXT,CLK_CLKDIV0_HCLK(1));    /* Set PLL to power down mode and PLL_STB bit in CLKSTATUS register will be cleared by hardware.*/    CLK->PLLCTL |= CLK_PLLCTL_PD_Msk;    /* Set PLL frequency */    CLK->PLLCTL = CLK_PLLCTL_84MHz_HXT;    /* Waiting for clock ready */    CLK_WaitClockReady(CLK_STATUS_PLLSTB_Msk);    /* Switch HCLK clock source to PLL */    CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_PLL,CLK_CLKDIV0_HCLK(1));    /* Enable IP clock */    CLK_EnableModuleClock(UART0_MODULE);    CLK_EnableModuleClock(TMR0_MODULE);    CLK_EnableModuleClock(SPI0_MODULE);    CLK_EnableModuleClock(SPI1_MODULE);    /* Select IP clock source */    CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UARTSEL_HXT, CLK_CLKDIV0_UART(1));    CLK_SetModuleClock(TMR0_MODULE, CLK_CLKSEL1_TMR0SEL_HXT, 0);    /* Update System Core Clock */    /* User can use SystemCoreClockUpdate() to calculate SystemCoreClock. */    SystemCoreClockUpdate();    /*---------------------------------------------------------------------------------------------------------*/    /* Init I/O Multi-function                                                                                 */    /*---------------------------------------------------------------------------------------------------------*/    /* Set GPG multi-function pins for UART0 RXD and TXD */    SYS->GPG_MFPL = SYS_GPG_MFPL_PG1MFP_UART0_RXD | SYS_GPG_MFPL_PG2MFP_UART0_TXD ;    /* SPI0: GPE4=SS0, GPE3=MOSI0, GPE2=MISO0, GPE5=CLK */    SYS->GPE_MFPL = (SYS_GPE_MFPL_PE2MFP_SPI0_MISO0 | SYS_GPE_MFPL_PE3MFP_SPI0_MOSI0 | SYS_GPE_MFPL_PE4MFP_SPI0_SS0 | SYS_GPE_MFPL_PE5MFP_SPI0_CLK);    /* SPI1: GPC12=SS0, GPC15=MOSI0, GPD0=MISO0, GPD1=CLK */    SYS->GPC_MFPH |= (SYS_GPC_MFPH_PC12MFP_SPI1_SS0 | SYS_GPC_MFPH_PC15MFP_SPI1_MOSI0);    SYS->GPD_MFPL = (SYS_GPD_MFPL_PD0MFP_SPI1_MISO0 | SYS_GPD_MFPL_PD1MFP_SPI1_CLK);    /* Lock protected registers */    SYS_LockReg();}

void SYS_Init(void){    /*---------------------------------------------------------------------------------------------------------*/    /* Init System Clock                                                                                       */    /*---------------------------------------------------------------------------------------------------------*/    /* Enable Internal RC clock */    CLK_EnableXtalRC(CLK_PWRCON_OSC22M_EN_Msk);    /* Waiting for IRC22M clock ready */    CLK_WaitClockReady(CLK_CLKSTATUS_OSC22M_STB_Msk);    /* Switch HCLK clock source to Internal RC and HCLK source divide 1 */    CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_HIRC, CLK_CLKDIV_HCLK(1));    /* Enable external 12MHz XTAL, internal 22.1184MHz */    CLK_EnableXtalRC(CLK_PWRCON_XTL12M_EN_Msk | CLK_PWRCON_OSC22M_EN_Msk);    /* Enable PLL and Set PLL frequency */    CLK_SetCoreClock(PLLCON_SETTING);    /* Waiting for clock ready */    CLK_WaitClockReady(CLK_CLKSTATUS_PLL_STB_Msk | CLK_CLKSTATUS_XTL12M_STB_Msk | CLK_CLKSTATUS_OSC22M_STB_Msk);    /* Switch HCLK clock source to PLL, STCLK to HCLK/2 */    CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_PLL, CLK_CLKDIV_HCLK(2));    /* Enable UART module clock */    CLK_EnableModuleClock(UART0_MODULE);    /* Enable PWM module clock */    CLK_EnableModuleClock(PWM01_MODULE);    CLK_EnableModuleClock(PWM23_MODULE);    /* Select UART module clock source */    CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UART_S_HXT, CLK_CLKDIV_UART(1));    /* Select PWM module clock source */    CLK_SetModuleClock(PWM01_MODULE, CLK_CLKSEL1_PWM01_S_HXT, 0);    CLK_SetModuleClock(PWM23_MODULE, CLK_CLKSEL1_PWM23_S_HXT, 0);    /* Reset PWMA channel0~channel3 */    SYS_ResetModule(PWM03_RST);    /* Update System Core Clock */    /* User can use SystemCoreClockUpdate() to calculate PllClock, SystemCoreClock and CycylesPerUs automatically. */    //SystemCoreClockUpdate();    PllClock        = PLL_CLOCK;            // PLL    SystemCoreClock = PLL_CLOCK / 1;        // HCLK    CyclesPerUs     = PLL_CLOCK / 1000000;  // For SYS_SysTickDelay()    /*---------------------------------------------------------------------------------------------------------*/    /* Init I/O Multi-function                                                                                 */    /*---------------------------------------------------------------------------------------------------------*/    /* Set P3 multi-function pins for UART0 RXD and TXD  */    SYS->P3_MFP = SYS_MFP_P30_RXD0 | SYS_MFP_P31_TXD0;    /* Set P2 multi-function pins for PWMA Channel0~3 */    SYS->P2_MFP = SYS_MFP_P20_PWM0 | SYS_MFP_P21_PWM1 | SYS_MFP_P22_PWM2 | SYS_MFP_P23_PWM3;}

void SYS_Init(void){    /*---------------------------------------------------------------------------------------------------------*/    /* Init System Clock                                                                                       */    /*---------------------------------------------------------------------------------------------------------*/    /* Enable Internal RC 22.1184MHz clock */    CLK_EnableXtalRC(CLK_PWRCON_OSC22M_EN_Msk);    /* Waiting for Internal RC clock ready */    CLK_WaitClockReady(CLK_CLKSTATUS_OSC22M_STB_Msk);    /* Switch HCLK clock source to Internal RC and HCLK source divide 1 */    CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_HIRC, CLK_CLKDIV_HCLK(1));    /* Enable external XTAL 12MHz clock */    CLK_EnableXtalRC(CLK_PWRCON_XTL12M_EN_Msk);    /* Waiting for clock ready */    CLK_WaitClockReady(CLK_CLKSTATUS_XTL12M_STB_Msk);    /* Set core clock as PLL_CLOCK from PLL */    CLK_SetCoreClock(PLL_CLOCK);        /* Enable UART module clock */    CLK_EnableModuleClock(UART0_MODULE);            /* Select UART module clock source */    CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UART_S_HXT, CLK_CLKDIV_UART(1));    /* Enable Timer 0~3 module clock */    CLK_EnableModuleClock(TMR0_MODULE);        CLK_EnableModuleClock(TMR2_MODULE);        CLK_EnableModuleClock(TMR3_MODULE);        /* Select Timer 0~3 module clock source */    CLK_SetModuleClock(TMR0_MODULE, CLK_CLKSEL1_TMR0_S_HXT, NULL);    CLK_SetModuleClock(TMR2_MODULE, CLK_CLKSEL1_TMR2_S_HCLK, NULL);    CLK_SetModuleClock(TMR3_MODULE, CLK_CLKSEL1_TMR3_S_HXT, NULL);    /*---------------------------------------------------------------------------------------------------------*/    /* Init I/O Multi-function                                                                                 */    /*---------------------------------------------------------------------------------------------------------*/    /* Set PB multi-function pins for UART0 RXD, TXD */    SYS->GPB_MFP &= ~(SYS_GPB_MFP_PB0_Msk | SYS_GPB_MFP_PB1_Msk);    SYS->GPB_MFP |= (SYS_GPB_MFP_PB0_UART0_RXD | SYS_GPB_MFP_PB1_UART0_TXD);    /* Set PB multi-function pins for TM0, TM2, TM3 and TM2_EXT */    SYS->GPB_MFP &= ~(SYS_GPB_MFP_PB8_Msk | SYS_GPB_MFP_PB10_Msk |                       SYS_GPB_MFP_PB11_Msk | SYS_GPB_MFP_PB2_Msk);    SYS->GPB_MFP |= (SYS_GPB_MFP_PB8_TM0 | SYS_GPB_MFP_PB10_TM2 |                      SYS_GPB_MFP_PB11_TM3 | SYS_GPB_MFP_PB2_TM2_EXT);    SYS->ALT_MFP  &= ~( SYS_ALT_MFP_PB8_Msk | SYS_ALT_MFP_PB10_Msk | SYS_ALT_MFP_PB11_Msk |                        SYS_ALT_MFP_PB2_Msk);    SYS->ALT_MFP  |= (SYS_ALT_MFP_PB8_TM0 | SYS_ALT_MFP_PB10_TM2 |SYS_ALT_MFP_PB11_TM3 |                      SYS_ALT_MFP_PB2_TM2_EXT);    SYS->ALT_MFP2 &= ~SYS_ALT_MFP2_PB2_TM2_Msk;    SYS->ALT_MFP2 |= SYS_ALT_MFP2_PB2_TM2_EXT;}

/** * Initializes the system. * System control registers must be unlocked. */void SYS_Init() {	// TODO: why is SYS_UnlockReg() needed? Should be already unlocked.	SYS_UnlockReg();	// HIRC clock (internal RC 22.1184MHz)	CLK_EnableXtalRC(CLK_PWRCTL_HIRCEN_Msk);	CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);		// HCLK clock source: HIRC, HCLK source divider: 1	CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HIRC, CLK_CLKDIV0_HCLK(1));		// HXT clock (external XTAL 12MHz)	CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk);	CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk);		// Enable 72MHz optimization	FMC_EnableFreqOptimizeMode(FMC_FTCTL_OPTIMIZE_72MHZ);		// Core clock: PLL	CLK_SetCoreClock(PLL_CLOCK);	CLK_WaitClockReady(CLK_STATUS_PLLSTB_Msk);		// SPI0 clock: PCLK0	CLK_SetModuleClock(SPI0_MODULE, CLK_CLKSEL2_SPI0SEL_PCLK0, 0);	CLK_EnableModuleClock(SPI0_MODULE);		// TMR0 clock: HXT	CLK_SetModuleClock(TMR0_MODULE, CLK_CLKSEL1_TMR0SEL_HXT, 0);	CLK_EnableModuleClock(TMR0_MODULE);	// USBD clock	CLK_SetModuleClock(USBD_MODULE, 0, CLK_CLKDIV0_USB(3));	CLK_EnableModuleClock(USBD_MODULE);		// Enable USB 3.3V LDO	SYS->USBPHY = SYS_USBPHY_LDO33EN_Msk;	// EADC clock: 72Mhz / 8	CLK_SetModuleClock(EADC_MODULE, 0, CLK_CLKDIV0_EADC(8));	CLK_EnableModuleClock(EADC_MODULE);		// Enable BOD (reset, 2.2V)	SYS_EnableBOD(SYS_BODCTL_BOD_RST_EN, SYS_BODCTL_BODVL_2_2V);		// Update system core clock	SystemCoreClockUpdate();	// Initialize dataflash	Dataflash_Init();	// Initialize I/O	Display_SetupSPI();	Button_Init();	ADC_Init();	// Initialize display	Display_Init();}

void SYS_Init(void){    /*---------------------------------------------------------------------------------------------------------*/    /* Init System Clock                                                                                       */    /*---------------------------------------------------------------------------------------------------------*/    /* Enable HIRC clock (Internal RC 22.1184MHz) */    CLK_EnableXtalRC(CLK_PWRCTL_HIRCEN_Msk);    /* Wait for HIRC clock ready */    CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);    /* Select HCLK clock source as HIRC and and HCLK source divider as 1 */    CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HIRC, CLK_CLKDIV0_HCLK(1));    /* Set PLL to Power-down mode and PLLSTB bit in CLK_STATUS register will be cleared by hardware.*/    CLK_DisablePLL();    /* Enable HXT clock (external XTAL 12MHz) */    CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk);    /* Wait for HXT clock ready */    CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk);    /* Set core clock as PLL_CLOCK from PLL */    CLK_SetCoreClock(PLL_CLOCK);    /* Enable UART module clock */    CLK_EnableModuleClock(UART0_MODULE);    /* Select UART module clock source as HXT and UART module clock divider as 1 */    CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UARTSEL_HXT, CLK_CLKDIV0_UART(1));    /* Enable EADC module clock */    CLK_EnableModuleClock(EADC_MODULE);    /* EADC clock source is 72MHz, set divider to 8, ADC clock is 72/8 MHz */    CLK_SetModuleClock(EADC_MODULE, 0, CLK_CLKDIV0_EADC(8));    /*---------------------------------------------------------------------------------------------------------*/    /* Init I/O Multi-function                                                                                 */    /*---------------------------------------------------------------------------------------------------------*/    /* Set PD multi-function pins for UART0 RXD and TXD */    SYS->GPD_MFPL &= ~(SYS_GPD_MFPL_PD0MFP_Msk | SYS_GPD_MFPL_PD1MFP_Msk);    SYS->GPD_MFPL |= (SYS_GPD_MFPL_PD0MFP_UART0_RXD | SYS_GPD_MFPL_PD1MFP_UART0_TXD);    /* Configure the GPB0 - GPB3 ADC analog input pins.  */    SYS->GPB_MFPL &= ~(SYS_GPB_MFPL_PB0MFP_Msk | SYS_GPB_MFPL_PB1MFP_Msk |                       SYS_GPB_MFPL_PB2MFP_Msk | SYS_GPB_MFPL_PB3MFP_Msk);    SYS->GPB_MFPL |= (SYS_GPB_MFPL_PB0MFP_EADC_CH0 | SYS_GPB_MFPL_PB1MFP_EADC_CH1 |                      SYS_GPB_MFPL_PB2MFP_EADC_CH2 | SYS_GPB_MFPL_PB3MFP_EADC_CH3);    /* Disable the GPB0 - GPB3 digital input path to avoid the leakage current. */    GPIO_DISABLE_DIGITAL_PATH(PB, 0xF);}

/*---------------------------------------------------------------------------------------------------------*/void SysInit(void){    /* Unlock protected registers */    SYS_UnlockReg();    /* Set HCLK source form HXT and HCLK source divide 1  */    CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_HXT,CLK_HCLK_CLK_DIVIDER(1));    /* Enable external 12MHz HXT, 32KHz LXT and HIRC */    CLK_EnableXtalRC(CLK_PWRCTL_HXT_EN_Msk | CLK_PWRCTL_LXT_EN_Msk | CLK_PWRCTL_HIRC_EN_Msk);    /* Waiting for clock ready */    CLK_WaitClockReady(CLK_CLKSTATUS_HXT_STB_Msk | CLK_CLKSTATUS_LXT_STB_Msk | CLK_CLKSTATUS_HIRC_STB_Msk);#if 1    SYS->PB_H_MFP &= ~( SYS_PB_H_MFP_PB14_MFP_Msk | SYS_PB_H_MFP_PB13_MFP_Msk);    SYS->PB_H_MFP |= (SYS_PB_H_MFP_PB14_MFP_UART0_TX | SYS_PB_H_MFP_PB13_MFP_UART0_RX );    UART0->BAUD = 0x67;              /* Baud Rate:115200  OSC:12MHz */    //UART0->BAUD = 0x60;            /* Baud Rate:115200  OSC:11.0592 MHz */    UART0->TLCTL = (UART0->TLCTL & ~0x3) | 0x3; /* character len is 8 bits */    UART0->TLCTL |= (1<<2);#endif    /*  Set HCLK frequency 32MHz */    CLK_SetCoreClock(32000000);    /* Enable IP clock */    CLK_EnableModuleClock(UART0_MODULE);    /* Enable PWM clock */    CLK_EnableModuleClock(PWM0_CH01_MODULE);    CLK_EnableModuleClock(PWM0_CH23_MODULE);    /* Select IP clock source */    CLK_SetModuleClock(UART0_MODULE,CLK_CLKSEL1_UART_S_HIRC,CLK_UART_CLK_DIVIDER(1));    /* Set HCLK as PWM clock source */    CLK_SetModuleClock(PWM0_CH01_MODULE, CLK_CLKSEL1_PWM0_CH01_S_HCLK, 0);    CLK_SetModuleClock(PWM0_CH23_MODULE, CLK_CLKSEL1_PWM0_CH23_S_HCLK, 0);    /*---------------------------------------------------------------------------------------------------------*/    /* Init I/O Multi-function                                                                                 */    /*---------------------------------------------------------------------------------------------------------*/    /* Set PA multi-function pins for UART0 RXD and TXD */    SYS->PB_L_MFP &= ~( SYS_PB_L_MFP_PB0_MFP_Msk | SYS_PB_L_MFP_PB1_MFP_Msk);    SYS->PB_L_MFP |= (SYS_PB_L_MFP_PB0_MFP_UART0_TX | SYS_PB_L_MFP_PB1_MFP_UART0_RX );    /* Set PB multi-function pins for Clock Output */    SYS->PB_H_MFP = ( SYS->PB_H_MFP & ~SYS_PB_H_MFP_PB12_MFP_Msk ) |  SYS_PB_H_MFP_PB12_MFP_CKO0;    /* Set PB and PE multi-function pins for PWM */    SYS->PB_H_MFP = (SYS->PB_H_MFP & ~(SYS_PB_H_MFP_PB8_MFP_Msk | SYS_PB_H_MFP_PB9_MFP_Msk)) | SYS_PB_H_MFP_PB8_MFP_PWM0_CH0 | SYS_PB_H_MFP_PB9_MFP_PWM0_CH1;    SYS->PE_H_MFP = (SYS->PE_H_MFP & ~(SYS_PE_H_MFP_PE8_MFP_Msk | SYS_PE_H_MFP_PE9_MFP_Msk)) | SYS_PE_H_MFP_PE8_MFP_PWM0_CH2 | SYS_PE_H_MFP_PE9_MFP_PWM0_CH3;    /* Lock protected registers */    SYS_LockReg();}

void Motor_Init(void){	CLK_EnableModuleClock(PWMCH01_MODULE);	CLK_EnableModuleClock(PWMCH45_MODULE);	CLK_SetModuleClock(PWMCH01_MODULE, CLK_CLKSEL1_PWMCH01SEL_HCLK, 0);	CLK_SetModuleClock(PWMCH45_MODULE, CLK_CLKSEL2_PWMCH45SEL_HCLK, 0);	SYS->P1_MFP |= SYS_MFP_P12_PWM0_CH0 | SYS_MFP_P13_PWM0_CH1 | SYS_MFP_P14_PWM0_CH4;	SYS->P0_MFP |= SYS_MFP_P04_PWM0_CH5;		MotorPwmOutput(0,0,0,0);}

void lp_ticker_init(void){    if (lp_ticker_inited) {        return;    }    lp_ticker_inited = 1;    counter_major = 0;    cd_major_minor_clks = 0;    cd_minor_clks = 0;    wakeup_tick = (uint32_t) -1;    // Reset module    SYS_ResetModule(timer2_modinit.rsetidx);    SYS_ResetModule(timer3_modinit.rsetidx);    // Select IP clock source    CLK_SetModuleClock(timer2_modinit.clkidx, timer2_modinit.clksrc, timer2_modinit.clkdiv);    CLK_SetModuleClock(timer3_modinit.clkidx, timer3_modinit.clksrc, timer3_modinit.clkdiv);    // Enable IP clock    CLK_EnableModuleClock(timer2_modinit.clkidx);    CLK_EnableModuleClock(timer3_modinit.clkidx);    // Configure clock    uint32_t clk_timer2 = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(timer2_modinit.modname));    uint32_t prescale_timer2 = clk_timer2 / TMR2_CLK_PER_SEC - 1;    MBED_ASSERT((prescale_timer2 != (uint32_t) -1) && prescale_timer2 <= 127);    MBED_ASSERT((clk_timer2 % TMR2_CLK_PER_SEC) == 0);    uint32_t cmp_timer2 = TMR2_CLK_PER_TMR2_INT;    MBED_ASSERT(cmp_timer2 >= TMR_CMP_MIN && cmp_timer2 <= TMR_CMP_MAX);    // Continuous mode    // NOTE: TIMER_CTL_CNTDATEN_Msk exists in NUC472, but not in M451/M480. In M451/M480, TIMER_CNT is updated continuously by default.    ((TIMER_T *) NU_MODBASE(timer2_modinit.modname))->CTL = TIMER_PERIODIC_MODE | prescale_timer2/* | TIMER_CTL_CNTDATEN_Msk*/;    ((TIMER_T *) NU_MODBASE(timer2_modinit.modname))->CMP = cmp_timer2;    // Set vector    NVIC_SetVector(timer2_modinit.irq_n, (uint32_t) timer2_modinit.var);    NVIC_SetVector(timer3_modinit.irq_n, (uint32_t) timer3_modinit.var);    NVIC_EnableIRQ(timer2_modinit.irq_n);    NVIC_EnableIRQ(timer3_modinit.irq_n);    TIMER_EnableInt((TIMER_T *) NU_MODBASE(timer2_modinit.modname));    TIMER_EnableWakeup((TIMER_T *) NU_MODBASE(timer2_modinit.modname));    // NOTE: TIMER_Start() first and then lp_ticker_set_interrupt(); otherwise, we may get stuck in lp_ticker_read() because    //       timer is not running.    // Start timer    TIMER_Start((TIMER_T *) NU_MODBASE(timer2_modinit.modname));    // Schedule wakeup to match semantics of lp_ticker_get_compare_match()    lp_ticker_set_interrupt(wakeup_tick);}

void SYS_Init(void){    /*---------------------------------------------------------------------------------------------------------*/    /* Init System Clock                                                                                       */    /*---------------------------------------------------------------------------------------------------------*/    /* Unlock protected registers */    SYS_UnlockReg();    /* Set P5 multi-function pins for XTAL1 and XTAL2 */    SYS->P5_MFP &= ~(SYS_MFP_P50_Msk | SYS_MFP_P51_Msk);    SYS->P5_MFP |= (SYS_MFP_P50_XT1_IN | SYS_MFP_P51_XT1_OUT);    /* Enable external 12MHz XTAL (UART), HIRC */    CLK->PWRCTL = CLK_PWRCTL_XTL12M | CLK_PWRCTL_HIRCEN_Msk;    /* Waiting for clock ready */    CLK_WaitClockReady(CLK_STATUS_XTLSTB_Msk | CLK_STATUS_HIRCSTB_Msk);    /* Switch HCLK clock source to XTL */    CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_XTAL,CLK_CLKDIV_HCLK(1));    /* Enable IP clock */    CLK->APBCLK = CLK_APBCLK_UART0CKEN_Msk | CLK_APBCLK_ADCCKEN_Msk | CLK_APBCLK_PWMCH01CKEN_Msk;    /* Select UART clock source from external crystal */    CLK->CLKSEL1 = (CLK->CLKSEL1 & ~CLK_CLKSEL1_UARTSEL_Msk) | CLK_CLKSEL1_UARTSEL_XTAL;    /* Select ADC clock source from external crystal */    CLK->CLKSEL1 = (CLK->CLKSEL1 & ~CLK_CLKSEL1_ADCSEL_Msk) | CLK_CLKSEL1_ADCSEL_XTAL;    /* Select IP clock source */    CLK_SetModuleClock(UART0_MODULE,CLK_CLKSEL1_UARTSEL_XTAL,CLK_CLKDIV_UART(1));    CLK_SetModuleClock(ADC_MODULE,CLK_CLKSEL1_ADCSEL_XTAL,CLK_CLKDIV_ADC(6));    /* Update System Core Clock */    /* User can use SystemCoreClockUpdate() to calculate SystemCoreClock and CycylesPerUs automatically. */    SystemCoreClockUpdate();    /*---------------------------------------------------------------------------------------------------------*/    /* Init I/O Multi-function                                                                                 */    /*---------------------------------------------------------------------------------------------------------*/    /* Set P1 multi-function pins for UART RXD, TXD and ADC channel 5 input */    SYS->P1_MFP = SYS_MFP_P12_UART0_RXD | SYS_MFP_P13_UART0_TXD | SYS_MFP_P15_ADC_CH5;    /* Analog pin OFFD to prevent leakage */    P1->DINOFF |= (1 << 5) << GP_DINOFF_DINOFF0_Pos;    /* Set P2 multi-function pins for PWM Channel 0. */    SYS->P2_MFP = SYS_MFP_P22_PWM0_CH0;    /* Lock protected registers */    SYS_LockReg();}

void initialize(){    IO::pinMode(MUX_ADR0_PIN, OUTPUT);    IO::pinMode(MUX_ADR1_PIN, OUTPUT);    IO::pinMode(MUX_ADR2_PIN, OUTPUT);    IO::pinMode(V_IN_PIN, ANALOG_INPUT);    IO::pinMode(OUTPUT_VOLTAGE_MINUS_PIN, ANALOG_INPUT);    IO::pinMode(SMPS_CURRENT_PIN, ANALOG_INPUT);    IO::pinMode(OUTPUT_VOLTAGE_PLUS_PIN, ANALOG_INPUT);    IO::pinMode(DISCHARGE_CURRENT_PIN, ANALOG_INPUT);    IO::pinMode(MUX0_Z_D_PIN, ANALOG_INPUT_DISCHARGE);    IO::digitalWrite(MUX0_Z_D_PIN, 0);    //initialize internal temperature sensor    SYS->TEMPCR |= 1;    //initialize TIMER 1 (mux ADC capacitor discharge)    CLK_EnableModuleClock(TMR1_MODULE);    CLK_SetModuleClock(TMR1_MODULE,CLK_CLKSEL1_TMR1_S_HCLK,CLK_CLKDIV_UART(1));    //TODO: 50kHz ??    TIMER_Open(TIMER1, TIMER_ONESHOT_MODE, 1000000 / ADC_CAPACITOR_DISCHARGE_DELAY_US);    TIMER_EnableInt(TIMER1);    NVIC_EnableIRQ(TMR1_IRQn);    NVIC_SetPriority(TMR1_IRQn, ADC_C_DISCHARGE_IRQ_PRIORITY);    //initialize ADC    //init clock    CLK_EnableModuleClock(ADC_MODULE);    CLK_SetModuleClock(ADC_MODULE, CLK_CLKSEL1_ADC_S_HCLK, CLK_CLKDIV_ADC(CLK_GetHCLKFreq()/ADC_CLOCK_FREQUENCY));            //__HXT/ADC_CLOCK_FREQUENCY));    /* Set the ADC operation mode as burst, input mode as single-end and enable the analog input channel 2 */    ADC_Open(ADC, ADC_ADCR_DIFFEN_SINGLE_END, ADC_ADCR_ADMD_BURST, 0x1 << 2);    ADC_SET_DMOF(ADC, ADC_ADCR_DMOF_UNSIGNED_OUTPUT);    /* Power on ADC module */    ADC_POWER_ON(ADC);    /* clear the A/D interrupt flag for safe */    ADC_CLR_INT_FLAG(ADC, ADC_ADF_INT);    /* Enable the ADC interrupt */    ADC_EnableInt(ADC, ADC_ADF_INT);    NVIC_EnableIRQ(ADC_IRQn);    NVIC_SetPriority(ADC_IRQn, ADC_IRQ_PRIORITY);    current_input_ = 0;    startConversion();}

void lp_ticker_init(void){    if (lp_ticker_inited) {        return;    }    lp_ticker_inited = 1;        counter_major = 0;    cd_major_minor_ms = 0;    cd_minor_ms = 0;    wakeup_tick = TMR_CMP_MAX * MS_PER_TMR2_CLK / MS_PER_TICK;    // Reset module    SYS_ResetModule(timer2_modinit.rsetidx);    SYS_ResetModule(timer3_modinit.rsetidx);        // Select IP clock source    CLK_SetModuleClock(timer2_modinit.clkidx, timer2_modinit.clksrc, timer2_modinit.clkdiv);    CLK_SetModuleClock(timer3_modinit.clkidx, timer3_modinit.clksrc, timer3_modinit.clkdiv);    // Enable IP clock    CLK_EnableModuleClock(timer2_modinit.clkidx);    CLK_EnableModuleClock(timer3_modinit.clkidx);    // Configure clock    uint32_t clk_timer2 = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(timer2_modinit.modname));    uint32_t prescale_timer2 = clk_timer2 / TMR2_CLK_FREQ - 1;    MBED_ASSERT((prescale_timer2 != (uint32_t) -1) && prescale_timer2 <= 127);    uint32_t cmp_timer2 = MS_PER_TMR2_INT / MS_PER_TMR2_CLK;    MBED_ASSERT(cmp_timer2 >= TMR_CMP_MIN && cmp_timer2 <= TMR_CMP_MAX);    // Continuous mode    ((TIMER_T *) NU_MODBASE(timer2_modinit.modname))->CTL = TIMER_PERIODIC_MODE | prescale_timer2 | TIMER_CTL_CNTDATEN_Msk;    ((TIMER_T *) NU_MODBASE(timer2_modinit.modname))->CMP = cmp_timer2;        // Set vector    NVIC_SetVector(timer2_modinit.irq_n, (uint32_t) timer2_modinit.var);    NVIC_SetVector(timer3_modinit.irq_n, (uint32_t) timer3_modinit.var);        NVIC_EnableIRQ(timer2_modinit.irq_n);    NVIC_EnableIRQ(timer3_modinit.irq_n);        TIMER_EnableInt((TIMER_T *) NU_MODBASE(timer2_modinit.modname));    TIMER_EnableWakeup((TIMER_T *) NU_MODBASE(timer2_modinit.modname));        // Schedule wakeup to match semantics of lp_ticker_get_compare_match()    lp_ticker_set_interrupt(lp_ticker_read(), wakeup_tick);        // Start timer    TIMER_Start((TIMER_T *) NU_MODBASE(timer2_modinit.modname));}

void SysInit(void){    /*---------------------------------------------------------------------------------------------------------*/    /* Init System Clock                                                                                       */    /*---------------------------------------------------------------------------------------------------------*/    /* Unlock protected registers */    SYS_UnlockReg();    /* Enable External XTAL (4~24 MHz) */    CLK_EnableXtalRC(CLK_PWRCTL_HXT_EN_Msk);    /* Waiting for 12MHz clock ready */    CLK_WaitClockReady( CLK_CLKSTATUS_HXT_STB_Msk);    /* Switch HCLK clock source to HXT */    CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_HXT,CLK_HCLK_CLK_DIVIDER(1));    /* Enable IP clock */    CLK_EnableModuleClock(UART0_MODULE);    CLK_EnableModuleClock(TMR0_MODULE);    CLK_EnableModuleClock(TMR1_MODULE);    /* Select IP clock source */    CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UART_S_HXT, CLK_UART_CLK_DIVIDER(1));    CLK_SetModuleClock(TMR0_MODULE, CLK_CLKSEL1_TMR0_S_HXT, CLK_TMR0_CLK_DIVIDER(1));    CLK_SetModuleClock(TMR0_MODULE, CLK_CLKSEL1_TMR1_S_HXT, CLK_TMR1_CLK_DIVIDER(1));    /* Update System Core Clock */    /* User can use SystemCoreClockUpdate() to calculate SystemCoreClock. */    SystemCoreClockUpdate();    /*---------------------------------------------------------------------------------------------------------*/    /* Init I/O Multi-function                                                                                 */    /*---------------------------------------------------------------------------------------------------------*/    /* Set GPB multi-function pins for UART0 RXD and TXD */    SYS->PB_L_MFP &= ~(SYS_PB_L_MFP_PB0_MFP_Msk | SYS_PB_L_MFP_PB1_MFP_Msk);    SYS->PB_L_MFP |= (SYS_PB_L_MFP_PB0_MFP_UART0_TX | SYS_PB_L_MFP_PB1_MFP_UART0_RX);    /* Set Timer0 event counting/toggle out pin */    SYS->PB_H_MFP &= ~SYS_PB_H_MFP_PB8_MFP_Msk;    SYS->PB_H_MFP |= SYS_PB_H_MFP_PB8_MFP_TMR0_EXT;    /* Lock protected registers */    SYS_LockReg();}

void SYS_Init(void){    /*---------------------------------------------------------------------------------------------------------*/    /* Init System Clock                                                                                       */    /*---------------------------------------------------------------------------------------------------------*/    /* Enable Internal RC 22.1184MHz clock */    CLK_EnableXtalRC(CLK_PWRCON_OSC22M_EN_Msk);    /* Waiting for Internal RC clock ready */    CLK_WaitClockReady(CLK_CLKSTATUS_OSC22M_STB_Msk);    /* Switch HCLK clock source to Internal RC and HCLK source divide 1 */    CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_HIRC, CLK_CLKDIV_HCLK(1));    /* Enable external XTAL 12MHz clock */    CLK_EnableXtalRC(CLK_PWRCON_XTL12M_EN_Msk);    /* Waiting for external XTAL clock ready */    CLK_WaitClockReady(CLK_CLKSTATUS_XTL12M_STB_Msk);    /* Set core clock as PLL_CLOCK from PLL */    CLK_SetCoreClock(PLL_CLOCK);    /* Enable UART0 and UART1 module clock */    CLK_EnableModuleClock(UART0_MODULE);    CLK_EnableModuleClock(UART1_MODULE);    CLK_EnableModuleClock(TMR0_MODULE);    /* Select UART0 and UART1 module clock source */    CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UART_S_HXT, CLK_CLKDIV_UART(1));    CLK_SetModuleClock(UART1_MODULE, CLK_CLKSEL1_UART_S_HXT, CLK_CLKDIV_UART(1));    CLK_SetModuleClock(TMR0_MODULE, CLK_CLKSEL1_TMR0_S_HXT, 0);	    /*---------------------------------------------------------------------------------------------------------*/    /* Init I/O Multi-function                                                                                 */    /*---------------------------------------------------------------------------------------------------------*/    /* Set P3 multi-function pins for UART0 RXD and TXD */    SYS->P3_MFP &= ~(SYS_MFP_P30_Msk | SYS_MFP_P31_Msk);    SYS->P3_MFP |= (SYS_MFP_P30_RXD0 | SYS_MFP_P31_TXD0);				/* Set P0 multi-function pins for UART1 RXD and TXD */    SYS->P0_MFP &= ~(SYS_MFP_P00_Msk | SYS_MFP_P01_Msk);    SYS->P0_MFP |= (SYS_MFP_P00_TXD1 | SYS_MFP_P01_RXD1);}

// ---------------------------------------------------------------------------------------//  Gas ADC initialize setting//	Set PB2 as ADC converter//  Select APB0/8 as ADC module clock source  // --------------------------------------------------------------------------------------- void ID_Init(){	SYS_UnlockReg();	/* Enable EADC module clock */	CLK_EnableModuleClock(EADC_MODULE);		/* EADC clock source is 72MHz, set divider to 8, ADC clock is 72/8 MHz */	CLK_SetModuleClock(EADC_MODULE, 0, CLK_CLKDIV0_EADC(8));	SYS_LockReg();		/* Configure the GPB0 - GPB3 ADC analog input pins.  */	SYS->GPB_MFPL &= ~SYS_GPB_MFPL_PB0MFP_Msk;	SYS->GPB_MFPL |= SYS_GPB_MFPL_PB0MFP_EADC_CH0;		GPIO_DISABLE_DIGITAL_PATH(PB, BIT0);		/* Set the ADC internal sampling time, input mode as single-end and enable the A/D converter */	EADC_Open(EADC, EADC_CTL_DIFFEN_SINGLE_END);	EADC_SetInternalSampleTime(EADC, 6);	/* Configure the sample module 0 for analog input channel 1 and software trigger source.*/	EADC_ConfigSampleModule(EADC, 0, EADC_SOFTWARE_TRIGGER, 0);		/* Clear the A/D ADINT0 interrupt flag for safe */	EADC_CLR_INT_FLAG(EADC, 0x1);	/* Enable the sample module 0 interrupt.  */	EADC_ENABLE_INT(EADC, 0x1);//Enable sample module A/D ADINT0 interrupt.	EADC_ENABLE_SAMPLE_MODULE_INT(EADC, 0, 0x1);//Enable sample module 0 interrupt.}

void us_ticker_init(void){    if (ticker_inited) {        return;    }    ticker_inited = 1;    // Reset IP    SYS_ResetModule(TIMER_MODINIT.rsetidx);    // Select IP clock source    CLK_SetModuleClock(TIMER_MODINIT.clkidx, TIMER_MODINIT.clksrc, TIMER_MODINIT.clkdiv);    // Enable IP clock    CLK_EnableModuleClock(TIMER_MODINIT.clkidx);    // Timer for normal counter    uint32_t clk_timer = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));    uint32_t prescale_timer = clk_timer / NU_TMRCLK_PER_SEC - 1;    MBED_ASSERT((prescale_timer != (uint32_t) -1) && prescale_timer <= 127);    MBED_ASSERT((clk_timer % NU_TMRCLK_PER_SEC) == 0);    uint32_t cmp_timer = TMR_CMP_MAX;    MBED_ASSERT(cmp_timer >= TMR_CMP_MIN && cmp_timer <= TMR_CMP_MAX);    // NOTE: TIMER_CTL_CNTDATEN_Msk exists in NUC472, but not in M451. In M451, TIMER_CNT is updated continuously by default.    ((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname))->CTL = TIMER_CONTINUOUS_MODE | prescale_timer/* | TIMER_CTL_CNTDATEN_Msk*/;    ((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname))->CMP = cmp_timer;    NVIC_SetVector(TIMER_MODINIT.irq_n, (uint32_t) TIMER_MODINIT.var);    NVIC_EnableIRQ(TIMER_MODINIT.irq_n);    TIMER_EnableInt((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));    TIMER_Start((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));}

void SPIClass::begin() {		if(init_flag==0); //init();		/* Unlock protected registers */	SYS_UnlockReg();		/* Enable IP clock */       	CLK_EnableModuleClock(SPI1_MODULE);    	   		/* Select IP clock source and clock divider */	CLK_SetModuleClock(SPI1_MODULE,CLK_CLKSEL1_SPI1_S_HCLK,MODULE_NoMsk);	SYS->GPC_MFP |= SYS_GPC_MFP_PC11_SPI1_MOSI0;	SYS->GPA_MFP |= SYS_GPA_MFPH_GPA10_MFP_SPI1_MISO0 | SYS_GPA_MFPH_GPA11_MFP_SPI1_CLK;	SYS->ALT_MFP |= SYS_ALT_MFP_PC11_SPI1_MOSI0 | SYS_ALT_MFP_PA11_SPI1_CLK | SYS_ALT_MFP_PA10_SPI1_MISO0;	/* Lock protected registers */	SYS_LockReg();			  	/* Configure as a master, clock idle low, falling clock edge Tx, rising edge Rx and 8-bit transaction */	/* Set IP clock divider. SPI clock rate = 12MHz */	SPI_Open(spi, SPI_MASTER, SPI_MODE_0, 8, 6000000);	//SPI_EnableFIFO(spi,2,2); //ouki	setBitOrder(SS, MSBFIRST);}

void SYS_Init(void){    /*---------------------------------------------------------------------------------------------------------*/    /* Init System Clock                                                                                       */    /*---------------------------------------------------------------------------------------------------------*/    /* Unlock protected registers */    SYS_UnlockReg();    /* Set HCLK source form HXT and HCLK source divide 1  */    CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HXT, CLK_CLKDIV0_HCLK(1));    /*  Set HCLK frequency 42MHz */    CLK_SetCoreClock(42000000);    /* Select IP clock source */    CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UARTSEL_HIRC, CLK_CLKDIV0_UART(1));    /* Enable IP clock */    CLK_EnableModuleClock(UART0_MODULE);    /* Update System Core Clock */    /* User can use SystemCoreClockUpdate() to calculate PllClock, SystemCoreClock and CycylesPerUs automatically. */    SystemCoreClockUpdate();    /*---------------------------------------------------------------------------------------------------------*/    /* Init I/O Multi-function                                                                                 */    /*---------------------------------------------------------------------------------------------------------*/    /* Set PD multi-function pins for UART0 RXD(PD.0) and TXD(PD.1) */    SYS->GPD_MFPL &= ~(SYS_GPD_MFPL_PD0MFP_Msk | SYS_GPD_MFPL_PD1MFP_Msk);    SYS->GPD_MFPL |= (SYS_GPD_MFPL_PD0MFP_UART0_RXD | SYS_GPD_MFPL_PD1MFP_UART0_TXD);    /* Lock protected registers */    SYS_LockReg();}

/*---------------------------------------------------------------------------------------------------------*/int main(void){    //Initial System    SYS_Init();    //Enable Timer0 clock and select Timer0 clock source    CLK_EnableModuleClock(TMR0_MODULE);    CLK_SetModuleClock(TMR0_MODULE, CLK_CLKSEL1_TMR0SEL_HXT, 0);    //Initial Timer0 to periodic mode with 2Hz    TIMER_Open(TIMER0, TIMER_PERIODIC_MODE, 2);    //Enable Timer0 interrupt    TIMER_EnableInt(TIMER0);    NVIC_EnableIRQ(TMR0_IRQn);    //Initial 7-Segment    Open_Seven_Segment();    //Start Timer0    TIMER_Start(TIMER0);    while(1)    {        Show_Seven_Segment(TimerCounter / 10, 1);        CLK_SysTickDelay(200);        Show_Seven_Segment(TimerCounter % 10, 2);        CLK_SysTickDelay(200);    }}

void SPIClass::begin() {				if(init_flag==0) init();		 /* Unlock protected registers */	SYS_UnlockReg();		/* Enable IP clock */       	CLK_EnableModuleClock(module);    	   	  /* Select IP clock source and clock divider */	CLK_SetModuleClock(module,clksel,0);		/* Lock protected registers */	SYS_LockReg();			  	/* Configure as a master, clock idle low, falling clock edge Tx, rising edge Rx and 8-bit transaction */  /* Set IP clock divider. SPI clock rate = 4MHz */    SPI_Open(spi, SPI_MASTER, SPI_MODE_0, 8, 4000000); #if defined(__NUC240__)	| defined(__NANO100__) | defined(__NUC131__)  SPI_EnableFIFO(spi,12,12);#endif  setBitOrder(SS, MSBFIRST);  #if defined(__M451__)   SPI_ClearRxFIFO(spi);  SPI_TRIGGER(spi);#endif}

void SysInit(void){    /*---------------------------------------------------------------------------------------------------------*/    /* Init System Clock                                                                                       */    /*---------------------------------------------------------------------------------------------------------*/    /* Unlock protected registers */    SYS_UnlockReg();    /* Set HCLK source form HXT and HCLK source divide 1  */    CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_HXT,CLK_HCLK_CLK_DIVIDER(1));    /* Enable external 12MHz HXT, 32KHz LXT and HIRC */    CLK_EnableXtalRC(CLK_PWRCTL_HXT_EN_Msk | CLK_PWRCTL_LXT_EN_Msk | CLK_PWRCTL_HIRC_EN_Msk);    /* Waiting for clock ready */    CLK_WaitClockReady(CLK_CLKSTATUS_HXT_STB_Msk | CLK_CLKSTATUS_LXT_STB_Msk | CLK_CLKSTATUS_HIRC_STB_Msk);    /*  Set HCLK frequency 32MHz */    CLK_SetCoreClock(32000000);    /* Select IP clock source */    CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UART_S_HIRC, CLK_UART_CLK_DIVIDER(1));    CLK_SetModuleClock(I2C0_MODULE, 0, 0);    CLK_SetModuleClock(I2C1_MODULE, 0, 0);    /* Enable IP clock */    CLK_EnableModuleClock(UART0_MODULE);    CLK_EnableModuleClock(I2C0_MODULE);    CLK_EnableModuleClock(I2C1_MODULE);    /* Update System Core Clock */    /* User can use SystemCoreClockUpdate() to calculate PllClock, SystemCoreClock and CycylesPerUs automatically. */    SystemCoreClockUpdate();    /*---------------------------------------------------------------------------------------------------------*/    /* Init I/O Multi-function                                                                                 */    /*---------------------------------------------------------------------------------------------------------*/    /* Set PB multi-function pins for UART0 RXD and TXD  */    SYS->PB_L_MFP &= ~(SYS_PB_L_MFP_PB0_MFP_Msk | SYS_PB_L_MFP_PB1_MFP_Msk);    SYS->PB_L_MFP |= (SYS_PB_L_MFP_PB0_MFP_UART0_TX | SYS_PB_L_MFP_PB1_MFP_UART0_RX);    /* Set multi function pin for I2C0/I2C1 */    SYS->PC_L_MFP = (SYS_PC_L_MFP_PC0_MFP_I2C0_SCL | SYS_PC_L_MFP_PC1_MFP_I2C0_SDA | SYS_PC_L_MFP_PC2_MFP_I2C1_SCL | SYS_PC_L_MFP_PC3_MFP_I2C1_SDA);    /* Lock protected registers */    SYS_LockReg();}