自学教程：C++ DEBUGFUNC函数代码示例

/** * e1000_init_mac_params_82540 - Init MAC func ptrs. * @hw: pointer to the HW structure **/static s32 e1000_init_mac_params_82540(struct e1000_hw *hw){	struct e1000_mac_info *mac = &hw->mac;	s32 ret_val = E1000_SUCCESS;	DEBUGFUNC("e1000_init_mac_params_82540");	/* Set media type */	switch (hw->device_id) {	case E1000_DEV_ID_82545EM_FIBER:	case E1000_DEV_ID_82545GM_FIBER:	case E1000_DEV_ID_82546EB_FIBER:	case E1000_DEV_ID_82546GB_FIBER:		hw->phy.media_type = e1000_media_type_fiber;		break;	case E1000_DEV_ID_82545GM_SERDES:	case E1000_DEV_ID_82546GB_SERDES:		hw->phy.media_type = e1000_media_type_internal_serdes;		break;	default:		hw->phy.media_type = e1000_media_type_copper;		break;	}	/* Set mta register count */	mac->mta_reg_count = 128;	/* Set rar entry count */	mac->rar_entry_count = E1000_RAR_ENTRIES;	/* Function pointers */	/* bus type/speed/width */	mac->ops.get_bus_info = e1000_get_bus_info_pci_generic;	/* function id */	mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pci;	/* reset */	mac->ops.reset_hw = e1000_reset_hw_82540;	/* hw initialization */	mac->ops.init_hw = e1000_init_hw_82540;	/* link setup */	mac->ops.setup_link = e1000_setup_link_generic;	/* physical interface setup */	mac->ops.setup_physical_interface =		(hw->phy.media_type == e1000_media_type_copper)			? e1000_setup_copper_link_82540			: e1000_setup_fiber_serdes_link_82540;	/* check for link */	switch (hw->phy.media_type) {	case e1000_media_type_copper:		mac->ops.check_for_link = e1000_check_for_copper_link_generic;		break;	case e1000_media_type_fiber:		mac->ops.check_for_link = e1000_check_for_fiber_link_generic;		break;	case e1000_media_type_internal_serdes:		mac->ops.check_for_link = e1000_check_for_serdes_link_generic;		break;	default:		ret_val = -E1000_ERR_CONFIG;		goto out;		break;	}	/* link info */	mac->ops.get_link_up_info =		(hw->phy.media_type == e1000_media_type_copper)			? e1000_get_speed_and_duplex_copper_generic			: e1000_get_speed_and_duplex_fiber_serdes_generic;	/* multicast address update */	mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;	/* writing VFTA */	mac->ops.write_vfta = e1000_write_vfta_generic;	/* clearing VFTA */	mac->ops.clear_vfta = e1000_clear_vfta_generic;	/* read mac address */	mac->ops.read_mac_addr = e1000_read_mac_addr_82540;	/* ID LED init */	mac->ops.id_led_init = e1000_id_led_init_generic;	/* setup LED */	mac->ops.setup_led = e1000_setup_led_generic;	/* cleanup LED */	mac->ops.cleanup_led = e1000_cleanup_led_generic;	/* turn on/off LED */	mac->ops.led_on = e1000_led_on_generic;	mac->ops.led_off = e1000_led_off_generic;	/* clear hardware counters */	mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82540;out:	return ret_val;}

/*----------------------------------------------------------------------------*/WLAN_STATUSwlanoidSendSetQueryP2PCmd(IN P_ADAPTER_T prAdapter,			  UINT_8 ucCID,			  BOOLEAN fgSetQuery,			  BOOLEAN fgNeedResp,			  BOOLEAN fgIsOid,			  PFN_CMD_DONE_HANDLER pfCmdDoneHandler,			  PFN_CMD_TIMEOUT_HANDLER pfCmdTimeoutHandler,			  UINT_32 u4SetQueryInfoLen,			  PUINT_8 pucInfoBuffer,			  OUT PVOID pvSetQueryBuffer, IN UINT_32 u4SetQueryBufferLen){	P_GLUE_INFO_T prGlueInfo;	P_CMD_INFO_T prCmdInfo;	P_WIFI_CMD_T prWifiCmd;	UINT_8 ucCmdSeqNum;	ASSERT(prAdapter);	prGlueInfo = prAdapter->prGlueInfo;	ASSERT(prGlueInfo);	DEBUGFUNC("wlanoidSendSetQueryP2PCmd");	DBGLOG(REQ, TRACE, ("Command ID = 0x%08X/n", ucCID));	prCmdInfo = cmdBufAllocateCmdInfo(prAdapter, (CMD_HDR_SIZE + u4SetQueryInfoLen));	if (!prCmdInfo) {		DBGLOG(INIT, ERROR, ("Allocate CMD_INFO_T ==> FAILED./n"));		return WLAN_STATUS_FAILURE;	}	/* increase command sequence number */	ucCmdSeqNum = nicIncreaseCmdSeqNum(prAdapter);	DBGLOG(REQ, TRACE, ("ucCmdSeqNum =%d/n", ucCmdSeqNum));	/* Setup common CMD Info Packet */	prCmdInfo->eCmdType = COMMAND_TYPE_NETWORK_IOCTL;	prCmdInfo->eNetworkType = NETWORK_TYPE_P2P_INDEX;	prCmdInfo->u2InfoBufLen = (UINT_16) (CMD_HDR_SIZE + u4SetQueryInfoLen);	prCmdInfo->pfCmdDoneHandler = pfCmdDoneHandler;	prCmdInfo->pfCmdTimeoutHandler = pfCmdTimeoutHandler;	prCmdInfo->fgIsOid = fgIsOid;	prCmdInfo->ucCID = ucCID;	prCmdInfo->fgSetQuery = fgSetQuery;	prCmdInfo->fgNeedResp = fgNeedResp;	prCmdInfo->fgDriverDomainMCR = FALSE;	prCmdInfo->ucCmdSeqNum = ucCmdSeqNum;	prCmdInfo->u4SetInfoLen = u4SetQueryInfoLen;	prCmdInfo->pvInformationBuffer = pvSetQueryBuffer;	prCmdInfo->u4InformationBufferLength = u4SetQueryBufferLen;	/* Setup WIFI_CMD_T (no payload) */	prWifiCmd = (P_WIFI_CMD_T) (prCmdInfo->pucInfoBuffer);	prWifiCmd->u2TxByteCount_UserPriority = prCmdInfo->u2InfoBufLen;	prWifiCmd->ucCID = prCmdInfo->ucCID;	prWifiCmd->ucSetQuery = prCmdInfo->fgSetQuery;	prWifiCmd->ucSeqNum = prCmdInfo->ucCmdSeqNum;	if (u4SetQueryInfoLen > 0 && pucInfoBuffer != NULL) {		kalMemCopy(prWifiCmd->aucBuffer, pucInfoBuffer, u4SetQueryInfoLen);	}	/* insert into prCmdQueue */	kalEnqueueCommand(prGlueInfo, (P_QUE_ENTRY_T) prCmdInfo);	/* wakeup txServiceThread later */	GLUE_SET_EVENT(prGlueInfo);	return WLAN_STATUS_PENDING;}

/** *  e1000_init_mac_params_82543 - Init MAC func ptrs. *  @hw: pointer to the HW structure **/STATIC s32 e1000_init_mac_params_82543(struct e1000_hw *hw){	struct e1000_mac_info *mac = &hw->mac;	DEBUGFUNC("e1000_init_mac_params_82543");	/* Set media type */	switch (hw->device_id) {	case E1000_DEV_ID_82543GC_FIBER:	case E1000_DEV_ID_82544EI_FIBER:		hw->phy.media_type = e1000_media_type_fiber;		break;	default:		hw->phy.media_type = e1000_media_type_copper;		break;	}	/* Set mta register count */	mac->mta_reg_count = 128;	/* Set rar entry count */	mac->rar_entry_count = E1000_RAR_ENTRIES;	/* Function pointers */	/* bus type/speed/width */	mac->ops.get_bus_info = e1000_get_bus_info_pci_generic;	/* function id */	mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pci;	/* reset */	mac->ops.reset_hw = e1000_reset_hw_82543;	/* hw initialization */	mac->ops.init_hw = e1000_init_hw_82543;	/* link setup */	mac->ops.setup_link = e1000_setup_link_82543;	/* physical interface setup */	mac->ops.setup_physical_interface =		(hw->phy.media_type == e1000_media_type_copper)		 ? e1000_setup_copper_link_82543 : e1000_setup_fiber_link_82543;	/* check for link */	mac->ops.check_for_link =		(hw->phy.media_type == e1000_media_type_copper)		 ? e1000_check_for_copper_link_82543		 : e1000_check_for_fiber_link_82543;	/* link info */	mac->ops.get_link_up_info =		(hw->phy.media_type == e1000_media_type_copper)		 ? e1000_get_speed_and_duplex_copper_generic		 : e1000_get_speed_and_duplex_fiber_serdes_generic;	/* multicast address update */	mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;	/* writing VFTA */	mac->ops.write_vfta = e1000_write_vfta_82543;	/* clearing VFTA */	mac->ops.clear_vfta = e1000_clear_vfta_generic;	/* turn on/off LED */	mac->ops.led_on = e1000_led_on_82543;	mac->ops.led_off = e1000_led_off_82543;	/* clear hardware counters */	mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82543;	/* Set tbi compatibility */	if ((hw->mac.type != e1000_82543) ||	    (hw->phy.media_type == e1000_media_type_fiber))		e1000_set_tbi_compatibility_82543(hw, false);	return E1000_SUCCESS;}

/** *  e1000_null_mbx_check_for_flag - No-op function, return 0 *  @hw: pointer to the HW structure **/static s32 e1000_null_mbx_check_for_flag(struct e1000_hw *hw, u16 mbx_id){	DEBUGFUNC("e1000_null_mbx_check_flag");	return E1000_SUCCESS;}

/** *  e1000_check_for_copper_link_82543 - Check for link (Copper) *  @hw: pointer to the HW structure * *  Checks the phy for link, if link exists, do the following: *   - check for downshift *   - do polarity workaround (if necessary) *   - configure collision distance *   - configure flow control after link up *   - configure tbi compatibility **/STATIC s32 e1000_check_for_copper_link_82543(struct e1000_hw *hw){	struct e1000_mac_info *mac = &hw->mac;	u32 icr, rctl;	s32 ret_val;	u16 speed, duplex;	bool link;	DEBUGFUNC("e1000_check_for_copper_link_82543");	if (!mac->get_link_status) {		ret_val = E1000_SUCCESS;		goto out;	}	ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);	if (ret_val)		goto out;	if (!link)		goto out; /* No link detected */	mac->get_link_status = false;	e1000_check_downshift_generic(hw);	/*	 * If we are forcing speed/duplex, then we can return since	 * we have already determined whether we have link or not.	 */	if (!mac->autoneg) {		/*		 * If speed and duplex are forced to 10H or 10F, then we will		 * implement the polarity reversal workaround.  We disable		 * interrupts first, and upon returning, place the devices		 * interrupt state to its previous value except for the link		 * status change interrupt which will happened due to the		 * execution of this workaround.		 */		if (mac->forced_speed_duplex & E1000_ALL_10_SPEED) {			E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF);			ret_val = e1000_polarity_reversal_workaround_82543(hw);			icr = E1000_READ_REG(hw, E1000_ICR);			E1000_WRITE_REG(hw, E1000_ICS, (icr & ~E1000_ICS_LSC));			E1000_WRITE_REG(hw, E1000_IMS, IMS_ENABLE_MASK);		}		ret_val = -E1000_ERR_CONFIG;		goto out;	}	/*	 * We have a M88E1000 PHY and Auto-Neg is enabled.  If we	 * have Si on board that is 82544 or newer, Auto	 * Speed Detection takes care of MAC speed/duplex	 * configuration.  So we only need to configure Collision	 * Distance in the MAC.  Otherwise, we need to force	 * speed/duplex on the MAC to the current PHY speed/duplex	 * settings.	 */	if (mac->type == e1000_82544)		hw->mac.ops.config_collision_dist(hw);	else {		ret_val = e1000_config_mac_to_phy_82543(hw);		if (ret_val) {			DEBUGOUT("Error configuring MAC to PHY settings/n");			goto out;		}	}	/*	 * Configure Flow Control now that Auto-Neg has completed.	 * First, we need to restore the desired flow control	 * settings because we may have had to re-autoneg with a	 * different link partner.	 */	ret_val = e1000_config_fc_after_link_up_generic(hw);	if (ret_val)		DEBUGOUT("Error configuring flow control/n");	/*	 * At this point we know that we are on copper and we have	 * auto-negotiated link.  These are conditions for checking the link	 * partner capability register.  We use the link speed to determine if	 * TBI compatibility needs to be turned on or off.  If the link is not	 * at gigabit speed, then TBI compatibility is not needed.  If we are	 * at gigabit speed, we turn on TBI compatibility.	 */	if (e1000_tbi_compatibility_enabled_82543(hw)) {//.........这里部分代码省略.........

/** *  ixgbe_setup_mac_link_multispeed_fixed_fiber - Set MAC link speed *  @hw: pointer to hardware structure *  @speed: new link speed *  @autoneg_wait_to_complete: true when waiting for completion is needed * *  Set the link speed in the AUTOC register and restarts link. **/static s32ixgbe_setup_mac_link_multispeed_fixed_fiber(struct ixgbe_hw *hw,				     ixgbe_link_speed speed,				     bool autoneg_wait_to_complete){	s32 status = IXGBE_SUCCESS;	ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;	ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;	u32 speedcnt = 0;	u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);	u32 i = 0;	bool link_up = false;	bool negotiation;	DEBUGFUNC("");	/* Mask off requested but non-supported speeds */	status = ixgbe_get_link_capabilities(hw, &link_speed, &negotiation);	if (status != IXGBE_SUCCESS)		return status;	speed &= link_speed;	/*	 * Try each speed one by one, highest priority first.  We do this in	 * software because 10gb fiber doesn't support speed autonegotiation.	 */	if (speed & IXGBE_LINK_SPEED_10GB_FULL) {		speedcnt++;		highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;		/* If we already have link at this speed, just jump out */		status = ixgbe_check_link(hw, &link_speed, &link_up, false);		if (status != IXGBE_SUCCESS)			return status;		if ((link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up)			goto out;		/* Set the module link speed */		ixgbe_set_fiber_fixed_speed(hw, IXGBE_LINK_SPEED_10GB_FULL);		/* Set the module link speed */		esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);		IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);		IXGBE_WRITE_FLUSH(hw);		/* Allow module to change analog characteristics (1G->10G) */		msec_delay(40);		status = ixgbe_setup_mac_link_82599(hw,						    IXGBE_LINK_SPEED_10GB_FULL,						    autoneg_wait_to_complete);		if (status != IXGBE_SUCCESS)			return status;		/* Flap the tx laser if it has not already been done */		ixgbe_flap_tx_laser(hw);		/*		 * Wait for the controller to acquire link.  Per IEEE 802.3ap,		 * Section 73.10.2, we may have to wait up to 500ms if KR is		 * attempted.  82599 uses the same timing for 10g SFI.		 */		for (i = 0; i < 5; i++) {			/* Wait for the link partner to also set speed */			msec_delay(100);			/* If we have link, just jump out */			status = ixgbe_check_link(hw, &link_speed,						  &link_up, false);			if (status != IXGBE_SUCCESS)				return status;			if (link_up)				goto out;		}	}	if (speed & IXGBE_LINK_SPEED_1GB_FULL) {		speedcnt++;		if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)			highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;		/* If we already have link at this speed, just jump out */		status = ixgbe_check_link(hw, &link_speed, &link_up, false);		if (status != IXGBE_SUCCESS)			return status;		if ((link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up)			goto out;		/* Set the module link speed *///.........这里部分代码省略.........

/*----------------------------------------------------------------------------*/BOOLEAN nicpmSetAcpiPowerD0(IN P_ADAPTER_T prAdapter){	WLAN_STATUS u4Status = WLAN_STATUS_SUCCESS;	UINT_32 u4Value = 0, u4WHISR = 0;	UINT_8 aucTxCount[8];	UINT_32 i;#if CFG_ENABLE_FW_DOWNLOAD	UINT_32 u4FwImgLength, u4FwLoadAddr, u4ImgSecSize;	PVOID prFwMappingHandle;	PVOID pvFwImageMapFile = NULL;#if CFG_ENABLE_FW_DIVIDED_DOWNLOAD	UINT_32 j;	P_FIRMWARE_DIVIDED_DOWNLOAD_T prFwHead;	BOOLEAN fgValidHead;	const UINT_32 u4CRCOffset = offsetof(FIRMWARE_DIVIDED_DOWNLOAD_T, u4NumOfEntries);#endif#endif	DEBUGFUNC("nicpmSetAcpiPowerD0");	ASSERT(prAdapter);	do {		/* 0. Reset variables in ADAPTER_T */		prAdapter->fgIsFwOwn = TRUE;		prAdapter->fgWiFiInSleepyState = FALSE;		prAdapter->rAcpiState = ACPI_STATE_D0;		prAdapter->fgIsEnterD3ReqIssued = FALSE;		/* 1. Request Ownership to enter F/W download state */		ACQUIRE_POWER_CONTROL_FROM_PM(prAdapter);#if !CFG_ENABLE_FULL_PM		nicpmSetDriverOwn(prAdapter);#endif		/* 2. Initialize the Adapter */		u4Status = nicInitializeAdapter(prAdapter);		if (u4Status != WLAN_STATUS_SUCCESS) {			DBGLOG(NIC, ERROR, "nicInitializeAdapter failed!/n");			u4Status = WLAN_STATUS_FAILURE;			break;		}#if CFG_ENABLE_FW_DOWNLOAD		prFwMappingHandle = kalFirmwareImageMapping(prAdapter->prGlueInfo, &pvFwImageMapFile, &u4FwImgLength);		if (!prFwMappingHandle) {			DBGLOG(NIC, ERROR, "Fail to load FW image from file!/n");			pvFwImageMapFile = NULL;		}		if (pvFwImageMapFile == NULL) {			u4Status = WLAN_STATUS_FAILURE;			break;		}		/* 3.1 disable interrupt, download is done by polling mode only */		nicDisableInterrupt(prAdapter);		/* 3.2 Initialize Tx Resource to fw download state */		nicTxInitResetResource(prAdapter);		/* 3.3 FW download here */		u4FwLoadAddr = kalGetFwLoadAddress(prAdapter->prGlueInfo);#if CFG_ENABLE_FW_DIVIDED_DOWNLOAD		/* 3a. parse file header for decision of divided firmware download or not */		prFwHead = (P_FIRMWARE_DIVIDED_DOWNLOAD_T) pvFwImageMapFile;		if (prFwHead->u4Signature == MTK_WIFI_SIGNATURE &&		    prFwHead->u4CRC == wlanCRC32((PUINT_8) pvFwImageMapFile + u4CRCOffset,						 u4FwImgLength - u4CRCOffset)) {			fgValidHead = TRUE;		} else {			fgValidHead = FALSE;		}		/* 3b. engage divided firmware downloading */		if (fgValidHead == TRUE) {			for (i = 0; i < prFwHead->u4NumOfEntries; i++) {#if CFG_ENABLE_FW_DOWNLOAD_AGGREGATION				if (wlanImageSectionDownloadAggregated(prAdapter,					prFwHead->arSection[i].u4DestAddr,					prFwHead->arSection[i].u4Length,					(PUINT_8) pvFwImageMapFile +					prFwHead->arSection[i].u4Offset) !=					WLAN_STATUS_SUCCESS) {					DBGLOG(NIC, ERROR, "Firmware scatter download failed!/n");					u4Status = WLAN_STATUS_FAILURE;				}#else				for (j = 0; j < prFwHead->arSection[i].u4Length; j += CMD_PKT_SIZE_FOR_IMAGE) {					if (j + CMD_PKT_SIZE_FOR_IMAGE < prFwHead->arSection[i].u4Length)						u4ImgSecSize = CMD_PKT_SIZE_FOR_IMAGE;					else						u4ImgSecSize = prFwHead->arSection[i].u4Length - j;					if (wlanImageSectionDownload(prAdapter,						prFwHead->arSection[i].u4DestAddr + j,						u4ImgSecSize,						(PUINT_8) pvFwImageMapFile +//.........这里部分代码省略.........

s32at_setup_ring_resources(at_adapter *adapter){    int size;    u8 offset = 0;    DEBUGFUNC("at_setup_ring_resources()/n");    /* real ring DMA buffer */    adapter->ring_size = size =   	      adapter->txd_ring_size * 1   + 7         // dword align	    + adapter->txs_ring_size * 4   + 7         // dword align            + adapter->rxd_ring_size * 1536+ 127;    // 128bytes align    	adapter->memDesc = IOBufferMemoryDescriptor::withOptions(kIOMemoryPhysicallyContiguous|																 kIODirectionOut|kIODirectionIn,																	size,																	PAGE_SIZE);	DbgPrint("Allocated memory for ring header %d/n",size);	if (!adapter->memDesc || (adapter->memDesc->prepare() != kIOReturnSuccess))	{		IOSleep(1500);		ErrPrint("Couldn't alloc memory for descriptor ring/n");		if (adapter->memDesc)		{			adapter->memDesc->release();			adapter->memDesc = NULL;		}		DEBUGOUT1("Couldn't alloc memory for descriptor ring, size = D%d/n", size);        return AT_ERR_ENOMEM;	}	IOByteCount dmaLength = 0;	adapter->ring_dma = adapter->memDesc->getPhysicalSegment(0, &dmaLength);	adapter->ring_vir_addr = adapter->memDesc->getBytesNoCopy();	DbgPrint("ring Physical segment address %X pointer %p length %d/n",			adapter->ring_dma, adapter->ring_vir_addr, dmaLength);           memset(adapter->ring_vir_addr, 0, adapter->ring_size);      // Init TXD Ring            adapter->txd_dma = adapter->ring_dma ;      offset = (adapter->txd_dma & 0x7) ? (8 - (adapter->txd_dma & 0x7)) : 0;      adapter->txd_dma += offset;      adapter->txd_ring = (tx_pkt_header_t*) ((u8*)adapter->ring_vir_addr + offset);            // Init TXS Ring            adapter->txs_dma = adapter->txd_dma + adapter->txd_ring_size;      offset = (adapter->txs_dma & 0x7) ? (8- (adapter->txs_dma & 0x7)) : 0;      adapter->txs_dma += offset;      adapter->txs_ring = (tx_pkt_status_t*)                 (((u8*)adapter->txd_ring) + (adapter->txd_ring_size+offset));                      // Init RXD Ring      adapter->rxd_dma = adapter->txs_dma + adapter->txs_ring_size*4;      offset = (adapter->rxd_dma & 127) ? (128 - (adapter->rxd_dma & 127)) : 0;      if (offset > 7) {	  offset -= 8;      } else {	  offset += (128 - 8);      }      adapter->rxd_dma += offset;      adapter->rxd_ring = (rx_desc_t*)                (((u8*)adapter->txs_ring) + 		    (adapter->txs_ring_size*4 + offset));      // Read / Write Ptr Initialize:  //      init_ring_ptrs(adapter);    return AT_SUCCESS;}

/** *  e1000_set_mac_type - Sets MAC type *  @hw: pointer to the HW structure * *  This function sets the mac type of the adapter based on the *  device ID stored in the hw structure. *  MUST BE FIRST FUNCTION CALLED (explicitly or through *  e1000_setup_init_funcs()). **/s32 e1000_set_mac_type(struct e1000_hw *hw){	struct e1000_mac_info *mac = &hw->mac;	s32 ret_val = E1000_SUCCESS;	DEBUGFUNC("e1000_set_mac_type");	switch (hw->device_id) {	case E1000_DEV_ID_82575EB_COPPER:	case E1000_DEV_ID_82575EB_FIBER_SERDES:	case E1000_DEV_ID_82575GB_QUAD_COPPER:		mac->type = e1000_82575;		break;	case E1000_DEV_ID_82576:	case E1000_DEV_ID_82576_FIBER:	case E1000_DEV_ID_82576_SERDES:	case E1000_DEV_ID_82576_QUAD_COPPER:	case E1000_DEV_ID_82576_QUAD_COPPER_ET2:	case E1000_DEV_ID_82576_NS:	case E1000_DEV_ID_82576_NS_SERDES:	case E1000_DEV_ID_82576_SERDES_QUAD:		mac->type = e1000_82576;		break;	case E1000_DEV_ID_82580_COPPER:	case E1000_DEV_ID_82580_FIBER:	case E1000_DEV_ID_82580_SERDES:	case E1000_DEV_ID_82580_SGMII:	case E1000_DEV_ID_82580_COPPER_DUAL:	case E1000_DEV_ID_82580_QUAD_FIBER:	case E1000_DEV_ID_DH89XXCC_SGMII:	case E1000_DEV_ID_DH89XXCC_SERDES:	case E1000_DEV_ID_DH89XXCC_BACKPLANE:	case E1000_DEV_ID_DH89XXCC_SFP:		mac->type = e1000_82580;		break;	case E1000_DEV_ID_I350_COPPER:	case E1000_DEV_ID_I350_FIBER:	case E1000_DEV_ID_I350_SERDES:	case E1000_DEV_ID_I350_SGMII:	case E1000_DEV_ID_I350_DA4:		mac->type = e1000_i350;		break;	case E1000_DEV_ID_I210_COPPER_FLASHLESS:	case E1000_DEV_ID_I210_SERDES_FLASHLESS:	case E1000_DEV_ID_I210_COPPER:	case E1000_DEV_ID_I210_COPPER_OEM1:	case E1000_DEV_ID_I210_COPPER_IT:	case E1000_DEV_ID_I210_FIBER:	case E1000_DEV_ID_I210_SERDES:	case E1000_DEV_ID_I210_SGMII:		mac->type = e1000_i210;		break;	case E1000_DEV_ID_I211_COPPER:		mac->type = e1000_i211;		break;	case E1000_DEV_ID_I354_BACKPLANE_1GBPS:	case E1000_DEV_ID_I354_SGMII:	case E1000_DEV_ID_I354_BACKPLANE_2_5GBPS:		mac->type = e1000_i354;		break;	default:		/* Should never have loaded on this device */		ret_val = -E1000_ERR_MAC_INIT;		break;	}	return ret_val;}

/** *  e1000_init_hw_82540 - Initialize hardware *  @hw: pointer to the HW structure * *  This inits the hardware readying it for operation. **/static s32 e1000_init_hw_82540(struct e1000_hw *hw){	struct e1000_mac_info *mac = &hw->mac;	u32 txdctl, ctrl_ext;	s32 ret_val;	u16 i;	DEBUGFUNC("e1000_init_hw_82540");	/* Initialize identification LED */	ret_val = mac->ops.id_led_init(hw);	if (ret_val) {		DEBUGOUT("Error initializing identification LED/n");		/* This is not fatal and we should not stop init due to this */	}	/* Disabling VLAN filtering */	DEBUGOUT("Initializing the IEEE VLAN/n");	if (mac->type < e1000_82545_rev_3)		E1000_WRITE_REG(hw, E1000_VET, 0);	mac->ops.clear_vfta(hw);	/* Setup the receive address. */	e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);	/* Zero out the Multicast HASH table */	DEBUGOUT("Zeroing the MTA/n");	for (i = 0; i < mac->mta_reg_count; i++) {		E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);		/*		 * Avoid back to back register writes by adding the register		 * read (flush).  This is to protect against some strange		 * bridge configurations that may issue Memory Write Block		 * (MWB) to our register space.  The *_rev_3 hardware at		 * least doesn't respond correctly to every other dword in an		 * MWB to our register space.		 */		E1000_WRITE_FLUSH(hw);	}	if (mac->type < e1000_82545_rev_3)		e1000_pcix_mmrbc_workaround_generic(hw);	/* Setup link and flow control */	ret_val = mac->ops.setup_link(hw);	txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0));	txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |		  E1000_TXDCTL_FULL_TX_DESC_WB;	E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl);	/*	 * Clear all of the statistics registers (clear on read).  It is	 * important that we do this after we have tried to establish link	 * because the symbol error count will increment wildly if there	 * is no link.	 */	e1000_clear_hw_cntrs_82540(hw);	if ((hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER) ||	    (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3)) {		ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);		/*		 * Relaxed ordering must be disabled to avoid a parity		 * error crash in a PCI slot.		 */		ctrl_ext |= E1000_CTRL_EXT_RO_DIS;		E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);	}	return ret_val;}

/** *  ixgbe_reset_hw_X540 - Perform hardware reset *  @hw: pointer to hardware structure * *  Resets the hardware by resetting the transmit and receive units, masks *  and clears all interrupts, and perform a reset. **/s32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw){	s32 status;	u32 ctrl, i;	DEBUGFUNC("ixgbe_reset_hw_X540");	/* Call adapter stop to disable tx/rx and clear interrupts */	status = hw->mac.ops.stop_adapter(hw);	if (status != IXGBE_SUCCESS)		goto reset_hw_out;	/* flush pending Tx transactions */	ixgbe_clear_tx_pending(hw);mac_reset_top:	ctrl = IXGBE_CTRL_RST;	ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);	IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);	IXGBE_WRITE_FLUSH(hw);	/* Poll for reset bit to self-clear indicating reset is complete */	for (i = 0; i < 10; i++) {		usec_delay(1);		ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);		if (!(ctrl & IXGBE_CTRL_RST_MASK))			break;	}	if (ctrl & IXGBE_CTRL_RST_MASK) {		status = IXGBE_ERR_RESET_FAILED;		ERROR_REPORT1(IXGBE_ERROR_POLLING,			     "Reset polling failed to complete./n");	}	msec_delay(100);	/*	 * Double resets are required for recovery from certain error	 * conditions.  Between resets, it is necessary to stall to allow time	 * for any pending HW events to complete.	 */	if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {		hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;		goto mac_reset_top;	}	/* Set the Rx packet buffer size. */	IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), 384 << IXGBE_RXPBSIZE_SHIFT);	/* Store the permanent mac address */	hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);	/*	 * Store MAC address from RAR0, clear receive address registers, and	 * clear the multicast table.  Also reset num_rar_entries to 128,	 * since we modify this value when programming the SAN MAC address.	 */	hw->mac.num_rar_entries = 128;	hw->mac.ops.init_rx_addrs(hw);	/* Store the permanent SAN mac address */	hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);	/* Add the SAN MAC address to the RAR only if it's a valid address */	if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {		/* Save the SAN MAC RAR index */		hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;		hw->mac.ops.set_rar(hw, hw->mac.san_mac_rar_index,				    hw->mac.san_addr, 0, IXGBE_RAH_AV);		/* clear VMDq pool/queue selection for this RAR */		hw->mac.ops.clear_vmdq(hw, hw->mac.san_mac_rar_index,				       IXGBE_CLEAR_VMDQ_ALL);		/* Reserve the last RAR for the SAN MAC address */		hw->mac.num_rar_entries--;	}	/* Store the alternative WWNN/WWPN prefix */	hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,				   &hw->mac.wwpn_prefix);reset_hw_out:	return status;}

/** *  e1000_set_mac_type - Sets MAC type *  @hw: pointer to the HW structure * *  This function sets the mac type of the adapter based on the *  device ID stored in the hw structure. *  MUST BE FIRST FUNCTION CALLED (explicitly or through *  e1000_setup_init_funcs()). **/s32 e1000_set_mac_type(struct e1000_hw *hw){    struct e1000_mac_info *mac = &hw->mac;    s32 ret_val = E1000_SUCCESS;    DEBUGFUNC("e1000_set_mac_type");    switch (hw->device_id) {    case E1000_DEV_ID_82542:        mac->type = e1000_82542;        break;    case E1000_DEV_ID_82543GC_FIBER:    case E1000_DEV_ID_82543GC_COPPER:        mac->type = e1000_82543;        break;    case E1000_DEV_ID_82544EI_COPPER:    case E1000_DEV_ID_82544EI_FIBER:    case E1000_DEV_ID_82544GC_COPPER:    case E1000_DEV_ID_82544GC_LOM:        mac->type = e1000_82544;        break;    case E1000_DEV_ID_82540EM:    case E1000_DEV_ID_82540EM_LOM:    case E1000_DEV_ID_82540EP:    case E1000_DEV_ID_82540EP_LOM:    case E1000_DEV_ID_82540EP_LP:        mac->type = e1000_82540;        break;    case E1000_DEV_ID_82545EM_COPPER:    case E1000_DEV_ID_82545EM_FIBER:        mac->type = e1000_82545;        break;    case E1000_DEV_ID_82545GM_COPPER:    case E1000_DEV_ID_82545GM_FIBER:    case E1000_DEV_ID_82545GM_SERDES:        mac->type = e1000_82545_rev_3;        break;    case E1000_DEV_ID_82546EB_COPPER:    case E1000_DEV_ID_82546EB_FIBER:    case E1000_DEV_ID_82546EB_QUAD_COPPER:        mac->type = e1000_82546;        break;    case E1000_DEV_ID_82546GB_COPPER:    case E1000_DEV_ID_82546GB_FIBER:    case E1000_DEV_ID_82546GB_SERDES:    case E1000_DEV_ID_82546GB_PCIE:    case E1000_DEV_ID_82546GB_QUAD_COPPER:    case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:        mac->type = e1000_82546_rev_3;        break;    case E1000_DEV_ID_82541EI:    case E1000_DEV_ID_82541EI_MOBILE:    case E1000_DEV_ID_82541ER_LOM:        mac->type = e1000_82541;        break;    case E1000_DEV_ID_82541ER:    case E1000_DEV_ID_82541GI:    case E1000_DEV_ID_82541GI_LF:    case E1000_DEV_ID_82541GI_MOBILE:        mac->type = e1000_82541_rev_2;        break;    case E1000_DEV_ID_82547EI:    case E1000_DEV_ID_82547EI_MOBILE:        mac->type = e1000_82547;        break;    case E1000_DEV_ID_82547GI:        mac->type = e1000_82547_rev_2;        break;    case E1000_DEV_ID_82571EB_COPPER:    case E1000_DEV_ID_82571EB_FIBER:    case E1000_DEV_ID_82571EB_SERDES:    case E1000_DEV_ID_82571EB_SERDES_DUAL:    case E1000_DEV_ID_82571EB_SERDES_QUAD:    case E1000_DEV_ID_82571EB_QUAD_COPPER:    case E1000_DEV_ID_82571PT_QUAD_COPPER:    case E1000_DEV_ID_82571EB_QUAD_FIBER:    case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:        mac->type = e1000_82571;        break;    case E1000_DEV_ID_82572EI:    case E1000_DEV_ID_82572EI_COPPER:    case E1000_DEV_ID_82572EI_FIBER:    case E1000_DEV_ID_82572EI_SERDES:        mac->type = e1000_82572;        break;    case E1000_DEV_ID_82573E:    case E1000_DEV_ID_82573E_IAMT:    case E1000_DEV_ID_82573L:        mac->type = e1000_82573;        break;    case E1000_DEV_ID_82574L://.........这里部分代码省略.........

/** *  ixgbe_init_ops_X540 - Inits func ptrs and MAC type *  @hw: pointer to hardware structure * *  Initialize the function pointers and assign the MAC type for X540. *  Does not touch the hardware. **/s32 ixgbe_init_ops_X540(struct ixgbe_hw *hw){	struct ixgbe_mac_info *mac = &hw->mac;	struct ixgbe_phy_info *phy = &hw->phy;	struct ixgbe_eeprom_info *eeprom = &hw->eeprom;	s32 ret_val;	DEBUGFUNC("ixgbe_init_ops_X540");	ret_val = ixgbe_init_phy_ops_generic(hw);	ret_val = ixgbe_init_ops_generic(hw);	/* EEPROM */	eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;	eeprom->ops.read = ixgbe_read_eerd_X540;	eeprom->ops.read_buffer = ixgbe_read_eerd_buffer_X540;	eeprom->ops.write = ixgbe_write_eewr_X540;	eeprom->ops.write_buffer = ixgbe_write_eewr_buffer_X540;	eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X540;	eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X540;	eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X540;	/* PHY */	phy->ops.init = ixgbe_init_phy_ops_generic;	phy->ops.reset = NULL;	phy->ops.set_phy_power = ixgbe_set_copper_phy_power;	/* MAC */	mac->ops.reset_hw = ixgbe_reset_hw_X540;	mac->ops.enable_relaxed_ordering = ixgbe_enable_relaxed_ordering_gen2;	mac->ops.get_media_type = ixgbe_get_media_type_X540;	mac->ops.get_supported_physical_layer =				    ixgbe_get_supported_physical_layer_X540;	mac->ops.read_analog_reg8 = NULL;	mac->ops.write_analog_reg8 = NULL;	mac->ops.start_hw = ixgbe_start_hw_X540;	mac->ops.get_san_mac_addr = ixgbe_get_san_mac_addr_generic;	mac->ops.set_san_mac_addr = ixgbe_set_san_mac_addr_generic;	mac->ops.get_device_caps = ixgbe_get_device_caps_generic;	mac->ops.get_wwn_prefix = ixgbe_get_wwn_prefix_generic;	mac->ops.get_fcoe_boot_status = ixgbe_get_fcoe_boot_status_generic;	mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X540;	mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X540;	mac->ops.init_swfw_sync = ixgbe_init_swfw_sync_X540;	mac->ops.disable_sec_rx_path = ixgbe_disable_sec_rx_path_generic;	mac->ops.enable_sec_rx_path = ixgbe_enable_sec_rx_path_generic;	/* RAR, Multicast, VLAN */	mac->ops.set_vmdq = ixgbe_set_vmdq_generic;	mac->ops.set_vmdq_san_mac = ixgbe_set_vmdq_san_mac_generic;	mac->ops.clear_vmdq = ixgbe_clear_vmdq_generic;	mac->ops.insert_mac_addr = ixgbe_insert_mac_addr_generic;	mac->rar_highwater = 1;	mac->ops.set_vfta = ixgbe_set_vfta_generic;	mac->ops.set_vlvf = ixgbe_set_vlvf_generic;	mac->ops.clear_vfta = ixgbe_clear_vfta_generic;	mac->ops.init_uta_tables = ixgbe_init_uta_tables_generic;	mac->ops.set_mac_anti_spoofing = ixgbe_set_mac_anti_spoofing;	mac->ops.set_vlan_anti_spoofing = ixgbe_set_vlan_anti_spoofing;	/* Link */	mac->ops.get_link_capabilities =				ixgbe_get_copper_link_capabilities_generic;	mac->ops.setup_link = ixgbe_setup_mac_link_X540;	mac->ops.setup_rxpba = ixgbe_set_rxpba_generic;	mac->ops.check_link = ixgbe_check_mac_link_generic;	mac->mcft_size		= IXGBE_X540_MC_TBL_SIZE;	mac->vft_size		= IXGBE_X540_VFT_TBL_SIZE;	mac->num_rar_entries	= IXGBE_X540_RAR_ENTRIES;	mac->rx_pb_size		= IXGBE_X540_RX_PB_SIZE;	mac->max_rx_queues	= IXGBE_X540_MAX_RX_QUEUES;	mac->max_tx_queues	= IXGBE_X540_MAX_TX_QUEUES;	mac->max_msix_vectors	= ixgbe_get_pcie_msix_count_generic(hw);	/*	 * FWSM register	 * ARC supported; valid only if manageability features are	 * enabled.	 */	mac->arc_subsystem_valid = !!(IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw))				     & IXGBE_FWSM_MODE_MASK);	hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf;	/* LEDs */	mac->ops.blink_led_start = ixgbe_blink_led_start_X540;	mac->ops.blink_led_stop = ixgbe_blink_led_stop_X540;	/* Manageability interface */	mac->ops.set_fw_drv_ver = ixgbe_set_fw_drv_ver_generic;//.........这里部分代码省略.........

/** *  e1000_setup_copper_link_82543 - Configure copper link settings *  @hw: pointer to the HW structure * *  Configures the link for auto-neg or forced speed and duplex.  Then we check *  for link, once link is established calls to configure collision distance *  and flow control are called. **/STATIC s32 e1000_setup_copper_link_82543(struct e1000_hw *hw){	u32 ctrl;	s32 ret_val;	bool link;	DEBUGFUNC("e1000_setup_copper_link_82543");	ctrl = E1000_READ_REG(hw, E1000_CTRL) | E1000_CTRL_SLU;	/*	 * With 82543, we need to force speed and duplex on the MAC	 * equal to what the PHY speed and duplex configuration is.	 * In addition, we need to perform a hardware reset on the	 * PHY to take it out of reset.	 */	if (hw->mac.type == e1000_82543) {		ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);		E1000_WRITE_REG(hw, E1000_CTRL, ctrl);		ret_val = hw->phy.ops.reset(hw);		if (ret_val)			goto out;	} else {		ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);		E1000_WRITE_REG(hw, E1000_CTRL, ctrl);	}	/* Set MDI/MDI-X, Polarity Reversal, and downshift settings */	ret_val = e1000_copper_link_setup_m88(hw);	if (ret_val)		goto out;	if (hw->mac.autoneg) {		/*		 * Setup autoneg and flow control advertisement and perform		 * autonegotiation.		 */		ret_val = e1000_copper_link_autoneg(hw);		if (ret_val)			goto out;	} else {		/*		 * PHY will be set to 10H, 10F, 100H or 100F		 * depending on user settings.		 */		DEBUGOUT("Forcing Speed and Duplex/n");		ret_val = e1000_phy_force_speed_duplex_82543(hw);		if (ret_val) {			DEBUGOUT("Error Forcing Speed and Duplex/n");			goto out;		}	}	/*	 * Check link status. Wait up to 100 microseconds for link to become	 * valid.	 */	ret_val = e1000_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10,					     &link);	if (ret_val)		goto out;	if (link) {		DEBUGOUT("Valid link established!!!/n");		/* Config the MAC and PHY after link is up */		if (hw->mac.type == e1000_82544) {			hw->mac.ops.config_collision_dist(hw);		} else {			ret_val = e1000_config_mac_to_phy_82543(hw);			if (ret_val)				goto out;		}		ret_val = e1000_config_fc_after_link_up_generic(hw);	} else {		DEBUGOUT("Unable to establish link!!!/n");	}out:	return ret_val;}

/** *  e1000_get_hw_semaphore_i210 - Acquire hardware semaphore *  @hw: pointer to the HW structure * *  Acquire the HW semaphore to access the PHY or NVM **/static s32 e1000_get_hw_semaphore_i210(struct e1000_hw *hw){	u32 swsm;	s32 timeout = hw->nvm.word_size + 1;	s32 i = 0;	DEBUGFUNC("e1000_get_hw_semaphore_i210");	/* Get the SW semaphore */	while (i < timeout) {		swsm = E1000_READ_REG(hw, E1000_SWSM);		if (!(swsm & E1000_SWSM_SMBI))			break;		usec_delay(50);		i++;	}	if (i == timeout) {		/*		 * In rare circumstances, the driver may not have released the		 * SW semaphore. Clear the semaphore once before giving up.		 */		if (hw->dev_spec._82575.clear_semaphore_once) {			hw->dev_spec._82575.clear_semaphore_once = false;			e1000_put_hw_semaphore_generic(hw);			for (i = 0; i < timeout; i++) {				swsm = E1000_READ_REG(hw, E1000_SWSM);				if (!(swsm & E1000_SWSM_SMBI))					break;				usec_delay(50);			}		}		/* If we do not have the semaphore here, we have to give up. */		if (i == timeout) {			DEBUGOUT("Driver can't access device - SMBI bit is set./n");			return -E1000_ERR_NVM;		}	}	/* Get the FW semaphore. */	for (i = 0; i < timeout; i++) {		swsm = E1000_READ_REG(hw, E1000_SWSM);		E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI);		/* Semaphore acquired if bit latched */		if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI)			break;		usec_delay(50);	}	if (i == timeout) {		/* Release semaphores */		e1000_put_hw_semaphore_generic(hw);		DEBUGOUT("Driver can't access the NVM/n");		return -E1000_ERR_NVM;	}	return E1000_SUCCESS;}

/** *  e1000_check_for_fiber_link_82543 - Check for link (Fiber) *  @hw: pointer to the HW structure * *  Checks for link up on the hardware.  If link is not up and we have *  a signal, then we need to force link up. **/STATIC s32 e1000_check_for_fiber_link_82543(struct e1000_hw *hw){	struct e1000_mac_info *mac = &hw->mac;	u32 rxcw, ctrl, status;	s32 ret_val = E1000_SUCCESS;	DEBUGFUNC("e1000_check_for_fiber_link_82543");	ctrl = E1000_READ_REG(hw, E1000_CTRL);	status = E1000_READ_REG(hw, E1000_STATUS);	rxcw = E1000_READ_REG(hw, E1000_RXCW);	/*	 * If we don't have link (auto-negotiation failed or link partner	 * cannot auto-negotiate), the cable is plugged in (we have signal),	 * and our link partner is not trying to auto-negotiate with us (we	 * are receiving idles or data), we need to force link up. We also	 * need to give auto-negotiation time to complete, in case the cable	 * was just plugged in. The autoneg_failed flag does this.	 */	/* (ctrl & E1000_CTRL_SWDPIN1) == 0 == have signal */	if ((!(ctrl & E1000_CTRL_SWDPIN1)) &&	    (!(status & E1000_STATUS_LU)) &&	    (!(rxcw & E1000_RXCW_C))) {		if (!mac->autoneg_failed) {			mac->autoneg_failed = true;			ret_val = 0;			goto out;		}		DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link./n");		/* Disable auto-negotiation in the TXCW register */		E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE));		/* Force link-up and also force full-duplex. */		ctrl = E1000_READ_REG(hw, E1000_CTRL);		ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);		E1000_WRITE_REG(hw, E1000_CTRL, ctrl);		/* Configure Flow Control after forcing link up. */		ret_val = e1000_config_fc_after_link_up_generic(hw);		if (ret_val) {			DEBUGOUT("Error configuring flow control/n");			goto out;		}	} else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {		/*		 * If we are forcing link and we are receiving /C/ ordered		 * sets, re-enable auto-negotiation in the TXCW register		 * and disable forced link in the Device Control register		 * in an attempt to auto-negotiate with our link partner.		 */		DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link./n");		E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);		E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU));		mac->serdes_has_link = true;	}out:	return ret_val;}

/** *  e1000_read_nvm_i211 - Read NVM wrapper function for I211 *  @hw: pointer to the HW structure *  @address: the word address (aka eeprom offset) to read *  @data: pointer to the data read * *  Wrapper function to return data formerly found in the NVM. **/static s32 e1000_read_nvm_i211(struct e1000_hw *hw, u16 offset, u16 words,			       u16 *data){	s32 ret_val = E1000_SUCCESS;	DEBUGFUNC("e1000_read_nvm_i211");	/* Only the MAC addr is required to be present in the iNVM */	switch (offset) {	case NVM_MAC_ADDR:		ret_val = e1000_read_invm_i211(hw, (u8)offset, &data[0]);		ret_val |= e1000_read_invm_i211(hw, (u8)offset+1, &data[1]);		ret_val |= e1000_read_invm_i211(hw, (u8)offset+2, &data[2]);		if (ret_val != E1000_SUCCESS)			DEBUGOUT("MAC Addr not found in iNVM/n");		break;	case NVM_INIT_CTRL_2:		ret_val = e1000_read_invm_i211(hw, (u8)offset, data);		if (ret_val != E1000_SUCCESS) {			*data = NVM_INIT_CTRL_2_DEFAULT_I211;			ret_val = E1000_SUCCESS;		}		break;	case NVM_INIT_CTRL_4:		ret_val = e1000_read_invm_i211(hw, (u8)offset, data);		if (ret_val != E1000_SUCCESS) {			*data = NVM_INIT_CTRL_4_DEFAULT_I211;			ret_val = E1000_SUCCESS;		}		break;	case NVM_LED_1_CFG:		ret_val = e1000_read_invm_i211(hw, (u8)offset, data);		if (ret_val != E1000_SUCCESS) {			*data = NVM_LED_1_CFG_DEFAULT_I211;			ret_val = E1000_SUCCESS;		}		break;	case NVM_LED_0_2_CFG:		ret_val = e1000_read_invm_i211(hw, (u8)offset, data);		if (ret_val != E1000_SUCCESS) {			*data = NVM_LED_0_2_CFG_DEFAULT_I211;			ret_val = E1000_SUCCESS;		}		break;	case NVM_ID_LED_SETTINGS:		ret_val = e1000_read_invm_i211(hw, (u8)offset, data);		if (ret_val != E1000_SUCCESS) {			*data = ID_LED_RESERVED_FFFF;			ret_val = E1000_SUCCESS;		}		break;	case NVM_SUB_DEV_ID:		*data = hw->subsystem_device_id;		break;	case NVM_SUB_VEN_ID:		*data = hw->subsystem_vendor_id;		break;	case NVM_DEV_ID:		*data = hw->device_id;		break;	case NVM_VEN_ID:		*data = hw->vendor_id;		break;	default:		DEBUGOUT1("NVM word 0x%02x is not mapped./n", offset);		*data = NVM_RESERVED_WORD;		break;	}	return ret_val;}

/** *  e1000_init_phy_params_82543 - Init PHY func ptrs. *  @hw: pointer to the HW structure **/STATIC s32 e1000_init_phy_params_82543(struct e1000_hw *hw){	struct e1000_phy_info *phy = &hw->phy;	s32 ret_val = E1000_SUCCESS;	DEBUGFUNC("e1000_init_phy_params_82543");	if (hw->phy.media_type != e1000_media_type_copper) {		phy->type = e1000_phy_none;		goto out;	} else {		phy->ops.power_up = e1000_power_up_phy_copper;		phy->ops.power_down = e1000_power_down_phy_copper;	}	phy->addr		= 1;	phy->autoneg_mask	= AUTONEG_ADVERTISE_SPEED_DEFAULT;	phy->reset_delay_us	= 10000;	phy->type		= e1000_phy_m88;	/* Function Pointers */	phy->ops.check_polarity	= e1000_check_polarity_m88;	phy->ops.commit		= e1000_phy_sw_reset_generic;	phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_82543;	phy->ops.get_cable_length = e1000_get_cable_length_m88;	phy->ops.get_cfg_done	= e1000_get_cfg_done_generic;	phy->ops.read_reg	= (hw->mac.type == e1000_82543)				  ? e1000_read_phy_reg_82543				  : e1000_read_phy_reg_m88;	phy->ops.reset		= (hw->mac.type == e1000_82543)				  ? e1000_phy_hw_reset_82543				  : e1000_phy_hw_reset_generic;	phy->ops.write_reg	= (hw->mac.type == e1000_82543)				  ? e1000_write_phy_reg_82543				  : e1000_write_phy_reg_m88;	phy->ops.get_info	= e1000_get_phy_info_m88;	/*	 * The external PHY of the 82543 can be in a funky state.	 * Resetting helps us read the PHY registers for acquiring	 * the PHY ID.	 */	if (!e1000_init_phy_disabled_82543(hw)) {		ret_val = phy->ops.reset(hw);		if (ret_val) {			DEBUGOUT("Resetting PHY during init failed./n");			goto out;		}		msec_delay(20);	}	ret_val = e1000_get_phy_id(hw);	if (ret_val)		goto out;	/* Verify phy id */	switch (hw->mac.type) {	case e1000_82543:		if (phy->id != M88E1000_E_PHY_ID) {			ret_val = -E1000_ERR_PHY;			goto out;		}		break;	case e1000_82544:		if (phy->id != M88E1000_I_PHY_ID) {			ret_val = -E1000_ERR_PHY;			goto out;		}		break;	default:		ret_val = -E1000_ERR_PHY;		goto out;		break;	}out:	return ret_val;}

/** *  e1000_release_nvm_i210 - Release exclusive access to EEPROM *  @hw: pointer to the HW structure * *  Stop any current commands to the EEPROM and clear the EEPROM request bit, *  then release the semaphores acquired. **/static void e1000_release_nvm_i210(struct e1000_hw *hw){	DEBUGFUNC("e1000_release_nvm_i210");	e1000_release_swfw_sync_i210(hw, E1000_SWFW_EEP_SM);}

/** *  e1000_init_nvm_params_82541 - Init NVM func ptrs. *  @hw: pointer to the HW structure **/static s32 e1000_init_nvm_params_82541(struct e1000_hw *hw){	struct e1000_nvm_info *nvm = &hw->nvm;	s32 ret_val = E1000_SUCCESS;	u32 eecd = E1000_READ_REG(hw, E1000_EECD);	u16 size;	DEBUGFUNC("e1000_init_nvm_params_82541");	switch (nvm->override) {	case e1000_nvm_override_spi_large:		nvm->type = e1000_nvm_eeprom_spi;		eecd |= E1000_EECD_ADDR_BITS;		break;	case e1000_nvm_override_spi_small:		nvm->type = e1000_nvm_eeprom_spi;		eecd &= ~E1000_EECD_ADDR_BITS;		break;	case e1000_nvm_override_microwire_large:		nvm->type = e1000_nvm_eeprom_microwire;		eecd |= E1000_EECD_SIZE;		break;	case e1000_nvm_override_microwire_small:		nvm->type = e1000_nvm_eeprom_microwire;		eecd &= ~E1000_EECD_SIZE;		break;	default:		nvm->type = eecd & E1000_EECD_TYPE ? e1000_nvm_eeprom_spi			    : e1000_nvm_eeprom_microwire;		break;	}	if (nvm->type == e1000_nvm_eeprom_spi) {		nvm->address_bits = (eecd & E1000_EECD_ADDR_BITS) ? 16 : 8;		nvm->delay_usec = 1;		nvm->opcode_bits = 8;		nvm->page_size = (eecd & E1000_EECD_ADDR_BITS) ? 32 : 8;		/* Function Pointers */		nvm->ops.acquire	= e1000_acquire_nvm_generic;		nvm->ops.read		= e1000_read_nvm_spi;		nvm->ops.release	= e1000_release_nvm_generic;		nvm->ops.update		= e1000_update_nvm_checksum_generic;		nvm->ops.valid_led_default = e1000_valid_led_default_generic;		nvm->ops.validate	= e1000_validate_nvm_checksum_generic;		nvm->ops.write		= e1000_write_nvm_spi;		/*		 * nvm->word_size must be discovered after the pointers		 * are set so we can verify the size from the nvm image		 * itself.  Temporarily set it to a dummy value so the		 * read will work.		 */		nvm->word_size = 64;		ret_val = nvm->ops.read(hw, NVM_CFG, 1, &size);		if (ret_val)			goto out;		size = (size & NVM_SIZE_MASK) >> NVM_SIZE_SHIFT;		/*		 * if size != 0, it can be added to a constant and become		 * the left-shift value to set the word_size.  Otherwise,		 * word_size stays at 64.		 */		if (size) {			size += NVM_WORD_SIZE_BASE_SHIFT_82541;			nvm->word_size = 1 << size;		}	} else {

/*----------------------------------------------------------------------------*/VOIDsecInit (    IN P_ADAPTER_T          prAdapter,    IN UINT_8               ucBssIndex    ){    UINT_8                  i;    P_CONNECTION_SETTINGS_T prConnSettings;    P_BSS_INFO_T            prBssInfo;    P_AIS_SPECIFIC_BSS_INFO_T prAisSpecBssInfo;    DEBUGFUNC("secInit");    ASSERT(prAdapter);    prConnSettings = &prAdapter->rWifiVar.rConnSettings;    prBssInfo = GET_BSS_INFO_BY_INDEX(prAdapter, ucBssIndex);    prAisSpecBssInfo = &prAdapter->rWifiVar.rAisSpecificBssInfo;    prBssInfo->u4RsnSelectedGroupCipher = 0;    prBssInfo->u4RsnSelectedPairwiseCipher = 0;    prBssInfo->u4RsnSelectedAKMSuite = 0;#if 0// CFG_ENABLE_WIFI_DIRECT    prBssInfo = &prAdapter->rWifiVar.arBssInfo[NETWORK_TYPE_P2P];    prBssInfo->u4RsnSelectedGroupCipher = RSN_CIPHER_SUITE_CCMP;    prBssInfo->u4RsnSelectedPairwiseCipher = RSN_CIPHER_SUITE_CCMP;    prBssInfo->u4RsnSelectedAKMSuite = RSN_AKM_SUITE_PSK;#endif#if 0//CFG_ENABLE_BT_OVER_WIFI    prBssInfo = &prAdapter->rWifiVar.arBssInfo[NETWORK_TYPE_BOW];    prBssInfo->u4RsnSelectedGroupCipher = RSN_CIPHER_SUITE_CCMP;    prBssInfo->u4RsnSelectedPairwiseCipher = RSN_CIPHER_SUITE_CCMP;    prBssInfo->u4RsnSelectedAKMSuite = RSN_AKM_SUITE_PSK;#endif    prAdapter->rMib.dot11RSNAConfigPairwiseCiphersTable[0].dot11RSNAConfigPairwiseCipher =            WPA_CIPHER_SUITE_WEP40;    prAdapter->rMib.dot11RSNAConfigPairwiseCiphersTable[1].dot11RSNAConfigPairwiseCipher =            WPA_CIPHER_SUITE_TKIP;    prAdapter->rMib.dot11RSNAConfigPairwiseCiphersTable[2].dot11RSNAConfigPairwiseCipher =            WPA_CIPHER_SUITE_CCMP;    prAdapter->rMib.dot11RSNAConfigPairwiseCiphersTable[3].dot11RSNAConfigPairwiseCipher =            WPA_CIPHER_SUITE_WEP104;    prAdapter->rMib.dot11RSNAConfigPairwiseCiphersTable[4].dot11RSNAConfigPairwiseCipher =            RSN_CIPHER_SUITE_WEP40;    prAdapter->rMib.dot11RSNAConfigPairwiseCiphersTable[5].dot11RSNAConfigPairwiseCipher =            RSN_CIPHER_SUITE_TKIP;    prAdapter->rMib.dot11RSNAConfigPairwiseCiphersTable[6].dot11RSNAConfigPairwiseCipher =            RSN_CIPHER_SUITE_CCMP;    prAdapter->rMib.dot11RSNAConfigPairwiseCiphersTable[7].dot11RSNAConfigPairwiseCipher =            RSN_CIPHER_SUITE_WEP104;    for (i = 0; i < MAX_NUM_SUPPORTED_CIPHER_SUITES; i ++) {        prAdapter->rMib.dot11RSNAConfigPairwiseCiphersTable[i].dot11RSNAConfigPairwiseCipherEnabled =            FALSE;    }    prAdapter->rMib.dot11RSNAConfigAuthenticationSuitesTable[0].dot11RSNAConfigAuthenticationSuite =            WPA_AKM_SUITE_NONE;    prAdapter->rMib.dot11RSNAConfigAuthenticationSuitesTable[1].dot11RSNAConfigAuthenticationSuite =            WPA_AKM_SUITE_802_1X;    prAdapter->rMib.dot11RSNAConfigAuthenticationSuitesTable[2].dot11RSNAConfigAuthenticationSuite =            WPA_AKM_SUITE_PSK;    prAdapter->rMib.dot11RSNAConfigAuthenticationSuitesTable[3].dot11RSNAConfigAuthenticationSuite =            RSN_AKM_SUITE_NONE;    prAdapter->rMib.dot11RSNAConfigAuthenticationSuitesTable[4].dot11RSNAConfigAuthenticationSuite =            RSN_AKM_SUITE_802_1X;    prAdapter->rMib.dot11RSNAConfigAuthenticationSuitesTable[5].dot11RSNAConfigAuthenticationSuite =            RSN_AKM_SUITE_PSK;#if CFG_SUPPORT_802_11W    prAdapter->rMib.dot11RSNAConfigAuthenticationSuitesTable[6].dot11RSNAConfigAuthenticationSuite =            RSN_AKM_SUITE_802_1X_SHA256;    prAdapter->rMib.dot11RSNAConfigAuthenticationSuitesTable[7].dot11RSNAConfigAuthenticationSuite =            RSN_AKM_SUITE_PSK_SHA256;#endif    for (i = 0; i < MAX_NUM_SUPPORTED_AKM_SUITES; i ++) {        prAdapter->rMib.dot11RSNAConfigAuthenticationSuitesTable[i].dot11RSNAConfigAuthenticationSuiteEnabled =            FALSE;    }    secClearPmkid(prAdapter);    cnmTimerInitTimer(prAdapter,                   &prAisSpecBssInfo->rPreauthenticationTimer,                   (PFN_MGMT_TIMEOUT_FUNC)rsnIndicatePmkidCand,                   (UINT_32)NULL);#if CFG_SUPPORT_802_11W    cnmTimerInitTimer(prAdapter,                   &prAisSpecBssInfo->rSaQueryTimer,                   (PFN_MGMT_TIMEOUT_FUNC)rsnStartSaQueryTimer,                   (UINT_32)NULL);//.........这里部分代码省略.........

/*----------------------------------------------------------------------------*/WLAN_STATUSwlanoidSetP2pSetNetworkAddress(IN P_ADAPTER_T prAdapter,			       IN PVOID pvSetBuffer,			       IN UINT_32 u4SetBufferLen, OUT PUINT_32 pu4SetInfoLen){	WLAN_STATUS rStatus = WLAN_STATUS_SUCCESS;	UINT_32 i, j;	P_CMD_SET_NETWORK_ADDRESS_LIST prCmdNetworkAddressList;	P_PARAM_NETWORK_ADDRESS_LIST prNetworkAddressList =	    (P_PARAM_NETWORK_ADDRESS_LIST) pvSetBuffer;	P_PARAM_NETWORK_ADDRESS prNetworkAddress;	P_PARAM_NETWORK_ADDRESS_IP prNetAddrIp;	UINT_32 u4IpAddressCount, u4CmdSize;	PUINT_8 pucBuf = (PUINT_8) pvSetBuffer;	DEBUGFUNC("wlanoidSetP2pSetNetworkAddress");	DBGLOG(INIT, TRACE, ("/n"));	printk("wlanoidSetP2pSetNetworkAddress (%d)/n", (INT_16) u4SetBufferLen);	ASSERT(prAdapter);	ASSERT(pu4SetInfoLen);	*pu4SetInfoLen = 4;	if (u4SetBufferLen < sizeof(PARAM_NETWORK_ADDRESS_LIST)) {		return WLAN_STATUS_INVALID_DATA;	}	*pu4SetInfoLen = 0;	u4IpAddressCount = 0;	prNetworkAddress = prNetworkAddressList->arAddress;	for (i = 0; i < prNetworkAddressList->u4AddressCount; i++) {		if (prNetworkAddress->u2AddressType == PARAM_PROTOCOL_ID_TCP_IP &&		    prNetworkAddress->u2AddressLength == sizeof(PARAM_NETWORK_ADDRESS_IP)) {			u4IpAddressCount++;		}		prNetworkAddress = (P_PARAM_NETWORK_ADDRESS) ((UINT_32) prNetworkAddress +							      (UINT_32) (prNetworkAddress->									 u2AddressLength +									 OFFSET_OF									 (PARAM_NETWORK_ADDRESS,									  aucAddress)));	}	/* construct payload of command packet */	u4CmdSize = OFFSET_OF(CMD_SET_NETWORK_ADDRESS_LIST, arNetAddress) +	    sizeof(IPV4_NETWORK_ADDRESS) * u4IpAddressCount;	if (u4IpAddressCount == 0) {		u4CmdSize = sizeof(CMD_SET_NETWORK_ADDRESS_LIST);	}	prCmdNetworkAddressList =	    (P_CMD_SET_NETWORK_ADDRESS_LIST) kalMemAlloc(u4CmdSize, VIR_MEM_TYPE);	if (prCmdNetworkAddressList == NULL)		return WLAN_STATUS_FAILURE;	/* fill P_CMD_SET_NETWORK_ADDRESS_LIST */	prCmdNetworkAddressList->ucNetTypeIndex = NETWORK_TYPE_P2P_INDEX;	/* only to set IP address to FW once ARP filter is enabled */	if (prAdapter->fgEnArpFilter) {		prCmdNetworkAddressList->ucAddressCount = (UINT_8) u4IpAddressCount;		prNetworkAddress = prNetworkAddressList->arAddress;		printk("u4IpAddressCount (%ld)/n", (INT_32) u4IpAddressCount);		for (i = 0, j = 0; i < prNetworkAddressList->u4AddressCount; i++) {			if (prNetworkAddress->u2AddressType == PARAM_PROTOCOL_ID_TCP_IP &&			    prNetworkAddress->u2AddressLength == sizeof(PARAM_NETWORK_ADDRESS_IP)) {				prNetAddrIp =				    (P_PARAM_NETWORK_ADDRESS_IP) prNetworkAddress->aucAddress;				kalMemCopy(prCmdNetworkAddressList->arNetAddress[j].aucIpAddr,					   &(prNetAddrIp->in_addr), sizeof(UINT_32));				j++;				pucBuf = (PUINT_8) &prNetAddrIp->in_addr;				printk("prNetAddrIp->in_addr:%d:%d:%d:%d/n", (UINT_8) pucBuf[0],				       (UINT_8) pucBuf[1], (UINT_8) pucBuf[2], (UINT_8) pucBuf[3]);			}			prNetworkAddress = (P_PARAM_NETWORK_ADDRESS) ((UINT_32) prNetworkAddress +								      (UINT_32) (prNetworkAddress->										 u2AddressLength +										 OFFSET_OF										 (PARAM_NETWORK_ADDRESS,										  aucAddress)));		}	} else {		prCmdNetworkAddressList->ucAddressCount = 0;	}	rStatus = wlanSendSetQueryCmd(prAdapter,				      CMD_ID_SET_IP_ADDRESS,//.........这里部分代码省略.........