自学教程：C++ E1000_WRITE_FLUSH函数代码示例

/** * e1000_configure_rx - Configure 8254x Receive Unit after Reset * @adapter: board private structure * * Configure the Rx unit of the MAC after a reset. **/static void e1000_configure_rx ( struct e1000_adapter *adapter ){	struct e1000_hw *hw = &adapter->hw;	uint32_t rctl;	DBG ( "e1000_configure_rx/n" );	/* disable receives while setting up the descriptors */	rctl = E1000_READ_REG ( hw, E1000_RCTL );	E1000_WRITE_REG ( hw, E1000_RCTL, rctl & ~E1000_RCTL_EN );	E1000_WRITE_FLUSH ( hw );	mdelay(10);	adapter->rx_curr = 0;	/* Setup the HW Rx Head and Tail Descriptor Pointers and	 * the Base and Length of the Rx Descriptor Ring */	E1000_WRITE_REG ( hw, E1000_RDBAL(0), virt_to_bus ( adapter->rx_base ) );	E1000_WRITE_REG ( hw, E1000_RDBAH(0), 0 );	E1000_WRITE_REG ( hw, E1000_RDLEN(0), adapter->rx_ring_size );	E1000_WRITE_REG ( hw, E1000_RDH(0), 0 );	E1000_WRITE_REG ( hw, E1000_RDT(0), NUM_RX_DESC - 1 );	/* Enable Receives */	rctl |=  E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_SZ_2048 |		 E1000_RCTL_MPE | E1000_RCTL_SECRC;	E1000_WRITE_REG ( hw, E1000_RCTL, rctl );	E1000_WRITE_FLUSH ( hw );        DBG ( "E1000_RDBAL(0): %#08x/n",  E1000_READ_REG ( hw, E1000_RDBAL(0) ) );        DBG ( "E1000_RDLEN(0): %d/n",     E1000_READ_REG ( hw, E1000_RDLEN(0) ) );        DBG ( "E1000_RCTL:  %#08x/n",  E1000_READ_REG ( hw, E1000_RCTL ) );}

/** *  e1000_phy_hw_reset_82543 - PHY hardware reset *  @hw: pointer to the HW structure * *  Sets the PHY_RESET_DIR bit in the extended device control register *  to put the PHY into a reset and waits for completion.  Once the reset *  has been accomplished, clear the PHY_RESET_DIR bit to take the PHY out *  of reset. **/static s32 e1000_phy_hw_reset_82543(struct e1000_hw *hw){	u32 ctrl_ext;	s32 ret_val;	DEBUGFUNC("e1000_phy_hw_reset_82543");	/*	 * Read the Extended Device Control Register, assert the PHY_RESET_DIR	 * bit to put the PHY into reset...	 */	ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);	ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;	ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;	E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);	E1000_WRITE_FLUSH(hw);	msec_delay(10);	/* ...then take it out of reset. */	ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;	E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);	E1000_WRITE_FLUSH(hw);	usec_delay(150);	if (!(hw->phy.ops.get_cfg_done))		return E1000_SUCCESS;	ret_val = hw->phy.ops.get_cfg_done(hw);	return ret_val;}

/** * e1000_close - Disables a network interface * * @v netdev	network interface device structure * **/static voide1000_close ( struct net_device *netdev ){	struct e1000_adapter *adapter = netdev_priv ( netdev );	struct e1000_hw *hw = &adapter->hw;	uint32_t rctl;	uint32_t icr;	DBG ( "e1000_close/n" );		/* Acknowledge interrupts */	icr = E1000_READ_REG ( hw, ICR );	e1000_irq_disable ( adapter );	/* disable receives */	rctl = E1000_READ_REG ( hw, RCTL );	E1000_WRITE_REG ( hw, RCTL, rctl & ~E1000_RCTL_EN );	E1000_WRITE_FLUSH ( hw );	e1000_reset_hw ( hw );	e1000_free_tx_resources ( adapter );	e1000_free_rx_resources ( adapter );}

/** * e1000_irq_enable - Enable default interrupt generation settings * * @v adapter	e1000 private structure **/static voide1000_irq_enable ( struct e1000_adapter *adapter ){	E1000_WRITE_REG ( &adapter->hw, IMS, E1000_IMS_RXDMT0 |			                     E1000_IMS_RXSEQ );	E1000_WRITE_FLUSH ( &adapter->hw );}

/* * Disable interrupt on the specificed rx ring. */intigb_rx_ring_intr_disable(mac_intr_handle_t intrh){	igb_rx_ring_t *rx_ring = (igb_rx_ring_t *)intrh;	igb_t *igb = rx_ring->igb;	struct e1000_hw *hw = &igb->hw;	uint32_t index = rx_ring->index;	if (igb->intr_type == DDI_INTR_TYPE_MSIX) {		/* Interrupt disabling for MSI-X */		igb->eims_mask &= ~(E1000_EICR_RX_QUEUE0 << index);		E1000_WRITE_REG(hw, E1000_EIMC,		    (E1000_EICR_RX_QUEUE0 << index));		E1000_WRITE_REG(hw, E1000_EIAC, igb->eims_mask);	} else {		ASSERT(index == 0);		/* Interrupt disabling for MSI and legacy */		igb->ims_mask &= ~E1000_IMS_RXT0;		E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_RXT0);	}	E1000_WRITE_FLUSH(hw);	return (0);}

/** *  e1000_write_vfta_82543 - Write value to VLAN filter table *  @hw: pointer to the HW structure *  @offset: the 32-bit offset in which to write the value to. *  @value: the 32-bit value to write at location offset. * *  This writes a 32-bit value to a 32-bit offset in the VLAN filter *  table. **/static void e1000_write_vfta_82543(struct e1000_hw *hw, u32 offset, u32 value){	u32 temp;	DEBUGFUNC("e1000_write_vfta_82543");	if ((hw->mac.type == e1000_82544) && (offset & 1)) {		temp = E1000_READ_REG_ARRAY(hw, E1000_VFTA, offset - 1);		E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);		E1000_WRITE_FLUSH(hw);		E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset - 1, temp);		E1000_WRITE_FLUSH(hw);	} else {		e1000_write_vfta_generic(hw, offset, value);	}}

/** * e1000_configure_tx - Configure 8254x Transmit Unit after Reset * @adapter: board private structure * * Configure the Tx unit of the MAC after a reset. **/static voide1000_configure_tx ( struct e1000_adapter *adapter ){	struct e1000_hw *hw = &adapter->hw;	uint32_t tctl;	DBG ( "e1000_configure_tx/n" );	E1000_WRITE_REG ( hw, TDBAH, 0 );	E1000_WRITE_REG ( hw, TDBAL, virt_to_bus ( adapter->tx_base ) );	E1000_WRITE_REG ( hw, TDLEN, adapter->tx_ring_size );			          DBG ( "TDBAL: %#08x/n",  E1000_READ_REG ( hw, TDBAL ) );        DBG ( "TDLEN: %d/n",     E1000_READ_REG ( hw, TDLEN ) );	/* Setup the HW Tx Head and Tail descriptor pointers */	E1000_WRITE_REG ( hw, TDH, 0 );	E1000_WRITE_REG ( hw, TDT, 0 );	adapter->tx_head = 0;	adapter->tx_tail = 0;	adapter->tx_fill_ctr = 0;	/* Setup Transmit Descriptor Settings for eop descriptor */	tctl = E1000_TCTL_PSP | E1000_TCTL_EN |		(E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT) | 		(E1000_HDX_COLLISION_DISTANCE << E1000_COLD_SHIFT);	e1000_config_collision_dist ( hw );	E1000_WRITE_REG ( hw, TCTL, tctl );        E1000_WRITE_FLUSH ( hw );}

/** *  e1000_lower_mdi_clk_82543 - Lower Management Data Input clock *  @hw: pointer to the HW structure *  @ctrl: pointer to the control register * *  Lower the management data input clock by clearing the MDC bit in the *  control register. **/static void e1000_lower_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl){	/*	 * Lower the clock input to the Management Data Clock (by clearing the	 * MDC bit), and then delay a sufficient amount of time.	 */	E1000_WRITE_REG(hw, E1000_CTRL, (*ctrl & ~E1000_CTRL_MDC));	E1000_WRITE_FLUSH(hw);	usec_delay(10);}

/** *  e1000_raise_mdi_clk_82543 - Raise Management Data Input clock *  @hw: pointer to the HW structure *  @ctrl: pointer to the control register * *  Raise the management data input clock by setting the MDC bit in the control *  register. **/STATIC void e1000_raise_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl){	/*	 * Raise the clock input to the Management Data Clock (by setting the	 * MDC bit), and then delay a sufficient amount of time.	 */	E1000_WRITE_REG(hw, E1000_CTRL, (*ctrl | E1000_CTRL_MDC));	E1000_WRITE_FLUSH(hw);	usec_delay(10);}

/* * e1000_rar_set_vmdq - Clear the RAR registers */voide1000_rar_clear(struct e1000_hw *hw, uint32_t index){	uint32_t rar_high;	/* Make the hardware the Address invalid by setting the clear bit */	rar_high = ~E1000_RAH_AV;	E1000_WRITE_REG_ARRAY(hw, E1000_RA, ((index << 1) + 1), rar_high);	E1000_WRITE_FLUSH(hw);}

/** *  e1000_reset_hw_82540 - Reset hardware *  @hw: pointer to the HW structure * *  This resets the hardware into a known state. **/static s32 e1000_reset_hw_82540(struct e1000_hw *hw){	u32 ctrl, manc;	s32 ret_val = E1000_SUCCESS;	DEBUGFUNC("e1000_reset_hw_82540");	DEBUGOUT("Masking off all interrupts/n");	E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF);	E1000_WRITE_REG(hw, E1000_RCTL, 0);	E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);	E1000_WRITE_FLUSH(hw);	/*	 * Delay to allow any outstanding PCI transactions to complete	 * before resetting the device.	 */	msec_delay(10);	ctrl = E1000_READ_REG(hw, E1000_CTRL);	DEBUGOUT("Issuing a global reset to 82540/82545/82546 MAC/n");	switch (hw->mac.type) {	case e1000_82545_rev_3:	case e1000_82546_rev_3:		E1000_WRITE_REG(hw, E1000_CTRL_DUP, ctrl | E1000_CTRL_RST);		break;	default:		/*		 * These controllers can't ack the 64-bit write when		 * issuing the reset, so we use IO-mapping as a		 * workaround to issue the reset.		 */		E1000_WRITE_REG_IO(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);		break;	}	/* Wait for EEPROM reload */	msec_delay(5);	/* Disable HW ARPs on ASF enabled adapters */	manc = E1000_READ_REG(hw, E1000_MANC);	manc &= ~E1000_MANC_ARP_EN;	E1000_WRITE_REG(hw, E1000_MANC, manc);	E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);	E1000_READ_REG(hw, E1000_ICR);	return ret_val;}

/** *  e1000_shift_in_mdi_bits_82543 - Shift data bits in from the PHY *  @hw: pointer to the HW structure * *  In order to read a register from the PHY, we need to shift 18 bits *  in from the PHY.  Bits are "shifted in" by raising the clock input to *  the PHY (setting the MDC bit), and then reading the value of the data out *  MDIO bit. **/static u16 e1000_shift_in_mdi_bits_82543(struct e1000_hw *hw){	u32 ctrl;	u16 data = 0;	u8 i;	/*	 * In order to read a register from the PHY, we need to shift in a	 * total of 18 bits from the PHY.  The first two bit (turnaround)	 * times are used to avoid contention on the MDIO pin when a read	 * operation is performed.  These two bits are ignored by us and	 * thrown away.  Bits are "shifted in" by raising the input to the	 * Management Data Clock (setting the MDC bit) and then reading the	 * value of the MDIO bit.	 */	ctrl = E1000_READ_REG(hw, E1000_CTRL);	/*	 * Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as	 * input.	 */	ctrl &= ~E1000_CTRL_MDIO_DIR;	ctrl &= ~E1000_CTRL_MDIO;	E1000_WRITE_REG(hw, E1000_CTRL, ctrl);	E1000_WRITE_FLUSH(hw);	/*	 * Raise and lower the clock before reading in the data.  This accounts	 * for the turnaround bits.  The first clock occurred when we clocked	 * out the last bit of the Register Address.	 */	e1000_raise_mdi_clk_82543(hw, &ctrl);	e1000_lower_mdi_clk_82543(hw, &ctrl);	for (data = 0, i = 0; i < 16; i++) {		data <<= 1;		e1000_raise_mdi_clk_82543(hw, &ctrl);		ctrl = E1000_READ_REG(hw, E1000_CTRL);		/* Check to see if we shifted in a "1". */		if (ctrl & E1000_CTRL_MDIO)			data |= 1;		e1000_lower_mdi_clk_82543(hw, &ctrl);	}	e1000_raise_mdi_clk_82543(hw, &ctrl);	e1000_lower_mdi_clk_82543(hw, &ctrl);	return data;}

/** *  e1000_init_hw_82543 - Initialize hardware *  @hw: pointer to the HW structure * *  This inits the hardware readying it for operation. **/static s32 e1000_init_hw_82543(struct e1000_hw *hw){	struct e1000_mac_info *mac = &hw->mac;	struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543;	u32 ctrl;	s32 ret_val;	u16 i;	DEBUGFUNC("e1000_init_hw_82543");	/* Disabling VLAN filtering */	E1000_WRITE_REG(hw, E1000_VET, 0);	mac->ops.clear_vfta(hw);	/* Setup the receive address. */	e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);	/* Zero out the Multicast HASH table */	DEBUGOUT("Zeroing the MTA/n");	for (i = 0; i < mac->mta_reg_count; i++) {		E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);		E1000_WRITE_FLUSH(hw);	}	/*	 * Set the PCI priority bit correctly in the CTRL register.  This	 * determines if the adapter gives priority to receives, or if it	 * gives equal priority to transmits and receives.	 */	if (hw->mac.type == e1000_82543 && dev_spec->dma_fairness) {		ctrl = E1000_READ_REG(hw, E1000_CTRL);		E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PRIOR);	}	e1000_pcix_mmrbc_workaround_generic(hw);	/* Setup link and flow control */	ret_val = mac->ops.setup_link(hw);	/*	 * Clear all of the statistics registers (clear on read).  It is	 * important that we do this after we have tried to establish link	 * because the symbol error count will increment wildly if there	 * is no link.	 */	e1000_clear_hw_cntrs_82543(hw);	return ret_val;}

/** *  e1000_reset_hw_82543 - Reset hardware *  @hw: pointer to the HW structure * *  This resets the hardware into a known state. **/static s32 e1000_reset_hw_82543(struct e1000_hw *hw){	u32 ctrl;	s32 ret_val = E1000_SUCCESS;	DEBUGFUNC("e1000_reset_hw_82543");	DEBUGOUT("Masking off all interrupts/n");	E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);	E1000_WRITE_REG(hw, E1000_RCTL, 0);	E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);	E1000_WRITE_FLUSH(hw);	e1000_set_tbi_sbp_82543(hw, FALSE);	/*	 * Delay to allow any outstanding PCI transactions to complete before	 * resetting the device	 */	msec_delay(10);	ctrl = E1000_READ_REG(hw, E1000_CTRL);	DEBUGOUT("Issuing a global reset to 82543/82544 MAC/n");	if (hw->mac.type == e1000_82543) {		E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);	} else {		/*		 * The 82544 can't ACK the 64-bit write when issuing the		 * reset, so use IO-mapping as a workaround.		 */		E1000_WRITE_REG_IO(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);	}	/*	 * After MAC reset, force reload of NVM to restore power-on	 * settings to device.	 */	hw->nvm.ops.reload(hw);	msec_delay(2);	/* Masking off and clearing any pending interrupts */	E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);	E1000_READ_REG(hw, E1000_ICR);	return ret_val;}

/** *  e1000_shift_out_mdi_bits_82543 - Shift data bits our to the PHY *  @hw: pointer to the HW structure *  @data: data to send to the PHY *  @count: number of bits to shift out * *  We need to shift 'count' bits out to the PHY.  So, the value in the *  "data" parameter will be shifted out to the PHY one bit at a time. *  In order to do this, "data" must be broken down into bits. **/STATIC void e1000_shift_out_mdi_bits_82543(struct e1000_hw *hw, u32 data,					   u16 count){	u32 ctrl, mask;	/*	 * We need to shift "count" number of bits out to the PHY.  So, the	 * value in the "data" parameter will be shifted out to the PHY one	 * bit at a time.  In order to do this, "data" must be broken down	 * into bits.	 */	mask = 0x01;	mask <<= (count - 1);	ctrl = E1000_READ_REG(hw, E1000_CTRL);	/* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */	ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);	while (mask) {		/*		 * A "1" is shifted out to the PHY by setting the MDIO bit to		 * "1" and then raising and lowering the Management Data Clock.		 * A "0" is shifted out to the PHY by setting the MDIO bit to		 * "0" and then raising and lowering the clock.		 */		if (data & mask)			ctrl |= E1000_CTRL_MDIO;		else			ctrl &= ~E1000_CTRL_MDIO;		E1000_WRITE_REG(hw, E1000_CTRL, ctrl);		E1000_WRITE_FLUSH(hw);		usec_delay(10);		e1000_raise_mdi_clk_82543(hw, &ctrl);		e1000_lower_mdi_clk_82543(hw, &ctrl);		mask >>= 1;	}}

/** *  e1000_setup_fiber_link_82543 - Setup link for fiber *  @hw: pointer to the HW structure * *  Configures collision distance and flow control for fiber links.  Upon *  successful setup, poll for link. **/static s32 e1000_setup_fiber_link_82543(struct e1000_hw *hw){	u32 ctrl;	s32 ret_val;	DEBUGFUNC("e1000_setup_fiber_link_82543");	ctrl = E1000_READ_REG(hw, E1000_CTRL);	/* Take the link out of reset */	ctrl &= ~E1000_CTRL_LRST;	e1000_config_collision_dist_generic(hw);	ret_val = e1000_commit_fc_settings_generic(hw);	if (ret_val)		goto out;	DEBUGOUT("Auto-negotiation enabled/n");	E1000_WRITE_REG(hw, E1000_CTRL, ctrl);	E1000_WRITE_FLUSH(hw);	msec_delay(1);	/*	 * For these adapters, the SW definable pin 1 is cleared when the	 * optics detect a signal.  If we have a signal, then poll for a	 * "Link-Up" indication.	 */	if (!(E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) {		ret_val = e1000_poll_fiber_serdes_link_generic(hw);	} else {		DEBUGOUT("No signal detected/n");	}out:	return ret_val;}

//.........这里部分代码省略.........#ifdef HAVE_PTP_CLOCK_INFO_GETTIME64		adapter->ptp_caps.gettime64 = igb_ptp_gettime64_82576;		adapter->ptp_caps.settime64 = igb_ptp_settime64_82576;#else		adapter->ptp_caps.gettime = igb_ptp_gettime_82576;		adapter->ptp_caps.settime = igb_ptp_settime_82576;#endif		adapter->ptp_caps.enable = igb_ptp_feature_enable;		adapter->cc.read = igb_ptp_read_82580;		adapter->cc.mask = CLOCKSOURCE_MASK(IGB_NBITS_82580);		adapter->cc.mult = 1;		adapter->cc.shift = 0;		/* Enable the timer functions by clearing bit 31. */		E1000_WRITE_REG(hw, E1000_TSAUXC, 0x0);		break;	case e1000_i210:	case e1000_i211:#ifdef HAVE_PTP_1588_CLOCK_PINS		for (i = 0; i < IGB_N_SDP; i++) {			struct ptp_pin_desc *ppd = &adapter->sdp_config[i];			snprintf(ppd->name, sizeof(ppd->name), "SDP%d", i);			ppd->index = i;			ppd->func = PTP_PF_NONE;		}#endif /* HAVE_PTP_1588_CLOCK_PINS */		snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr);		adapter->ptp_caps.owner = THIS_MODULE;		adapter->ptp_caps.max_adj = 62499999;		adapter->ptp_caps.n_ext_ts = IGB_N_EXTTS;		adapter->ptp_caps.n_per_out = IGB_N_PEROUT;#ifdef HAVE_PTP_1588_CLOCK_PINS		adapter->ptp_caps.n_pins = IGB_N_SDP;#endif /* HAVE_PTP_1588_CLOCK_PINS */		adapter->ptp_caps.pps = 1;#ifdef HAVE_PTP_1588_CLOCK_PINS		adapter->ptp_caps.pin_config = adapter->sdp_config;#endif /* HAVE_PTP_1588_CLOCK_PINS */		adapter->ptp_caps.adjfreq = igb_ptp_adjfreq_82580;		adapter->ptp_caps.adjtime = igb_ptp_adjtime_i210;#ifdef HAVE_PTP_CLOCK_INFO_GETTIME64		adapter->ptp_caps.gettime64 = igb_ptp_gettime64_i210;		adapter->ptp_caps.settime64 = igb_ptp_settime64_i210;#else		adapter->ptp_caps.gettime = igb_ptp_gettime_i210;		adapter->ptp_caps.settime = igb_ptp_settime_i210;#endif		adapter->ptp_caps.enable = igb_ptp_feature_enable_i210;#ifdef HAVE_PTP_1588_CLOCK_PINS		adapter->ptp_caps.verify = igb_ptp_verify_pin;#endif /* HAVE_PTP_1588_CLOCK_PINS */		/* Enable the timer functions by clearing bit 31. */		E1000_WRITE_REG(hw, E1000_TSAUXC, 0x0);		break;	default:		adapter->ptp_clock = NULL;		return;	}	E1000_WRITE_FLUSH(hw);	spin_lock_init(&adapter->tmreg_lock);	INIT_WORK(&adapter->ptp_tx_work, igb_ptp_tx_work);	/* Initialize the clock and overflow work for devices that need it. */	if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) {		struct timespec64 ts = ktime_to_timespec64(ktime_get_real());		igb_ptp_settime64_i210(&adapter->ptp_caps, &ts);	} else {		timecounter_init(&adapter->tc, &adapter->cc,				 ktime_to_ns(ktime_get_real()));		INIT_DELAYED_WORK(&adapter->ptp_overflow_work,				  igb_ptp_overflow_check_82576);		schedule_delayed_work(&adapter->ptp_overflow_work,				      IGB_SYSTIM_OVERFLOW_PERIOD);	}	/* Initialize the time sync interrupts for devices that support it. */	if (hw->mac.type >= e1000_82580) {		E1000_WRITE_REG(hw, E1000_TSIM, TSYNC_INTERRUPTS);		E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_TS);	}	adapter->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE;	adapter->tstamp_config.tx_type = HWTSTAMP_TX_OFF;	adapter->ptp_clock = ptp_clock_register(&adapter->ptp_caps,						&adapter->pdev->dev);	if (IS_ERR(adapter->ptp_clock)) {		adapter->ptp_clock = NULL;		dev_err(&adapter->pdev->dev, "ptp_clock_register failed/n");	} else {		dev_info(&adapter->pdev->dev, "added PHC on %s/n",			 adapter->netdev->name);		adapter->flags |= IGB_FLAG_PTP;	}}

/** * e1000_irq_force - trigger interrupt * * @v adapter	e1000 private structure **/static voide1000_irq_force ( struct e1000_adapter *adapter ){	E1000_WRITE_REG ( &adapter->hw, ICS, E1000_ICS_RXDMT0 );	E1000_WRITE_FLUSH ( &adapter->hw );}

//.........这里部分代码省略.........		break;	case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:	case HWTSTAMP_FILTER_ALL:		/*		 * 82576 cannot timestamp all packets, which it needs to do to		 * support both V1 Sync and Delay_Req messages		 */		if (hw->mac.type != e1000_82576) {			tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;			config.rx_filter = HWTSTAMP_FILTER_ALL;			break;		}		/* fall through */	default:		config.rx_filter = HWTSTAMP_FILTER_NONE;		return -ERANGE;	}	if (hw->mac.type == e1000_82575) {		if (tsync_rx_ctl | tsync_tx_ctl)			return -EINVAL;		return 0;	}	/*	 * Per-packet timestamping only works if all packets are	 * timestamped, so enable timestamping in all packets as	 * long as one rx filter was configured.	 */	if ((hw->mac.type >= e1000_82580) && tsync_rx_ctl) {		tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;		tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;		config.rx_filter = HWTSTAMP_FILTER_ALL;		is_l2 = true;		is_l4 = true;		if ((hw->mac.type == e1000_i210) ||		    (hw->mac.type == e1000_i211)) {			regval = E1000_READ_REG(hw, E1000_RXPBS);			regval |= E1000_RXPBS_CFG_TS_EN;			E1000_WRITE_REG(hw, E1000_RXPBS, regval);		}	}	/* enable/disable TX */	regval = E1000_READ_REG(hw, E1000_TSYNCTXCTL);	regval &= ~E1000_TSYNCTXCTL_ENABLED;	regval |= tsync_tx_ctl;	E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, regval);	/* enable/disable RX */	regval = E1000_READ_REG(hw, E1000_TSYNCRXCTL);	regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK);	regval |= tsync_rx_ctl;	E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, regval);	/* define which PTP packets are time stamped */	E1000_WRITE_REG(hw, E1000_TSYNCRXCFG, tsync_rx_cfg);	/* define ethertype filter for timestamped packets */	if (is_l2)		E1000_WRITE_REG(hw, E1000_ETQF(3),		     (E1000_ETQF_FILTER_ENABLE | /* enable filter */		      E1000_ETQF_1588 | /* enable timestamping */		      ETH_P_1588));     /* 1588 eth protocol type */	else		E1000_WRITE_REG(hw, E1000_ETQF(3), 0);#define PTP_PORT 319	/* L4 Queue Filter[3]: filter by destination port and protocol */	if (is_l4) {		u32 ftqf = (IPPROTO_UDP /* UDP */			| E1000_FTQF_VF_BP /* VF not compared */			| E1000_FTQF_1588_TIME_STAMP /* Enable Timestamping */			| E1000_FTQF_MASK); /* mask all inputs */		ftqf &= ~E1000_FTQF_MASK_PROTO_BP; /* enable protocol check */		E1000_WRITE_REG(hw, E1000_IMIR(3), htons(PTP_PORT));		E1000_WRITE_REG(hw, E1000_IMIREXT(3),		     (E1000_IMIREXT_SIZE_BP | E1000_IMIREXT_CTRL_BP));		if (hw->mac.type == e1000_82576) {			/* enable source port check */			E1000_WRITE_REG(hw, E1000_SPQF(3), htons(PTP_PORT));			ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;		}		E1000_WRITE_REG(hw, E1000_FTQF(3), ftqf);	} else {		E1000_WRITE_REG(hw, E1000_FTQF(3), E1000_FTQF_MASK);	}	E1000_WRITE_FLUSH(hw);	/* clear TX/RX time stamp registers, just to be sure */	regval = E1000_READ_REG(hw, E1000_TXSTMPL);	regval = E1000_READ_REG(hw, E1000_TXSTMPH);	regval = E1000_READ_REG(hw, E1000_RXSTMPL);	regval = E1000_READ_REG(hw, E1000_RXSTMPH);	return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?		-EFAULT : 0;}

void igb_ptp_init(struct igb_adapter *adapter){	struct e1000_hw *hw = &adapter->hw;	struct net_device *netdev = adapter->netdev;	switch (hw->mac.type) {	case e1000_82576:		snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr);		adapter->ptp_caps.owner = THIS_MODULE;		adapter->ptp_caps.max_adj = 1000000000;		adapter->ptp_caps.n_ext_ts = 0;		adapter->ptp_caps.pps = 0;		adapter->ptp_caps.adjfreq = igb_ptp_adjfreq_82576;		adapter->ptp_caps.adjtime = igb_ptp_adjtime_82576;		adapter->ptp_caps.gettime = igb_ptp_gettime_82576;		adapter->ptp_caps.settime = igb_ptp_settime_82576;		adapter->ptp_caps.enable = igb_ptp_enable;		adapter->cc.read = igb_ptp_read_82576;		adapter->cc.mask = CLOCKSOURCE_MASK(64);		adapter->cc.mult = 1;		adapter->cc.shift = IGB_82576_TSYNC_SHIFT;		/* Dial the nominal frequency. */		E1000_WRITE_REG(hw, E1000_TIMINCA, INCPERIOD_82576 |						   INCVALUE_82576);		break;	case e1000_82580:	case e1000_i350:		snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr);		adapter->ptp_caps.owner = THIS_MODULE;		adapter->ptp_caps.max_adj = 62499999;		adapter->ptp_caps.n_ext_ts = 0;		adapter->ptp_caps.pps = 0;		adapter->ptp_caps.adjfreq = igb_ptp_adjfreq_82580;		adapter->ptp_caps.adjtime = igb_ptp_adjtime_82576;		adapter->ptp_caps.gettime = igb_ptp_gettime_82576;		adapter->ptp_caps.settime = igb_ptp_settime_82576;		adapter->ptp_caps.enable = igb_ptp_enable;		adapter->cc.read = igb_ptp_read_82580;		adapter->cc.mask = CLOCKSOURCE_MASK(IGB_NBITS_82580);		adapter->cc.mult = 1;		adapter->cc.shift = 0;		/* Enable the timer functions by clearing bit 31. */		E1000_WRITE_REG(hw, E1000_TSAUXC, 0x0);		break;	case e1000_i210:	case e1000_i211:		snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr);		adapter->ptp_caps.owner = THIS_MODULE;		adapter->ptp_caps.max_adj = 62499999;		adapter->ptp_caps.n_ext_ts = 0;		adapter->ptp_caps.pps = 0;		adapter->ptp_caps.adjfreq = igb_ptp_adjfreq_82580;		adapter->ptp_caps.adjtime = igb_ptp_adjtime_i210;		adapter->ptp_caps.gettime = igb_ptp_gettime_i210;		adapter->ptp_caps.settime = igb_ptp_settime_i210;		adapter->ptp_caps.enable = igb_ptp_enable;		/* Enable the timer functions by clearing bit 31. */		E1000_WRITE_REG(hw, E1000_TSAUXC, 0x0);		break;	default:		adapter->ptp_clock = NULL;		return;	}	E1000_WRITE_FLUSH(hw);	spin_lock_init(&adapter->tmreg_lock);	INIT_WORK(&adapter->ptp_tx_work, igb_ptp_tx_work);	/* Initialize the clock and overflow work for devices that need it. */	if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) {		struct timespec ts = ktime_to_timespec(ktime_get_real());		igb_ptp_settime_i210(&adapter->ptp_caps, &ts);	} else {		timecounter_init(&adapter->tc, &adapter->cc,				 ktime_to_ns(ktime_get_real()));		INIT_DELAYED_WORK(&adapter->ptp_overflow_work,				  igb_ptp_overflow_check);		schedule_delayed_work(&adapter->ptp_overflow_work,				      IGB_SYSTIM_OVERFLOW_PERIOD);	}	/* Initialize the time sync interrupts for devices that support it. */	if (hw->mac.type >= e1000_82580) {		E1000_WRITE_REG(hw, E1000_TSIM, E1000_TSIM_TXTS);		E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_TS);	}	adapter->ptp_clock = ptp_clock_register(&adapter->ptp_caps);	if (IS_ERR(adapter->ptp_clock)) {		adapter->ptp_clock = NULL;		dev_err(&adapter->pdev->dev, "ptp_clock_register failed/n");	} else {		dev_info(&adapter->pdev->dev, "added PHC on %s/n",			 adapter->netdev->name);		adapter->flags |= IGB_FLAG_PTP;	}//.........这里部分代码省略.........

/** * e1000_configure_rx - Configure 8254x Receive Unit after Reset * @adapter: board private structure * * Configure the Rx unit of the MAC after a reset. **/static voide1000_configure_rx ( struct e1000_adapter *adapter ){	struct e1000_hw *hw = &adapter->hw;	uint32_t rctl, rxdctl, mrqc, rxcsum;	DBG ( "e1000_configure_rx/n" );	/* disable receives while setting up the descriptors */	rctl = E1000_READ_REG ( hw, RCTL );	E1000_WRITE_REG ( hw, RCTL, rctl & ~E1000_RCTL_EN );	E1000_WRITE_FLUSH ( hw );	mdelay(10);	adapter->rx_curr = 0;	/* Setup the HW Rx Head and Tail Descriptor Pointers and	 * the Base and Length of the Rx Descriptor Ring */	 	E1000_WRITE_REG ( hw, RDBAL, virt_to_bus ( adapter->rx_base ) );	E1000_WRITE_REG ( hw, RDBAH, 0 );	E1000_WRITE_REG ( hw, RDLEN, adapter->rx_ring_size );	E1000_WRITE_REG ( hw, RDH, 0 );	if (hw->mac_type == e1000_82576)		E1000_WRITE_REG ( hw, RDT, 0 );	else		E1000_WRITE_REG ( hw, RDT, NUM_RX_DESC - 1 );	/* This doesn't seem to  be necessary for correct operation,	 * but it seems as well to be implicit	 */	if (hw->mac_type == e1000_82576) {		rxdctl = E1000_READ_REG ( hw, RXDCTL );		rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;		rxdctl &= 0xFFF00000;		rxdctl |= IGB_RX_PTHRESH;		rxdctl |= IGB_RX_HTHRESH << 8;		rxdctl |= IGB_RX_WTHRESH << 16;		E1000_WRITE_REG ( hw, RXDCTL, rxdctl );		E1000_WRITE_FLUSH ( hw );		rxcsum = E1000_READ_REG(hw, RXCSUM);		rxcsum &= ~( E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPPCSE );		E1000_WRITE_REG ( hw, RXCSUM, 0 );		/* The initial value for MRQC disables multiple receive		 * queues, however this setting is not recommended.		 * - Intel
C++ E1000_WRITE_REG函数代码示例
C++ E1000_READ_REG函数代码示例