自学教程：C++ E1000_WRITE_REG函数代码示例

/** * e1000_close - Disables a network interface * * @v netdev	network interface device structure * **/static voide1000_close ( struct net_device *netdev ){	struct e1000_adapter *adapter = netdev_priv ( netdev );	struct e1000_hw *hw = &adapter->hw;	uint32_t rctl;	uint32_t icr;	DBG ( "e1000_close/n" );		/* Acknowledge interrupts */	icr = E1000_READ_REG ( hw, ICR );	e1000_irq_disable ( adapter );	/* disable receives */	rctl = E1000_READ_REG ( hw, RCTL );	E1000_WRITE_REG ( hw, RCTL, rctl & ~E1000_RCTL_EN );	E1000_WRITE_FLUSH ( hw );	e1000_reset_hw ( hw );	e1000_free_tx_resources ( adapter );	e1000_free_rx_resources ( adapter );}

BOOLEAN WriteEepromWord(PADAPTER_STRUCT Adapter, UINT16 Reg, UINT16 Data) {    E1000_WRITE_REG(Eecd, E1000_EECS);    ShiftOutBits(Adapter, EEPROM_EWEN_OPCODE, 5);    ShiftOutBits(Adapter, Reg, 4);    StandBy(Adapter);    ShiftOutBits(Adapter, EEPROM_ERASE_OPCODE, 3);    ShiftOutBits(Adapter, Reg, 6);    if (!WaitEepromCommandDone(Adapter))        return (FALSE);    ShiftOutBits(Adapter, EEPROM_WRITE_OPCODE, 3);    ShiftOutBits(Adapter, Reg, 6);    ShiftOutBits(Adapter, Data, 16);    if (!WaitEepromCommandDone(Adapter))        return (FALSE);    ShiftOutBits(Adapter, EEPROM_EWDS_OPCODE, 5);    ShiftOutBits(Adapter, Reg, 4);    EepromCleanup(Adapter);    return (TRUE);}

/* * Set the promiscuity of the device. */intigb_m_promisc(void *arg, boolean_t on){	igb_t *igb = (igb_t *)arg;	uint32_t reg_val;	mutex_enter(&igb->gen_lock);	if (igb->igb_state & IGB_SUSPENDED) {		mutex_exit(&igb->gen_lock);		return (ECANCELED);	}	reg_val = E1000_READ_REG(&igb->hw, E1000_RCTL);	if (on)		reg_val |= (E1000_RCTL_UPE | E1000_RCTL_MPE);	else		reg_val &= (~(E1000_RCTL_UPE | E1000_RCTL_MPE));	E1000_WRITE_REG(&igb->hw, E1000_RCTL, reg_val);	mutex_exit(&igb->gen_lock);	if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) {		ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED);		return (EIO);	}	return (0);}

/** * e1000_irq_enable - Enable default interrupt generation settings * * @v adapter	e1000 private structure **/static voide1000_irq_enable ( struct e1000_adapter *adapter ){	E1000_WRITE_REG ( &adapter->hw, IMS, E1000_IMS_RXDMT0 |			                     E1000_IMS_RXSEQ );	E1000_WRITE_FLUSH ( &adapter->hw );}

/** *  e1000_read_mbx_pf - Read a message from the mailbox *  @hw: pointer to the HW structure *  @msg: The message buffer *  @size: Length of buffer *  @vf_number: the VF index * *  This function copies a message from the mailbox buffer to the caller's *  memory buffer.  The presumption is that the caller knows that there was *  a message due to a VF request so no polling for message is needed. **/static s32 e1000_read_mbx_pf(struct e1000_hw *hw, u32 *msg, u16 size,			     u16 vf_number){	s32 ret_val;	u16 i;	DEBUGFUNC("e1000_read_mbx_pf");	/* lock the mailbox to prevent pf/vf race condition */	ret_val = e1000_obtain_mbx_lock_pf(hw, vf_number);	if (ret_val)		goto out_no_read;	/* copy the message to the mailbox memory buffer */	for (i = 0; i < size; i++)		msg[i] = E1000_READ_REG_ARRAY(hw, E1000_VMBMEM(vf_number), i);	/* Acknowledge the message and release buffer */	E1000_WRITE_REG(hw, E1000_P2VMAILBOX(vf_number), E1000_P2VMAILBOX_ACK);	/* update stats */	hw->mbx.stats.msgs_rx++;out_no_read:	return ret_val;}

static voide1000_loopback_cleanup(struct e1000_adapter *adapter){	uint32_t rctl;	uint16_t phy_reg;	rctl = E1000_READ_REG(&adapter->hw, RCTL);	rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);	E1000_WRITE_REG(&adapter->hw, RCTL, rctl);	if(adapter->hw.media_type == e1000_media_type_copper ||	   ((adapter->hw.media_type == e1000_media_type_fiber ||	     adapter->hw.media_type == e1000_media_type_internal_serdes) &&	    (adapter->hw.mac_type == e1000_82545 ||	     adapter->hw.mac_type == e1000_82546 ||	     adapter->hw.mac_type == e1000_82545_rev_3 ||	     adapter->hw.mac_type == e1000_82546_rev_3))) {		adapter->hw.autoneg = TRUE;		e1000_read_phy_reg(&adapter->hw, PHY_CTRL, &phy_reg);		if(phy_reg & MII_CR_LOOPBACK) {			phy_reg &= ~MII_CR_LOOPBACK;			e1000_write_phy_reg(&adapter->hw, PHY_CTRL, phy_reg);			e1000_phy_reset(&adapter->hw);		}	}}

/** *  e1000_setup_link_82543 - Setup flow control and link settings *  @hw: pointer to the HW structure * *  Read the EEPROM to determine the initial polarity value and write the *  extended device control register with the information before calling *  the generic setup link function, which does the following: *  Determines which flow control settings to use, then configures flow *  control.  Calls the appropriate media-specific link configuration *  function.  Assuming the adapter has a valid link partner, a valid link *  should be established.  Assumes the hardware has previously been reset *  and the transmitter and receiver are not enabled. **/static s32 e1000_setup_link_82543(struct e1000_hw *hw){	u32 ctrl_ext;	s32  ret_val;	u16 data;	DEBUGFUNC("e1000_setup_link_82543");	/*	 * Take the 4 bits from NVM word 0xF that determine the initial	 * polarity value for the SW controlled pins, and setup the	 * Extended Device Control reg with that info.	 * This is needed because one of the SW controlled pins is used for	 * signal detection.  So this should be done before phy setup.	 */	if (hw->mac.type == e1000_82543) {		ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &data);		if (ret_val) {			DEBUGOUT("NVM Read Error/n");			ret_val = -E1000_ERR_NVM;			goto out;		}		ctrl_ext = ((data & NVM_WORD0F_SWPDIO_EXT_MASK) <<		            NVM_SWDPIO_EXT_SHIFT);		E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);	}	ret_val = e1000_setup_link_generic(hw);out:	return ret_val;}

/** *  e1000_obtain_mbx_lock_pf - obtain mailbox lock *  @hw: pointer to the HW structure *  @vf_number: the VF index * *  return SUCCESS if we obtained the mailbox lock **/static s32 e1000_obtain_mbx_lock_pf(struct e1000_hw *hw, u16 vf_number){	s32 ret_val = -E1000_ERR_MBX;	u32 p2v_mailbox;	int count = 10;	DEBUGFUNC("e1000_obtain_mbx_lock_pf");	do {		/* Take ownership of the buffer */		E1000_WRITE_REG(hw, E1000_P2VMAILBOX(vf_number),				E1000_P2VMAILBOX_PFU);		/* reserve mailbox for pf use */		p2v_mailbox = E1000_READ_REG(hw, E1000_P2VMAILBOX(vf_number));		if (p2v_mailbox & E1000_P2VMAILBOX_PFU) {			ret_val = E1000_SUCCESS;			break;		}		usec_delay(1000);	} while (count-- > 0);	return ret_val;}

STATIC VOID StandBy(PADAPTER_STRUCT Adapter) {    UINT32 EecdRegValue;    EecdRegValue = E1000_READ_REG(Eecd);    EecdRegValue &= ~(E1000_EECS | E1000_EESK);    E1000_WRITE_REG(Eecd, EecdRegValue);    DelayInMicroseconds(5);    EecdRegValue |= E1000_EECS;    E1000_WRITE_REG(Eecd, EecdRegValue);}

/** *  e1000_get_hw_semaphore_i210 - Acquire hardware semaphore *  @hw: pointer to the HW structure * *  Acquire the HW semaphore to access the PHY or NVM **/static s32 e1000_get_hw_semaphore_i210(struct e1000_hw *hw){	u32 swsm;	s32 ret_val = E1000_SUCCESS;	s32 timeout = hw->nvm.word_size + 1;	s32 i = 0;	DEBUGFUNC("e1000_get_hw_semaphore_i210");	/* Get the FW semaphore. */	for (i = 0; i < timeout; i++) {		swsm = E1000_READ_REG(hw, E1000_SWSM);		E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI);		/* Semaphore acquired if bit latched */		if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI)			break;		usec_delay(50);	}	if (i == timeout) {		/* Release semaphores */		e1000_put_hw_semaphore_generic(hw);		DEBUGOUT("Driver can't access the NVM/n");		ret_val = -E1000_ERR_NVM;		goto out;	}out:	return ret_val;}

/** *  e1000_write_mbx_pf - Places a message in the mailbox *  @hw: pointer to the HW structure *  @msg: The message buffer *  @size: Length of buffer *  @vf_number: the VF index * *  returns SUCCESS if it successfully copied message into the buffer **/static s32 e1000_write_mbx_pf(struct e1000_hw *hw, u32 *msg, u16 size,			      u16 vf_number){	s32 ret_val;	u16 i;	DEBUGFUNC("e1000_write_mbx_pf");	/* lock the mailbox to prevent pf/vf race condition */	ret_val = e1000_obtain_mbx_lock_pf(hw, vf_number);	if (ret_val)		goto out_no_write;	/* flush msg and acks as we are overwriting the message buffer */	e1000_check_for_msg_pf(hw, vf_number);	e1000_check_for_ack_pf(hw, vf_number);	/* copy the caller specified message to the mailbox memory buffer */	for (i = 0; i < size; i++)		E1000_WRITE_REG_ARRAY(hw, E1000_VMBMEM(vf_number), i, msg[i]);	/* Interrupt VF to tell it a message has been sent and release buffer*/	E1000_WRITE_REG(hw, E1000_P2VMAILBOX(vf_number), E1000_P2VMAILBOX_STS);	/* update stats */	hw->mbx.stats.msgs_tx++;out_no_write:	return ret_val;}

static int igb_ptp_adjfreq_82576(struct ptp_clock_info *ptp, s32 ppb){	struct igb_adapter *igb = container_of(ptp, struct igb_adapter,					       ptp_caps);	struct e1000_hw *hw = &igb->hw;	int neg_adj = 0;	u64 rate;	u32 incvalue;	if (ppb < 0) {		neg_adj = 1;		ppb = -ppb;	}	rate = ppb;	rate <<= 14;	rate = div_u64(rate, 1953125);	incvalue = 16 << IGB_82576_TSYNC_SHIFT;	if (neg_adj)		incvalue -= rate;	else		incvalue += rate;	E1000_WRITE_REG(hw, E1000_TIMINCA, INCPERIOD_82576			| (incvalue & INCVALUE_82576_MASK));	return 0;}

/** * e1000_reset - Put e1000 NIC in known initial state * * @v adapter	e1000 private structure **/void e1000_reset ( struct e1000_adapter *adapter ){	struct e1000_mac_info *mac = &adapter->hw.mac;	u32 pba = 0;	DBG ( "e1000_reset/n" );	switch (mac->type) {	case e1000_82542:	case e1000_82543:	case e1000_82544:	case e1000_82540:	case e1000_82541:	case e1000_82541_rev_2:		pba = E1000_PBA_48K;		break;	case e1000_82545:	case e1000_82545_rev_3:	case e1000_82546:	case e1000_82546_rev_3:		pba = E1000_PBA_48K;		break;	case e1000_82547:	case e1000_82547_rev_2:		pba = E1000_PBA_30K;		break;	case e1000_undefined:	case e1000_num_macs:		break;	}	E1000_WRITE_REG ( &adapter->hw, E1000_PBA, pba );	/* Allow time for pending master requests to run */	e1000_reset_hw ( &adapter->hw );	if ( mac->type >= e1000_82544 )		E1000_WRITE_REG ( &adapter->hw, E1000_WUC, 0 );	if ( e1000_init_hw ( &adapter->hw ) )		DBG ( "Hardware Error/n" );	e1000_reset_adaptive ( &adapter->hw );	e1000_get_phy_info ( &adapter->hw );	e1000_init_manageability ( adapter );}

/** * igb_ptp_reset - Re-enable the adapter for PTP following a reset. * @adapter: Board private structure. * * This function handles the reset work required to re-enable the PTP device. **/void igb_ptp_reset(struct igb_adapter *adapter){	struct e1000_hw *hw = &adapter->hw;	unsigned long flags;	if (!(adapter->flags & IGB_FLAG_PTP))		return;	/* reset the tstamp_config */	igb_ptp_set_timestamp_mode(adapter, &adapter->tstamp_config);	spin_lock_irqsave(&adapter->tmreg_lock, flags);	switch (adapter->hw.mac.type) {	case e1000_82576:		/* Dial the nominal frequency. */		E1000_WRITE_REG(hw, E1000_TIMINCA, INCPERIOD_82576 |						   INCVALUE_82576);		break;	case e1000_82580:	case e1000_i350:	case e1000_i354:	case e1000_i210:	case e1000_i211:		E1000_WRITE_REG(hw, E1000_TSAUXC, 0x0);		E1000_WRITE_REG(hw, E1000_TSSDP, 0x0);		E1000_WRITE_REG(hw, E1000_TSIM, TSYNC_INTERRUPTS);		E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_TS);		break;	default:		/* No work to do. */		goto out;	}	/* Re-initialize the timer. */	if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) {		struct timespec64 ts64 = ktime_to_timespec64(ktime_get_real());		igb_ptp_write_i210(adapter, &ts64);	} else {		timecounter_init(&adapter->tc, &adapter->cc,				 ktime_to_ns(ktime_get_real()));	}out:	spin_unlock_irqrestore(&adapter->tmreg_lock, flags);}

void dna_cleanup_rx_ring(struct igb_ring *rx_ring) {  struct igb_adapter	  *adapter = netdev_priv(rx_ring->netdev);  struct e1000_hw	  *hw = &adapter->hw;  union e1000_adv_rx_desc *rx_desc, *shadow_rx_desc;  u32 head = E1000_READ_REG(hw, E1000_RDH(rx_ring->reg_idx));  u32 tail;    /*  tail = E1000_READ_REG(hw, E1000_RDT(rx_ring->reg_idx))  u32 count = rx_ring->count;    if(unlikely(enable_debug))    printk("[DNA] dna_cleanup_rx_ring(%d): [head=%u][tail=%u]/n", rx_ring->queue_index, head, tail);  // We now point to the next slot where packets will be received  if(++tail == rx_ring->count) tail = 0;  while(count > 0) {    if(tail == head) break; // Do not go beyond head    rx_desc = IGB_RX_DESC(rx_ring, tail);    shadow_rx_desc = IGB_RX_DESC(rx_ring, tail + rx_ring->count);        if(rx_desc->wb.upper.status_error != 0) {      print_adv_rx_descr(rx_desc);      break;    }    // Writeback    rx_desc->wb.upper.status_error = 0;    rx_desc->read.hdr_addr = shadow_rx_desc->read.hdr_addr, rx_desc->read.pkt_addr = shadow_rx_desc->read.pkt_addr;    E1000_WRITE_REG(hw, E1000_RDT(rx_ring->reg_idx), tail);    if(unlikely(enable_debug))      printk("[DNA] dna_cleanup_rx_ring(%d): idx=%d/n", rx_ring->queue_index, tail);    if(++tail == rx_ring->count) tail = 0;    count--;  }  */  /* resetting all */  for (i=0; i<rx_ring->count; i++) {    rx_desc = IGB_RX_DESC(rx_ring, i);    shadow_rx_desc = IGB_RX_DESC(rx_ring, i + rx_ring->count);    rx_desc->wb.upper.status_error = 0;    rx_desc->read.hdr_addr = shadow_rx_desc->read.hdr_addr;    rx_desc->read.pkt_addr = shadow_rx_desc->read.pkt_addr;  }  if (head == 0) tail = rx_ring->count - 1;  else tail = head - 1;  E1000_WRITE_REG(hw, E1000_RDT(rx_ring->reg_idx), tail);}

/** * e1000_configure_rx - Configure 8254x Receive Unit after Reset * @adapter: board private structure * * Configure the Rx unit of the MAC after a reset. **/static void e1000e_configure_rx ( struct e1000_adapter *adapter ){	struct e1000_hw *hw = &adapter->hw;	uint32_t rctl;	DBGP ( "e1000_configure_rx/n" );	/* disable receives while setting up the descriptors */	rctl = E1000_READ_REG ( hw, E1000_RCTL );	E1000_WRITE_REG ( hw, E1000_RCTL, rctl & ~E1000_RCTL_EN );	e1e_flush();	mdelay(10);	adapter->rx_curr = 0;	/* Setup the HW Rx Head and Tail Descriptor Pointers and	 * the Base and Length of the Rx Descriptor Ring */	E1000_WRITE_REG ( hw, E1000_RDBAL(0), virt_to_bus ( adapter->rx_base ) );	E1000_WRITE_REG ( hw, E1000_RDBAH(0), 0 );	E1000_WRITE_REG ( hw, E1000_RDLEN(0), adapter->rx_ring_size );	E1000_WRITE_REG ( hw, E1000_RDH(0), 0 );	E1000_WRITE_REG ( hw, E1000_RDT(0), NUM_RX_DESC - 1 );	/* Enable Receives */	rctl |=	 E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_SZ_2048 |		 E1000_RCTL_MPE;	E1000_WRITE_REG ( hw, E1000_RCTL, rctl );	e1e_flush();	DBG ( "E1000_RDBAL(0): %#08x/n",  E1000_READ_REG ( hw, E1000_RDBAL(0) ) );	DBG ( "E1000_RDLEN(0): %d/n",	  E1000_READ_REG ( hw, E1000_RDLEN(0) ) );	DBG ( "E1000_RCTL:  %#08x/n",  E1000_READ_REG ( hw, E1000_RCTL ) );}

STATIC VOID LowerClock(PADAPTER_STRUCT Adapter, UINT32 * EecdRegValue) {    *EecdRegValue = *EecdRegValue & ~E1000_EESK;    E1000_WRITE_REG(Eecd, *EecdRegValue);    DelayInMicroseconds(50);}

/** *  e1000_lower_mdi_clk_82543 - Lower Management Data Input clock *  @hw: pointer to the HW structure *  @ctrl: pointer to the control register * *  Lower the management data input clock by clearing the MDC bit in the *  control register. **/static void e1000_lower_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl){	/*	 * Lower the clock input to the Management Data Clock (by clearing the	 * MDC bit), and then delay a sufficient amount of time.	 */	E1000_WRITE_REG(hw, E1000_CTRL, (*ctrl & ~E1000_CTRL_MDC));	E1000_WRITE_FLUSH(hw);	usec_delay(10);}

/** *  e1000_raise_mdi_clk_82543 - Raise Management Data Input clock *  @hw: pointer to the HW structure *  @ctrl: pointer to the control register * *  Raise the management data input clock by setting the MDC bit in the control *  register. **/STATIC void e1000_raise_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl){	/*	 * Raise the clock input to the Management Data Clock (by setting the	 * MDC bit), and then delay a sufficient amount of time.	 */	E1000_WRITE_REG(hw, E1000_CTRL, (*ctrl | E1000_CTRL_MDC));	E1000_WRITE_FLUSH(hw);	usec_delay(10);}

/** * e1000_init_manageability - disable interception of ARP packets * * @v adapter	e1000 private structure **/static void e1000_init_manageability ( struct e1000_adapter *adapter ){	if (adapter->en_mng_pt) {		u32 manc = E1000_READ_REG(&adapter->hw, E1000_MANC);		/* disable hardware interception of ARP */		manc &= ~(E1000_MANC_ARP_EN);		E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc);	}}

voidigb_writereg(device_t *dev, u_int32_t reg, u_int32_t data){	struct adapter	*adapter;	if (NULL == dev) return;	adapter = (struct adapter *)dev->private_data;	if (NULL == adapter) return;	E1000_WRITE_REG(&(adapter->hw), reg, data);}

static s32 e1000_check_for_bit_pf(struct e1000_hw *hw, u32 mask){	u32 mbvficr = E1000_READ_REG(hw, E1000_MBVFICR);	s32 ret_val = -E1000_ERR_MBX;	if (mbvficr & mask) {		ret_val = E1000_SUCCESS;		E1000_WRITE_REG(hw, E1000_MBVFICR, mask);	}	return ret_val;}

/** *  e1000_put_hw_semaphore_i210 - Release hardware semaphore *  @hw: pointer to the HW structure * *  Release hardware semaphore used to access the PHY or NVM **/static void e1000_put_hw_semaphore_i210(struct e1000_hw *hw){	u32 swsm;	DEBUGFUNC("e1000_put_hw_semaphore_i210");	swsm = E1000_READ_REG(hw, E1000_SWSM);	swsm &= ~E1000_SWSM_SWESMBI;	E1000_WRITE_REG(hw, E1000_SWSM, swsm);}

/** * e1000_configure_tx - Configure 8254x Transmit Unit after Reset * @adapter: board private structure * * Configure the Tx unit of the MAC after a reset. **/static voide1000_configure_tx ( struct e1000_adapter *adapter ){	struct e1000_hw *hw = &adapter->hw;	uint32_t tctl;	DBG ( "e1000_configure_tx/n" );	E1000_WRITE_REG ( hw, TDBAH, 0 );	E1000_WRITE_REG ( hw, TDBAL, virt_to_bus ( adapter->tx_base ) );	E1000_WRITE_REG ( hw, TDLEN, adapter->tx_ring_size );			          DBG ( "TDBAL: %#08x/n",  E1000_READ_REG ( hw, TDBAL ) );        DBG ( "TDLEN: %d/n",     E1000_READ_REG ( hw, TDLEN ) );	/* Setup the HW Tx Head and Tail descriptor pointers */	E1000_WRITE_REG ( hw, TDH, 0 );	E1000_WRITE_REG ( hw, TDT, 0 );	adapter->tx_head = 0;	adapter->tx_tail = 0;	adapter->tx_fill_ctr = 0;	/* Setup Transmit Descriptor Settings for eop descriptor */	tctl = E1000_TCTL_PSP | E1000_TCTL_EN |		(E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT) | 		(E1000_HDX_COLLISION_DISTANCE << E1000_COLD_SHIFT);	e1000_config_collision_dist ( hw );	E1000_WRITE_REG ( hw, TCTL, tctl );        E1000_WRITE_FLUSH ( hw );}

STATIC VOID EepromCleanup(PADAPTER_STRUCT Adapter) {    UINT32 EecdRegValue;    EecdRegValue = E1000_READ_REG(Eecd);    EecdRegValue &= ~(E1000_EECS | E1000_EEDI);    E1000_WRITE_REG(Eecd, EecdRegValue);    RaiseClock(Adapter, &EecdRegValue);    LowerClock(Adapter, &EecdRegValue);}