自学教程：C++ HWREG函数代码示例

//*****************************************************************************//// This is the main routine for performing an update from a mass storage// device.//// This function forms the main loop of the USB stick updater.  It polls for// a USB mass storage device to be connected,  Once a device is connected// it will attempt to read a firmware image from the device and load it into// flash.//// /return None.////*****************************************************************************voidUpdaterUSB(void){    //    // Loop forever, running the USB host driver.    //    while(1)    {        USBHCDMain();        //        // Check for a state change from the USB driver.        //        switch(g_eState)        {            //            // This state means that a mass storage device has been            // plugged in and enumerated.            //            case STATE_DEVICE_ENUM:            {                //                // Attempt to read the application image from the storage                // device and load it into flash memory.                //                if(ReadAppAndProgram())                {                    //                    // There was some error reading or programming the app,                    // so reset the state to no device which will cause a                    // wait for a new device to be plugged in.                    //                    g_eState = STATE_NO_DEVICE;                }                else                {                    //                    // User app load and programming was successful, so reboot                    // the micro.  Perform a software reset request.  This                    // will cause the microcontroller to reset; no further                    // code will be executed.                    //                    HWREG(NVIC_APINT) = NVIC_APINT_VECTKEY |                                        NVIC_APINT_SYSRESETREQ;                    //                    // The microcontroller should have reset, so this should                    // never be reached.  Just in case, loop forever.                    //                    while(1)                    {                    }                }                break;            }            //            // This state means that there is no device present, so just            // do nothing until something is plugged in.            //            case STATE_NO_DEVICE:            {                break;            }        }    }}

/** * /brief   Read the status of Write Posted Status register. * * /param   baseAdd       Base Address of the DMTimer Module Register. * * /return  This API returns the status of TWPS register. * **/unsigned int DMTimerWritePostedStatusGet(unsigned int baseAdd){    /* Return the status of TWPS register */    return (HWREG(baseAdd + DMTIMER_TWPS));}

static void vSerialTxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex ){portTickType xDelayPeriod;static unsigned long *pulRandomBytes = mainFIRST_PROGRAM_BYTES;	/* Co-routine MUST start with a call to crSTART. */	crSTART( xHandle );	for(;;)    {			/* Was the previously transmitted string received correctly? */		if( uxErrorStatus != pdPASS )		{			/* An error was encountered so set the error LED. */			vSetErrorLED();		}		/* The next character to Tx is the first in the string. */		cNextChar = mainFIRST_TX_CHAR;		UARTIntDisable( UART0_BASE, UART_INT_TX );		{			/* Send the first character. */			if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) )			{				HWREG( UART0_BASE + UART_O_DR ) = cNextChar;			}			/* Move the variable to the char to Tx on so the ISR transmits			the next character in the string once this one has completed. */			cNextChar++;		}		UARTIntEnable(UART0_BASE, UART_INT_TX);		/* Toggle the LED to show a new string is being transmitted. */        vParTestToggleLED( mainCOMMS_TX_LED );		/* Delay before we start the string off again.  A pseudo-random delay		is used as this will provide a better test. */		xDelayPeriod = xTaskGetTickCount() + ( *pulRandomBytes );		pulRandomBytes++;		if( pulRandomBytes > mainTOTAL_PROGRAM_MEMORY )		{			pulRandomBytes = mainFIRST_PROGRAM_BYTES;		}		/* Make sure we don't wait too long... */		xDelayPeriod &= mainMAX_TX_DELAY;		/* ...but we do want to wait. */		if( xDelayPeriod < mainMIN_TX_DELAY )		{			xDelayPeriod = mainMIN_TX_DELAY;		}		/* Block for the random(ish) time. */		crDELAY( xHandle, xDelayPeriod );    }	/* Co-routine MUST end with a call to crEND. */	crEND();}

/** * /brief   Get the reload count value from the timer load register. * * /param   baseAdd       Base Address of the DMTimer Module Register. * * /return  This API returns the value present in DMTimer Load Register. * **/unsigned int DMTimerReloadGet(unsigned int baseAdd){    /* Return the contents of TLDR */    return (HWREG(baseAdd + DMTIMER_TLDR));}

/** * /brief   Read the status of IRQ_STATUS register. * * /param   baseAdd       Base Address of the DMTimer Module Register. * * /return  This API returns the status of IRQSTATUS register. * **/unsigned int DMTimerIntStatusGet(unsigned int baseAdd){    /* Return the status of IRQSTATUS register */    return (HWREG(baseAdd + DMTIMER_IRQSTATUS));}

static inline void SysTickMode_DeepSleep(void){	HWREG(NVIC_ST_RELOAD) = DEEPSLEEP_CPU / (1000/100) - 1;	HWREG(NVIC_ST_CURRENT) = 0;  // Clear SysTick}

static inline void SysTickMode_Run(void){	HWREG(NVIC_ST_RELOAD) = F_CPU / SYSTICKHZ - 1;	HWREG(NVIC_ST_CURRENT) = 0;}

//*****************************************************************************//// Handles the GPIO port C interrupt.//// This function is called when GPIO port C asserts its interrupt.  GPIO port// C is configured to generate an interrupt on the rising edge of the encoder// input signal.  The time between the current edge and the previous edge is// computed and used as a measure of the rotor speed.//// /return None.////*****************************************************************************voidGPIOCIntHandler(void){    unsigned long ulTime, ulNewTime;    //    // Clear the GPIO interrupt.    //    GPIOPinIntClear(PIN_ENCA_PORT, PIN_ENCA_PIN);    //    // Get the time of this edge.    //    ulNewTime = g_ulSpeedTime + HWREG(QEI0_BASE + QEI_O_TIME);    //    // Compute the time between this edge and the previous edge.    //    ulTime = ulNewTime - g_ulSpeedPrevious;    //    // Save the time of the current edge.    //    g_ulSpeedPrevious = ulNewTime;    //    // See if this edge should be skipped.    //    if(HWREGBITW(&g_ulSpeedFlags, FLAG_SKIP_BIT))    {        //        // This edge should be skipped, but an edge time now exists so the next        // edge should not be skipped.        //        HWREGBITW(&g_ulSpeedFlags, FLAG_SKIP_BIT) = 0;        //        // There is nothing further to be done.        //        return;    }    //    // Indicate that an edge has been seen to prevent the QEI interrupt handler    // from forcing the rotor speed to zero.    //    HWREGBITW(&g_ulSpeedFlags, FLAG_EDGE_BIT) = 1;    //    // Compute the new speed from the time between edges.    //    SpeedNewValue(((unsigned long)SYSTEM_CLOCK * (unsigned long)60) /                  (ulTime * (UI_PARAM_NUM_LINES + 1)));    //    // See if the edge time has become too small, meaning that the number of    // edges per second is too large.    //    if(ulTime < (SYSTEM_CLOCK / (MAX_EDGE_COUNT + EDGE_DELTA)))    {        //        // Edge counting mode should be used instead of edge timing mode.        //        HWREGBITW(&g_ulSpeedFlags, FLAG_COUNT_BIT) = 1;        //        // Disable the GPIO interrupt while using edge counting mode.        //        IntDisable(INT_GPIOC);        //        // Indicate that the first timing period should be skipped in edge        // count mode.        //        HWREGBITW(&g_ulSpeedFlags, FLAG_SKIP_BIT) = 1;    }}

ProtocolBitVector_tChipInfo_GetSupportedProtocol_BV( void ){   return ((ProtocolBitVector_t)( HWREG( PRCM_BASE + 0x1D4 ) & 0x0E ));}//*****************************************************************************//// ChipInfo_GetPackageType()////*****************************************************************************PackageType_tChipInfo_GetPackageType( void ){   PackageType_t packType = (PackageType_t)((      HWREG( FCFG1_BASE + FCFG1_O_USER_ID     ) &                          FCFG1_USER_ID_PKG_M ) >>                          FCFG1_USER_ID_PKG_S ) ;   if (( packType < PACKAGE_4x4    ) ||       ( packType > PACKAGE_7x7_Q1 )    )   {      packType = PACKAGE_Unknown;   }   return ( packType );}//*****************************************************************************//// ChipInfo_GetChipFamily()

void vs_ssi_writewait(void){  while(HWREG(SSI0_BASE + SSI_O_SR) & SSI_SR_BSY);  //busy?  return;}

//*****************************************************************************//// This is the main loop that runs the application.////*****************************************************************************intmain(void){    uint_fast32_t ui32LastTickCount;    bool bLastSuspend;    tRectangle sRect;    tContext sContext;    int_fast32_t i32CenterX;    //    // Enable lazy stacking for interrupt handlers.  This allows floating-point    // instructions to be used within interrupt handlers, but at the expense of    // extra stack usage.    //    ROM_FPULazyStackingEnable();    //    // Set the clocking to run from the PLL at 50MHz.    //    ROM_SysCtlClockSet(SYSCTL_SYSDIV_4 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN |                       SYSCTL_XTAL_16MHZ);    //    // Configure the required pins for USB operation.    //    ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB);    ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOG);    ROM_GPIOPinConfigure(GPIO_PG4_USB0EPEN);    ROM_GPIOPinTypeUSBDigital(GPIO_PORTG_BASE, GPIO_PIN_4);    ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOL);    ROM_GPIOPinTypeUSBAnalog(GPIO_PORTL_BASE, GPIO_PIN_6 | GPIO_PIN_7);    ROM_GPIOPinTypeUSBAnalog(GPIO_PORTB_BASE, GPIO_PIN_0 | GPIO_PIN_1);    //    // Erratum workaround for silicon revision A1.  VBUS must have pull-down.    //    if(CLASS_IS_BLIZZARD && REVISION_IS_A1)    {        HWREG(GPIO_PORTB_BASE + GPIO_O_PDR) |= GPIO_PIN_1;    }    //    // Enable the GPIO that is used for the on-board LED.    //    ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOG);    ROM_GPIOPinTypeGPIOOutput(GPIO_PORTG_BASE, GPIO_PIN_2);    ROM_GPIOPinWrite(GPIO_PORTG_BASE, GPIO_PIN_2, 0);    //    // Initialize the buttons driver    //    ButtonsInit();    //    // Initialize the display driver.    //    CFAL96x64x16Init();    //    // Initialize the graphics context and find the middle X coordinate.    //    GrContextInit(&sContext, &g_sCFAL96x64x16);    i32CenterX = GrContextDpyWidthGet(&sContext) / 2;    //    // Fill the top part of the screen with blue to create the banner.    //    sRect.i16XMin = 0;    sRect.i16YMin = 0;    sRect.i16XMax = GrContextDpyWidthGet(&sContext) - 1;    sRect.i16YMax = 9;    GrContextForegroundSet(&sContext, ClrDarkBlue);    GrRectFill(&sContext, &sRect);    //    // Change foreground for white text.    //    GrContextForegroundSet(&sContext, ClrWhite);    //    // Put the application name in the middle of the banner.    //    GrContextFontSet(&sContext, g_psFontFixed6x8);    GrStringDrawCentered(&sContext, "usb-dev-keyboard", -1, i32CenterX, 4, 0);    //    // Not configured initially.    //    g_bConnected = false;    g_bSuspended = false;    bLastSuspend = false;    //    // Initialize the USB stack for device mode.    ////.........这里部分代码省略.........

void vOLEDTask( void *pvParameters ){    xOLEDMessage xMessage;    unsigned portLONG ulY, ulMaxY;    static portCHAR cMessage[ mainMAX_MSG_LEN ];    extern volatile unsigned portLONG ulMaxJitter;    unsigned portBASE_TYPE uxUnusedStackOnEntry, uxUnusedStackNow;    const unsigned portCHAR *pucImage;    /* Functions to access the OLED.  The one used depends on the dev kit    being used. */    void ( *vOLEDInit )( unsigned portLONG ) = NULL;    void ( *vOLEDStringDraw )( const portCHAR *, unsigned portLONG, unsigned portLONG, unsigned portCHAR ) = NULL;    void ( *vOLEDImageDraw )( const unsigned portCHAR *, unsigned portLONG, unsigned portLONG, unsigned portLONG, unsigned portLONG ) = NULL;    void ( *vOLEDClear )( void ) = NULL;    /* Just for demo purposes. */    uxUnusedStackOnEntry = uxTaskGetStackHighWaterMark( NULL );    /* Map the OLED access functions to the driver functions that are appropriate    for the evaluation kit being used. */    switch( HWREG( SYSCTL_DID1 ) & SYSCTL_DID1_PRTNO_MASK )    {    case SYSCTL_DID1_PRTNO_2965	:        vOLEDInit = OSRAM128x64x4Init;        vOLEDStringDraw = OSRAM128x64x4StringDraw;        vOLEDImageDraw = OSRAM128x64x4ImageDraw;        vOLEDClear = OSRAM128x64x4Clear;        ulMaxY = mainMAX_ROWS_64;        pucImage = pucBasicBitmap;        break;    case SYSCTL_DID1_PRTNO_1968	:    case SYSCTL_DID1_PRTNO_6965	:    case SYSCTL_DID1_PRTNO_8962 :        vOLEDInit = RIT128x96x4Init;        vOLEDStringDraw = RIT128x96x4StringDraw;        vOLEDImageDraw = RIT128x96x4ImageDraw;        vOLEDClear = RIT128x96x4Clear;        ulMaxY = mainMAX_ROWS_96;        pucImage = pucBasicBitmap;        break;    default						:        vOLEDInit = vFormike128x128x16Init;        vOLEDStringDraw = vFormike128x128x16StringDraw;        vOLEDImageDraw = vFormike128x128x16ImageDraw;        vOLEDClear = vFormike128x128x16Clear;        ulMaxY = mainMAX_ROWS_128;        pucImage = pucGrLibBitmap;        break;    }    ulY = ulMaxY;    /* Initialise the OLED and display a startup message. */    vOLEDInit( ulSSI_FREQUENCY );    vOLEDStringDraw( "POWERED BY FreeRTOS", 0, 0, mainFULL_SCALE );    vOLEDImageDraw( pucImage, 0, mainCHARACTER_HEIGHT + 1, bmpBITMAP_WIDTH, bmpBITMAP_HEIGHT );    for( ;; )    {        /* Wait for a message to arrive that requires displaying. */        xQueueReceive( xOLEDQueue, &xMessage, portMAX_DELAY );        /* Write the message on the next available row. */        ulY += mainCHARACTER_HEIGHT;        if( ulY >= ulMaxY )        {            ulY = mainCHARACTER_HEIGHT;            vOLEDClear();            vOLEDStringDraw( pcWelcomeMessage, 0, 0, mainFULL_SCALE );        }        /* Display the message along with the maximum jitter time from the        high priority time test. */        sprintf( cMessage, "%s [%uns]", xMessage.pcMessage, ulMaxJitter * mainNS_PER_CLOCK );        vOLEDStringDraw( cMessage, 0, ulY, mainFULL_SCALE );    }}

//clears the pin on the host microcontroller that is attached to the 24l01's CSN pinvoid nrf24l01_set_csn(){//	nrf24l01_CSN_IOREGISTER |= nrf24l01_CSN_PINMASK;	HWREG(nrf24l01_CSN_IOREGISTER + (GPIO_O_DATA + (nrf24l01_CSN_PIN << 2))) = nrf24l01_CSN_PIN;}

//sets the pin on the host microcontroller that is attached to the 24l01's CSN pinvoid nrf24l01_clear_csn(){//	nrf24l01_CSN_IOREGISTER &= ~nrf24l01_CSN_PINMASK;	HWREG(nrf24l01_CSN_IOREGISTER + (GPIO_O_DATA + (nrf24l01_CSN_PIN << 2))) = 0;}

//*****************************************************************************////! Write the key into the Key Ram.////*****************************************************************************uint32_tCRYPTOAesLoadKey(uint32_t *pui32AesKey,                 uint32_t ui32KeyLocation){    //    // Check the arguments.    //    ASSERT((ui32KeyLocation == CRYPTO_KEY_AREA_0) |           (ui32KeyLocation == CRYPTO_KEY_AREA_1) |           (ui32KeyLocation == CRYPTO_KEY_AREA_2) |           (ui32KeyLocation == CRYPTO_KEY_AREA_3) |           (ui32KeyLocation == CRYPTO_KEY_AREA_4) |           (ui32KeyLocation == CRYPTO_KEY_AREA_5) |           (ui32KeyLocation == CRYPTO_KEY_AREA_6) |           (ui32KeyLocation == CRYPTO_KEY_AREA_7));    //    // Set current operating state of the Crypto module.    //    g_ui32CurrentAesOp = CRYPTO_AES_KEYL0AD;    //    // Disable the external interrupt to stop the interrupt form propagating    // from the module to the CM3.    //    IntDisable(INT_CRYPTO);    //    // Enable internal interrupts.    //    HWREG(CRYPTO_BASE + CRYPTO_O_IRQTYPE) = CRYPTO_INT_LEVEL;    HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) = CRYPTO_IRQEN_DMA_IN_DONE |                                           CRYPTO_IRQEN_RESULT_AVAIL;    //    // Configure master control module.    //    HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) &= (~CRYPTO_ALGSEL_KEY_STORE);    HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) |= CRYPTO_ALGSEL_KEY_STORE;    //    // Clear any outstanding events.    //    HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = (CRYPTO_IRQCLR_DMA_IN_DONE |                                            CRYPTO_IRQCLR_RESULT_AVAIL);    //    // Configure key store module for 128 bit operation.    //    HWREG(CRYPTO_BASE + CRYPTO_O_KEYSIZE) &= ~CRYPTO_KEYSIZE_SIZE_M;    HWREG(CRYPTO_BASE + CRYPTO_O_KEYSIZE) |= KEY_STORE_SIZE_128;    //    // Enable keys to write (e.g. Key 0).    //    HWREG(CRYPTO_BASE + CRYPTO_O_KEYWRITEAREA) = (0x00000001 << ui32KeyLocation);    //    // Enable Crypto DMA channel 0.    //    HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0CTL) |= CRYPTO_DMACH0CTL_EN;    //    // Base address of the key in ext. memory.    //    HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0EXTADDR) = (uint32_t)pui32AesKey;    //    // Total key length in bytes (e.g. 16 for 1 x 128-bit key).    // Writing the length of the key enables the DMA operation.    //    HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0LEN) = KEY_BLENGTH;    //    // Wait for the DMA operation to complete.    //    do    {        CPUdelay(1);    }    while(!(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & 0x00000001));    //    // Check for errors in DMA and key store.    //    if((HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) &            (CRYPTO_IRQSTAT_DMA_BUS_ERR |             CRYPTO_IRQSTAT_KEY_ST_WR_ERR)) == 0)    {        //        // Acknowledge/clear the interrupt and disable the master control.        //        HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = (CRYPTO_IRQCLR_DMA_IN_DONE |                                                CRYPTO_IRQCLR_RESULT_AVAIL);        HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = 0x00000000;//.........这里部分代码省略.........

//*****************************************************************************//// Demonstrate the use of the boot loader.////*****************************************************************************intmain(void){    tRectangle sRect;    //    // Set the clocking to run directly from the crystal.    //    ROM_SysCtlClockSet(SYSCTL_SYSDIV_1 | SYSCTL_USE_OSC | SYSCTL_OSC_MAIN |                       SYSCTL_XTAL_8MHZ);    //    // If running on Rev A0 silicon, write the FMPRE[2-3]/FMPPE[2-3] registers    // to zero.  This is a workaround to allow the mass erase in the ROM-based    // boot loader to succeed if a locked device recovery has been performed.    //    if(REVISION_IS_A0)    {        HWREG(FLASH_FMPPE2) = 0;        HWREG(FLASH_FMPPE3) = 0;        HWREG(FLASH_FMPRE2) = 0;        HWREG(FLASH_FMPRE3) = 0;    }    //    // Enable the UART and GPIO modules.    //    ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);    ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0);    //    // Make the UART pins be peripheral controlled.    //    ROM_GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1);    //    // Configure the UART for 115,200, 8-N-1 operation.    //    ROM_UARTConfigSetExpClk(UART0_BASE, ROM_SysCtlClockGet(), 115200,                            (UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE |                             UART_CONFIG_PAR_NONE));    //    // Initialize the display driver.    //    Formike128x128x16Init();    //    // Turn on the backlight.    //    Formike128x128x16BacklightOn();    //    // Initialize the graphics context.    //    GrContextInit(&g_sContext, &g_sFormike128x128x16);    //    // Fill the top 15 rows of the screen with blue to create the banner.    //    sRect.sXMin = 0;    sRect.sYMin = 0;    sRect.sXMax = GrContextDpyWidthGet(&g_sContext) - 1;    sRect.sYMax = 14;    GrContextForegroundSet(&g_sContext, ClrDarkBlue);    GrRectFill(&g_sContext, &sRect);    //    // Put a white box around the banner.    //    GrContextForegroundSet(&g_sContext, ClrWhite);    GrRectDraw(&g_sContext, &sRect);    //    // Put the application name in the middle of the banner.    //    GrContextFontSet(&g_sContext, &g_sFontFixed6x8);    GrStringDrawCentered(&g_sContext, "boot_demo1", -1,                         GrContextDpyWidthGet(&g_sContext) / 2, 7, 0);    //    // Indicate what is happening.    //    GrStringDrawCentered(&g_sContext, "The boot loader is", -1,                         GrContextDpyWidthGet(&g_sContext) / 2, 24, 0);    GrStringDrawCentered(&g_sContext, "now running and", -1,                         GrContextDpyWidthGet(&g_sContext) / 2, 32, 0);    GrStringDrawCentered(&g_sContext, "awaiting an update", -1,                         GrContextDpyWidthGet(&g_sContext) / 2, 40, 0);    GrStringDrawCentered(&g_sContext, "over UART0 at", -1,                         GrContextDpyWidthGet(&g_sContext) / 2, 48, 0);    GrStringDrawCentered(&g_sContext, "115200, 8-N-1.", -1,                         GrContextDpyWidthGet(&g_sContext) / 2, 56, 0);    ////.........这里部分代码省略.........

//*****************************************************************************//// The interrupt handler for the PB4 pin interrupt.  When triggered, this will// toggle the JTAG pins between JTAG and GPIO mode.////*****************************************************************************voidGPIOBIntHandler(void){    //    // Clear the GPIO interrupt.    //    ROM_GPIOPinIntClear(GPIO_PORTB_BASE, GPIO_PIN_4);    //    // Toggle the pin mode.    //    g_ulMode ^= 1;    //    // See if the pins should be in JTAG or GPIO mode.    //    if(g_ulMode == 0)    {        //        // Change PC0-3 into hardware (i.e. JTAG) pins.        //        HWREG(GPIO_PORTC_BASE + GPIO_O_LOCK) = GPIO_LOCK_KEY_DD;        HWREG(GPIO_PORTC_BASE + GPIO_O_CR) = 0x01;        HWREG(GPIO_PORTC_BASE + GPIO_O_AFSEL) |= 0x01;        HWREG(GPIO_PORTC_BASE + GPIO_O_LOCK) = GPIO_LOCK_KEY_DD;        HWREG(GPIO_PORTC_BASE + GPIO_O_CR) = 0x02;        HWREG(GPIO_PORTC_BASE + GPIO_O_AFSEL) |= 0x02;        HWREG(GPIO_PORTC_BASE + GPIO_O_LOCK) = GPIO_LOCK_KEY_DD;        HWREG(GPIO_PORTC_BASE + GPIO_O_CR) = 0x04;        HWREG(GPIO_PORTC_BASE + GPIO_O_AFSEL) |= 0x04;        HWREG(GPIO_PORTC_BASE + GPIO_O_LOCK) = GPIO_LOCK_KEY_DD;        HWREG(GPIO_PORTC_BASE + GPIO_O_CR) = 0x08;        HWREG(GPIO_PORTC_BASE + GPIO_O_AFSEL) |= 0x08;        HWREG(GPIO_PORTC_BASE + GPIO_O_LOCK) = GPIO_LOCK_KEY_DD;        HWREG(GPIO_PORTC_BASE + GPIO_O_CR) = 0x00;        HWREG(GPIO_PORTC_BASE + GPIO_O_LOCK) = 0;        //        // Turn on the LED to indicate that the pins are in JTAG mode.        //        ROM_GPIOPinWrite(GPIO_PORTD_BASE, GPIO_PIN_0, GPIO_PIN_0);    }    else    {        //        // Change PC0-3 into GPIO inputs.        //        HWREG(GPIO_PORTC_BASE + GPIO_O_LOCK) = GPIO_LOCK_KEY_DD;        HWREG(GPIO_PORTC_BASE + GPIO_O_CR) = 0x01;        HWREG(GPIO_PORTC_BASE + GPIO_O_AFSEL) &= 0xfe;        HWREG(GPIO_PORTC_BASE + GPIO_O_LOCK) = GPIO_LOCK_KEY_DD;        HWREG(GPIO_PORTC_BASE + GPIO_O_CR) = 0x02;        HWREG(GPIO_PORTC_BASE + GPIO_O_AFSEL) &= 0xfd;        HWREG(GPIO_PORTC_BASE + GPIO_O_LOCK) = GPIO_LOCK_KEY_DD;        HWREG(GPIO_PORTC_BASE + GPIO_O_CR) = 0x04;        HWREG(GPIO_PORTC_BASE + GPIO_O_AFSEL) &= 0xfb;        HWREG(GPIO_PORTC_BASE + GPIO_O_LOCK) = GPIO_LOCK_KEY_DD;        HWREG(GPIO_PORTC_BASE + GPIO_O_CR) = 0x08;        HWREG(GPIO_PORTC_BASE + GPIO_O_AFSEL) &= 0xf7;        HWREG(GPIO_PORTC_BASE + GPIO_O_LOCK) = GPIO_LOCK_KEY_DD;        HWREG(GPIO_PORTC_BASE + GPIO_O_CR) = 0x00;        HWREG(GPIO_PORTC_BASE + GPIO_O_LOCK) = 0;        ROM_GPIOPinTypeGPIOInput(GPIO_PORTC_BASE, (GPIO_PIN_0 | GPIO_PIN_1 |                                                   GPIO_PIN_2 | GPIO_PIN_3));        //        // Turn off the LED to indicate that the pins are in GPIO mode.        //        ROM_GPIOPinWrite(GPIO_PORTD_BASE, GPIO_PIN_0, 0);    }}

static inline void SysTickMode_DeepSleepCoarse(void){	HWREG(NVIC_ST_RELOAD) = DEEPSLEEP_CPU - 1;	HWREG(NVIC_ST_CURRENT) = 0;  // Clear SysTick}

void GPMCClkConfig(void){    HWREG(SOC_PRCM_REGS + CM_PER_L3S_CLKSTCTRL) |=                             CM_PER_L3S_CLKSTCTRL_CLKTRCTRL_SW_WKUP;    while((HWREG(SOC_PRCM_REGS + CM_PER_L3S_CLKSTCTRL) &     CM_PER_L3S_CLKSTCTRL_CLKTRCTRL) != CM_PER_L3S_CLKSTCTRL_CLKTRCTRL_SW_WKUP);    HWREG(SOC_PRCM_REGS + CM_PER_L3_CLKSTCTRL) |=                             CM_PER_L3_CLKSTCTRL_CLKTRCTRL_SW_WKUP;    while((HWREG(SOC_PRCM_REGS + CM_PER_L3_CLKSTCTRL) &     CM_PER_L3_CLKSTCTRL_CLKTRCTRL) != CM_PER_L3_CLKSTCTRL_CLKTRCTRL_SW_WKUP);    HWREG(SOC_PRCM_REGS + CM_PER_L3_INSTR_CLKCTRL) |=                             CM_PER_L3_INSTR_CLKCTRL_MODULEMODE_ENABLE;    while((HWREG(SOC_PRCM_REGS + CM_PER_L3_INSTR_CLKCTRL) &                               CM_PER_L3_INSTR_CLKCTRL_MODULEMODE) !=                                   CM_PER_L3_INSTR_CLKCTRL_MODULEMODE_ENABLE);    HWREG(SOC_PRCM_REGS + CM_PER_L3_CLKCTRL) |=                             CM_PER_L3_CLKCTRL_MODULEMODE_ENABLE;    while((HWREG(SOC_PRCM_REGS + CM_PER_L3_CLKCTRL) &        CM_PER_L3_CLKCTRL_MODULEMODE) != CM_PER_L3_CLKCTRL_MODULEMODE_ENABLE);    HWREG(SOC_PRCM_REGS + CM_PER_OCPWP_L3_CLKSTCTRL) |=                             CM_PER_OCPWP_L3_CLKSTCTRL_CLKTRCTRL_SW_WKUP;    while((HWREG(SOC_PRCM_REGS + CM_PER_OCPWP_L3_CLKSTCTRL) &                              CM_PER_OCPWP_L3_CLKSTCTRL_CLKTRCTRL) !=                                CM_PER_OCPWP_L3_CLKSTCTRL_CLKTRCTRL_SW_WKUP);    HWREG(SOC_PRCM_REGS + CM_PER_GPMC_CLKCTRL) |=                             CM_PER_GPMC_CLKCTRL_MODULEMODE_ENABLE;    while((HWREG(SOC_PRCM_REGS + CM_PER_GPMC_CLKCTRL) &      CM_PER_GPMC_CLKCTRL_MODULEMODE) != CM_PER_GPMC_CLKCTRL_MODULEMODE_ENABLE);    HWREG(SOC_PRCM_REGS + CM_PER_ELM_CLKCTRL) |=                             CM_PER_ELM_CLKCTRL_MODULEMODE_ENABLE;    while((HWREG(SOC_PRCM_REGS + CM_PER_ELM_CLKCTRL) &      CM_PER_ELM_CLKCTRL_MODULEMODE) != CM_PER_ELM_CLKCTRL_MODULEMODE_ENABLE);    while(!(HWREG(SOC_PRCM_REGS + CM_PER_L3S_CLKSTCTRL) &            CM_PER_L3S_CLKSTCTRL_CLKACTIVITY_L3S_GCLK));    while(!(HWREG(SOC_PRCM_REGS + CM_PER_L3_CLKSTCTRL) &            CM_PER_L3_CLKSTCTRL_CLKACTIVITY_L3_GCLK));}

//*****************************************************************************//// The interrupt handler for the PG7 pin interrupt.  When triggered, this will// toggle the JTAG pins between JTAG and GPIO mode.////*****************************************************************************voidGPIOGIntHandler(void){    //    // Clear the GPIO interrupt.    //    GPIOPinIntClear(GPIO_PORTG_BASE, GPIO_PIN_7);    //    // Toggle the pin mode.    //    g_ulMode ^= 1;    //    // See if the pins should be in JTAG or GPIO mode.    //    if(g_ulMode == 0)    {        //        // Change PB7 and PC0-3 into hardware (i.e. JTAG) pins.        //        HWREG(GPIO_PORTB_BASE + GPIO_O_LOCK) = GPIO_LOCK_KEY;        HWREG(GPIO_PORTB_BASE + GPIO_O_CR) = 0x80;        HWREG(GPIO_PORTB_BASE + GPIO_O_AFSEL) |= 0x80;        HWREG(GPIO_PORTB_BASE + GPIO_O_LOCK) = GPIO_LOCK_KEY;        HWREG(GPIO_PORTB_BASE + GPIO_O_CR) = 0x00;        HWREG(GPIO_PORTB_BASE + GPIO_O_LOCK) = 0;        HWREG(GPIO_PORTC_BASE + GPIO_O_LOCK) = GPIO_LOCK_KEY;        HWREG(GPIO_PORTC_BASE + GPIO_O_CR) = 0x01;        HWREG(GPIO_PORTC_BASE + GPIO_O_AFSEL) |= 0x01;        HWREG(GPIO_PORTC_BASE + GPIO_O_LOCK) = GPIO_LOCK_KEY;        HWREG(GPIO_PORTC_BASE + GPIO_O_CR) = 0x02;        HWREG(GPIO_PORTC_BASE + GPIO_O_AFSEL) |= 0x02;        HWREG(GPIO_PORTC_BASE + GPIO_O_LOCK) = GPIO_LOCK_KEY;        HWREG(GPIO_PORTC_BASE + GPIO_O_CR) = 0x04;        HWREG(GPIO_PORTC_BASE + GPIO_O_AFSEL) |= 0x04;        HWREG(GPIO_PORTC_BASE + GPIO_O_LOCK) = GPIO_LOCK_KEY;        HWREG(GPIO_PORTC_BASE + GPIO_O_CR) = 0x08;        HWREG(GPIO_PORTC_BASE + GPIO_O_AFSEL) |= 0x08;        HWREG(GPIO_PORTC_BASE + GPIO_O_LOCK) = GPIO_LOCK_KEY;        HWREG(GPIO_PORTC_BASE + GPIO_O_CR) = 0x00;        HWREG(GPIO_PORTC_BASE + GPIO_O_LOCK) = 0;        HWREG(GPIO_PORTB_BASE + GPIO_O_DEN) |= 0x80;        HWREG(GPIO_PORTC_BASE + GPIO_O_DEN) |= 0x0f;    }    else    {        //        // Change PB7 and PC0-3 into GPIO inputs.        //        HWREG(GPIO_PORTB_BASE + GPIO_O_LOCK) = GPIO_LOCK_KEY;        HWREG(GPIO_PORTB_BASE + GPIO_O_CR) = 0x80;        HWREG(GPIO_PORTB_BASE + GPIO_O_AFSEL) &= ~0x7f;        HWREG(GPIO_PORTB_BASE + GPIO_O_LOCK) = GPIO_LOCK_KEY;        HWREG(GPIO_PORTB_BASE + GPIO_O_CR) = 0x00;        HWREG(GPIO_PORTB_BASE + GPIO_O_LOCK) = 0;        HWREG(GPIO_PORTC_BASE + GPIO_O_LOCK) = GPIO_LOCK_KEY;        HWREG(GPIO_PORTC_BASE + GPIO_O_CR) = 0x01;        HWREG(GPIO_PORTC_BASE + GPIO_O_AFSEL) &= ~0xfe;        HWREG(GPIO_PORTC_BASE + GPIO_O_LOCK) = GPIO_LOCK_KEY;        HWREG(GPIO_PORTC_BASE + GPIO_O_CR) = 0x02;        HWREG(GPIO_PORTC_BASE + GPIO_O_AFSEL) &= 0xfd;        HWREG(GPIO_PORTC_BASE + GPIO_O_LOCK) = GPIO_LOCK_KEY;        HWREG(GPIO_PORTC_BASE + GPIO_O_CR) = 0x04;        HWREG(GPIO_PORTC_BASE + GPIO_O_AFSEL) &= 0xfb;        HWREG(GPIO_PORTC_BASE + GPIO_O_LOCK) = GPIO_LOCK_KEY;        HWREG(GPIO_PORTC_BASE + GPIO_O_CR) = 0x08;        HWREG(GPIO_PORTC_BASE + GPIO_O_AFSEL) &= 0xf7;        HWREG(GPIO_PORTC_BASE + GPIO_O_LOCK) = GPIO_LOCK_KEY;        HWREG(GPIO_PORTC_BASE + GPIO_O_CR) = 0x00;        HWREG(GPIO_PORTC_BASE + GPIO_O_LOCK) = 0;        HWREG(GPIO_PORTB_BASE + GPIO_O_DEN) &= ~0x80;        HWREG(GPIO_PORTC_BASE + GPIO_O_DEN) &= ~0x0f;        GPIOPinTypeGPIOInput(GPIO_PORTB_BASE, GPIO_PIN_7);        GPIOPinTypeGPIOInput(GPIO_PORTC_BASE, (GPIO_PIN_0 | GPIO_PIN_1 |                                               GPIO_PIN_2 | GPIO_PIN_3));    }}

unsigned int NANDPinMuxSetup(void){    unsigned int profile = 0;    unsigned int status = FALSE;    profile = EVMProfileGet();     switch (profile)    {        /* All profiles have the same setting. */        case 0:        case 1:        case 4:        case 5:        case 6:        case 7:                /* GPMC_AD0 */                HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(0)) =                ( 0 << CONTROL_CONF_GPMC_AD0_CONF_GPMC_AD0_MMODE_SHIFT) |                ( 0 << CONTROL_CONF_GPMC_AD0_CONF_GPMC_AD0_PUDEN_SHIFT) |                ( 0 << CONTROL_CONF_GPMC_AD0_CONF_GPMC_AD0_PUTYPESEL_SHIFT) |                ( 1 << CONTROL_CONF_GPMC_AD0_CONF_GPMC_AD0_RXACTIVE_SHIFT);                /* GPMC_AD1 */                HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(1)) =                ( 0 << CONTROL_CONF_GPMC_AD1_CONF_GPMC_AD1_MMODE_SHIFT) |                ( 0 << CONTROL_CONF_GPMC_AD1_CONF_GPMC_AD1_PUDEN_SHIFT)|                ( 0 << CONTROL_CONF_GPMC_AD1_CONF_GPMC_AD1_PUTYPESEL_SHIFT) |                ( 1 << CONTROL_CONF_GPMC_AD1_CONF_GPMC_AD1_RXACTIVE_SHIFT) ;                /* GPMC_AD2 */                HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(2)) =                ( 0 << CONTROL_CONF_GPMC_AD2_CONF_GPMC_AD2_MMODE_SHIFT) |                ( 0 << CONTROL_CONF_GPMC_AD2_CONF_GPMC_AD2_PUDEN_SHIFT)|                ( 0 << CONTROL_CONF_GPMC_AD2_CONF_GPMC_AD2_PUTYPESEL_SHIFT) |                ( 1 << CONTROL_CONF_GPMC_AD2_CONF_GPMC_AD2_RXACTIVE_SHIFT) ;                /* GPMC_AD3 */                HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(3)) =                ( 0 << CONTROL_CONF_GPMC_AD3_CONF_GPMC_AD3_MMODE_SHIFT) |                ( 0 << CONTROL_CONF_GPMC_AD3_CONF_GPMC_AD3_PUDEN_SHIFT)|                ( 0 << CONTROL_CONF_GPMC_AD3_CONF_GPMC_AD3_PUTYPESEL_SHIFT) |                ( 1 << CONTROL_CONF_GPMC_AD3_CONF_GPMC_AD3_RXACTIVE_SHIFT) ;                /* GPMC_AD4 */                HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(4)) =                ( 0 << CONTROL_CONF_GPMC_AD4_CONF_GPMC_AD4_MMODE_SHIFT) |                ( 0 << CONTROL_CONF_GPMC_AD4_CONF_GPMC_AD4_PUDEN_SHIFT)|                ( 0 << CONTROL_CONF_GPMC_AD4_CONF_GPMC_AD4_PUTYPESEL_SHIFT) |                ( 1 << CONTROL_CONF_GPMC_AD4_CONF_GPMC_AD4_RXACTIVE_SHIFT) ;                /* GPMC_AD5 */                HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(5)) =                ( 0 << CONTROL_CONF_GPMC_AD5_CONF_GPMC_AD5_MMODE_SHIFT) |                ( 0 << CONTROL_CONF_GPMC_AD5_CONF_GPMC_AD5_PUDEN_SHIFT)|                ( 0 << CONTROL_CONF_GPMC_AD5_CONF_GPMC_AD5_PUTYPESEL_SHIFT) |                ( 1 << CONTROL_CONF_GPMC_AD5_CONF_GPMC_AD5_RXACTIVE_SHIFT) ;                /* GPMC_AD6 */                HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(6)) =                ( 0 << CONTROL_CONF_GPMC_AD6_CONF_GPMC_AD6_MMODE_SHIFT) |                ( 0 << CONTROL_CONF_GPMC_AD6_CONF_GPMC_AD6_PUDEN_SHIFT) |                ( 0 << CONTROL_CONF_GPMC_AD6_CONF_GPMC_AD6_PUTYPESEL_SHIFT) |                ( 1 << CONTROL_CONF_GPMC_AD6_CONF_GPMC_AD6_RXACTIVE_SHIFT) ;                /* GPMC_AD7 */                HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(7)) =                ( 0 << CONTROL_CONF_GPMC_AD7_CONF_GPMC_AD7_MMODE_SHIFT) |                ( 0 << CONTROL_CONF_GPMC_AD7_CONF_GPMC_AD7_PUDEN_SHIFT) |                ( 0 << CONTROL_CONF_GPMC_AD7_CONF_GPMC_AD7_PUTYPESEL_SHIFT) |                ( 1 << CONTROL_CONF_GPMC_AD7_CONF_GPMC_AD7_RXACTIVE_SHIFT) ;                /* GPMC_AD8 */                HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(8)) =                ( 0 << CONTROL_CONF_GPMC_AD8_CONF_GPMC_AD8_MMODE_SHIFT) |                ( 0 << CONTROL_CONF_GPMC_AD8_CONF_GPMC_AD8_PUDEN_SHIFT) |                ( 0 << CONTROL_CONF_GPMC_AD8_CONF_GPMC_AD8_PUTYPESEL_SHIFT) |                ( 1 << CONTROL_CONF_GPMC_AD8_CONF_GPMC_AD8_RXACTIVE_SHIFT) ;                /* GPMC_AD9 */                HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(9)) =                ( 0 << CONTROL_CONF_GPMC_AD9_CONF_GPMC_AD9_MMODE_SHIFT) |                ( 0 << CONTROL_CONF_GPMC_AD9_CONF_GPMC_AD9_PUDEN_SHIFT) |                ( 0 << CONTROL_CONF_GPMC_AD9_CONF_GPMC_AD9_PUTYPESEL_SHIFT) |                ( 1 << CONTROL_CONF_GPMC_AD9_CONF_GPMC_AD9_RXACTIVE_SHIFT) ;                /* GPMC_AD10 */                HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(10)) =                ( 0 << CONTROL_CONF_GPMC_AD10_CONF_GPMC_AD10_MMODE_SHIFT) |                ( 0 << CONTROL_CONF_GPMC_AD10_CONF_GPMC_AD10_PUDEN_SHIFT) |                ( 0 << CONTROL_CONF_GPMC_AD10_CONF_GPMC_AD10_PUTYPESEL_SHIFT) |                ( 1 << CONTROL_CONF_GPMC_AD10_CONF_GPMC_AD10_RXACTIVE_SHIFT) ;                /* GPMC_AD11 */                HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(11)) =                ( 0 << CONTROL_CONF_GPMC_AD11_CONF_GPMC_AD11_MMODE_SHIFT) |                ( 0 << CONTROL_CONF_GPMC_AD11_CONF_GPMC_AD11_PUDEN_SHIFT) |                ( 0 << CONTROL_CONF_GPMC_AD11_CONF_GPMC_AD11_PUTYPESEL_SHIFT) |                ( 1 << CONTROL_CONF_GPMC_AD11_CONF_GPMC_AD11_RXACTIVE_SHIFT) ;                /* GPMC_AD12 */                HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(12)) =                ( 0 << CONTROL_CONF_GPMC_AD12_CONF_GPMC_AD12_MMODE_SHIFT) |                ( 0 << CONTROL_CONF_GPMC_AD12_CONF_GPMC_AD12_PUDEN_SHIFT) |                ( 0 << CONTROL_CONF_GPMC_AD12_CONF_GPMC_AD12_PUTYPESEL_SHIFT) |                ( 1 << CONTROL_CONF_GPMC_AD12_CONF_GPMC_AD12_RXACTIVE_SHIFT) ;                /* GPMC_AD13 */                HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(13)) =                ( 0 << CONTROL_CONF_GPMC_AD13_CONF_GPMC_AD13_MMODE_SHIFT) |                ( 0 << CONTROL_CONF_GPMC_AD13_CONF_GPMC_AD13_PUDEN_SHIFT) |//.........这里部分代码省略.........

/** * /brief   Get the match register contents. * * /param   baseAdd       Base Address of the DMTimer Module Register. * * /return  This API returns the match register contents. * **/unsigned int DMTimerCompareGet(unsigned int baseAdd){    /* Return the TMAR value */    return (HWREG(baseAdd + DMTIMER_TMAR));}

/*** Uart ISR to read the inputs*/static void gpioIsr(void){	/*	Clear wake interrupt	*/	HWREG(SOC_GPIO_0_REGS + 0x2C) = 0x4;	HWREG(SOC_GPIO_0_REGS + 0x30) = 0x4;}

/** * /brief   Read the status of IRQENABLE_SET register. * * /param   baseAdd       Base Address of the DMTimer Module Register. * * /return  This API returns the status of IRQENABLE_SET register. * **/unsigned int DMTimerIntEnableGet(unsigned int baseAdd){    /* Return the status of register IRQENABLE_SET */    return (HWREG(baseAdd + DMTIMER_IRQENABLE_SET));}

//*****************************************************************************////! Start an AES-ECB operation (encryption or decryption).////*****************************************************************************uint32_tCRYPTOAesEcb(uint32_t *pui32MsgIn, uint32_t *pui32MsgOut,             uint32_t ui32KeyLocation, bool bEncrypt,             bool bIntEnable){    //    // Set current operating state of the Crypto module.    //    g_ui32CurrentAesOp = CRYPTO_AES_ECB;    //    // Enable internal interrupts.    //    HWREG(CRYPTO_BASE + CRYPTO_O_IRQTYPE) = CRYPTO_INT_LEVEL;    HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) = CRYPTO_IRQEN_RESULT_AVAIL;    //    // Clear any outstanding interrupts.    //    HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = (CRYPTO_IRQCLR_DMA_IN_DONE |                                            CRYPTO_IRQCLR_RESULT_AVAIL);    //    // If using interrupts clear any pending interrupts and enable interrupts    // for the Crypto module.    //    if(bIntEnable)    {        IntPendClear(INT_CRYPTO);        IntEnable(INT_CRYPTO);    }    //    // Configure Master Control module.    //    HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = CRYPTO_ALGSEL_AES;    //    //    //    HWREG(CRYPTO_BASE + CRYPTO_O_KEYREADAREA) = ui32KeyLocation;    //    //Wait until key is loaded to the AES module.    //    do    {        CPUdelay(1);    }    while((HWREG(CRYPTO_BASE + CRYPTO_O_KEYREADAREA) & CRYPTO_KEYREADAREA_BUSY));    //    // Check for Key store Read error.    //    if((HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT)& CRYPTO_KEY_ST_RD_ERR))    {        return (AES_KEYSTORE_READ_ERROR);    }    //    // Configure AES engine (program AES-ECB-128 encryption and no    // initialization vector - IV).    //    if(bEncrypt)    {        HWREG(CRYPTO_BASE + CRYPTO_O_AESCTL) = CRYPTO_AES128_ENCRYPT;    }    else    {        HWREG(CRYPTO_BASE + CRYPTO_O_AESCTL) = CRYPTO_AES128_DECRYPT;    }    //    // Write the length of the data.    //    HWREG(CRYPTO_BASE + CRYPTO_O_AESDATALEN0) = AES_ECB_LENGTH;    HWREG(CRYPTO_BASE + CRYPTO_O_AESDATALEN1) = 0;    //    // Enable Crypto DMA channel 0.    //    HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0CTL) |= CRYPTO_DMACH0CTL_EN;    //    // Base address of the input data in ext. memory.    //    HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0EXTADDR) = (uint32_t)pui32MsgIn;    //    // Input data length in bytes, equal to the message.    //    HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0LEN) = AES_ECB_LENGTH;    //    // Enable Crypto DMA channel 1.//.........这里部分代码省略.........

//*****************************************************************************//// This is the main example program.  It checks to see that the interrupts are// processed in the correct order when they have identical priorities,// increasing priorities, and decreasing priorities.  This exercises interrupt// preemption and tail chaining.////*****************************************************************************intmain(void){    uint32_t ui32Error;    //    // Enable lazy stacking for interrupt handlers.  This allows floating-point    // instructions to be used within interrupt handlers, but at the expense of    // extra stack usage.    //    ROM_FPULazyStackingEnable();    //    // Set the clocking to run directly from the crystal.    //    ROM_SysCtlClockSet(SYSCTL_SYSDIV_1 | SYSCTL_USE_OSC | SYSCTL_OSC_MAIN |                       SYSCTL_XTAL_16MHZ);    //    // Enable the peripherals used by this example.    //    ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOE);    //    // Initialize the UART.    //    ConfigureUART();    UARTprintf("/033[2JInterrupts/n");    //    // Configure the PB0-PB2 to be outputs to indicate entry/exit of one    // of the interrupt handlers.    //    ROM_GPIOPinTypeGPIOOutput(GPIO_PORTE_BASE, GPIO_PIN_1 | GPIO_PIN_2 |                                               GPIO_PIN_3);    ROM_GPIOPinWrite(GPIO_PORTE_BASE, GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3, 0);    //    // Set up and enable the SysTick timer.  It will be used as a reference    // for delay loops in the interrupt handlers.  The SysTick timer period    // will be set up for one second.    //    ROM_SysTickPeriodSet(ROM_SysCtlClockGet());    ROM_SysTickEnable();    //    // Reset the error indicator.    //    ui32Error = 0;    //    // Enable interrupts to the processor.    //    ROM_IntMasterEnable();    //    // Enable the interrupts.    //    ROM_IntEnable(INT_GPIOA);    ROM_IntEnable(INT_GPIOB);    ROM_IntEnable(INT_GPIOC);    //    // Indicate that the equal interrupt priority test is beginning.    //    UARTprintf("/nEqual Priority/n");    //    // Set the interrupt priorities so they are all equal.    //    ROM_IntPrioritySet(INT_GPIOA, 0x00);    ROM_IntPrioritySet(INT_GPIOB, 0x00);    ROM_IntPrioritySet(INT_GPIOC, 0x00);    //    // Reset the interrupt flags.    //    g_ui32GPIOa = 0;    g_ui32GPIOb = 0;    g_ui32GPIOc = 0;    g_ui32Index = 1;    //    // Trigger the interrupt for GPIO C.    //    HWREG(NVIC_SW_TRIG) = INT_GPIOC - 16;    //    // Put the current interrupt state on the LCD.    //    DisplayIntStatus();//.........这里部分代码省略.........

//*****************************************************************************////! Start CCM operation////*****************************************************************************uint32_tCRYPTOCcmAuthEncrypt(bool bEncrypt, uint32_t ui32AuthLength ,                     uint32_t *pui32Nonce, uint32_t *pui32PlainText,                     uint32_t ui32PlainTextLength, uint32_t *pui32Header,                     uint32_t ui32HeaderLength, uint32_t ui32KeyLocation,                     uint32_t ui32FieldLength, bool bIntEnable){    uint8_t ui8InitVec[16];    uint32_t ui32CtrlVal;    uint32_t i;    uint32_t *pui32CipherText;    //    // Input address for the encryption engine is the same as the output.    //    pui32CipherText = pui32PlainText;    //    // Set current operating state of the Crypto module.    //    g_ui32CurrentAesOp = CRYPTO_AES_CCM;    //    // Disable global interrupt, enable local interrupt and clear any pending    // interrupts.    //    IntDisable(INT_CRYPTO);    HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = (CRYPTO_IRQCLR_DMA_IN_DONE |                                            CRYPTO_IRQCLR_RESULT_AVAIL);    //    // Enable internal interrupts.    //    HWREG(CRYPTO_BASE + CRYPTO_O_IRQTYPE) = CRYPTO_INT_LEVEL;    HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) = CRYPTO_IRQEN_DMA_IN_DONE |                                           CRYPTO_IRQCLR_RESULT_AVAIL;    //    // Configure master control module for AES operation.    //    HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = CRYPTO_ALGSEL_AES;    //    // Enable keys to read (e.g. Key 0).    //    HWREG(CRYPTO_BASE + CRYPTO_O_KEYREADAREA) = ui32KeyLocation;    //    // Wait until key is loaded to the AES module.    //    do    {        CPUdelay(1);    }    while((HWREG(CRYPTO_BASE + CRYPTO_O_KEYREADAREA) & CRYPTO_KEYREADAREA_BUSY));    //    // Check for Key store Read error.    //    if((HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT)& CRYPTO_KEY_ST_RD_ERR))    {        return (AES_KEYSTORE_READ_ERROR);    }    //    // Prepare the initialization vector (IV),    // Length of Nonce l(n) = 15 - ui32FieldLength.    //    ui8InitVec[0] = ui32FieldLength - 1;    for(i = 0; i < 12; i++)    {        ui8InitVec[i + 1] = ((uint8_t*)pui32Nonce)[i];    }    if(ui32FieldLength == 2)    {        ui8InitVec[13] = ((uint8_t*)pui32Nonce)[12];    }    else    {        ui8InitVec[13] = 0;    }    ui8InitVec[14] = 0;    ui8InitVec[15] = 0;    //    // Write initialization vector.    //    HWREG(CRYPTO_BASE + CRYPTO_O_AESIV0) = ((uint32_t  *)&ui8InitVec)[0];    HWREG(CRYPTO_BASE + CRYPTO_O_AESIV1) = ((uint32_t  *)&ui8InitVec)[1];    HWREG(CRYPTO_BASE + CRYPTO_O_AESIV2) = ((uint32_t  *)&ui8InitVec)[2];    HWREG(CRYPTO_BASE + CRYPTO_O_AESIV3) = ((uint32_t  *)&ui8InitVec)[3];    //    // Configure AES engine.    ////.........这里部分代码省略.........

/*!    /brief open spi communication port to be used for communicating with a SimpleLink device	Given an interface name and option flags, this function opens the spi communication port	and creates a file descriptor. This file descriptor can be used afterwards to read and	write data from and to this specific spi channel.	The SPI speed, clock polarity, clock phase, chip select and all other attributes are all	set to hardcoded values in this function.	/param	 		ifName		-	points to the interface name/path. The interface name is an									optional attributes that the simple link driver receives									on opening the device. in systems that the spi channel is									not implemented as part of the os device drivers, this									parameter could be NULL.	/param			flags		-	option flags	/return			upon successful completion, the function shall open the spi channel and return					a non-negative integer representing the file descriptor.					Otherwise, -1 shall be returned    /sa             spi_Close , spi_Read , spi_Write	/note    /warning*/Fd_t spi_Open(char *ifName, unsigned long flags){    unsigned long ulBase;    //NWP master interface    ulBase = LSPI_BASE;    //Enable MCSPIA2    PRCMPeripheralClkEnable(PRCM_LSPI,PRCM_RUN_MODE_CLK|PRCM_SLP_MODE_CLK);    //Disable Chip Select    SPICSDisable(ulBase);    //Disable SPI Channel    SPIDisable(ulBase);    // Reset SPI    SPIReset(ulBase);    //    // Configure SPI interface    //    SPIConfigSetExpClk(ulBase,PRCMPeripheralClockGet(PRCM_LSPI),                       SPI_IF_BIT_RATE,SPI_MODE_MASTER,SPI_SUB_MODE_0,                       (SPI_SW_CTRL_CS |                        SPI_4PIN_MODE |                        SPI_TURBO_OFF |                        SPI_CS_ACTIVEHIGH |                        SPI_WL_32));    if(PRCMPeripheralStatusGet(PRCM_UDMA))    {        g_ucDMAEnabled = (HWREG(UDMA_BASE + UDMA_O_CTLBASE) != 0x0) ? 1 : 0;    }    else    {        g_ucDMAEnabled = 0;    }#ifdef SL_CPU_MODE    g_ucDMAEnabled = 0;#endif    if(g_ucDMAEnabled)    {        memset(g_ucDinDout,0xFF,sizeof(g_ucDinDout));        //g_ucDout[0]=0xFF;        //Simplelink_UDMAInit();        // Set DMA channel        cc_UDMAChannelSelect(UDMA_CH12_LSPI_RX);        cc_UDMAChannelSelect(UDMA_CH13_LSPI_TX);        SPIFIFOEnable(ulBase,SPI_RX_FIFO);        SPIFIFOEnable(ulBase,SPI_TX_FIFO);        SPIDmaEnable(ulBase,SPI_RX_DMA);        SPIDmaEnable(ulBase,SPI_TX_DMA);        SPIFIFOLevelSet(ulBase,1,1);#if defined(SL_PLATFORM_MULTI_THREADED)        osi_InterruptRegister(INT_LSPI, (P_OSI_INTR_ENTRY)DmaSpiSwIntHandler,INT_PRIORITY_LVL_1);        SPIIntEnable(ulBase,SPI_INT_EOW);        osi_MsgQCreate(&DMAMsgQ,"DMAQueue",sizeof(int),1);#else        IntRegister(INT_LSPI,(void(*)(void))DmaSpiSwIntHandler);        IntPrioritySet(INT_LSPI, INT_PRIORITY_LVL_1);        IntEnable(INT_LSPI);        SPIIntEnable(ulBase,SPI_INT_EOW);        g_cDummy = 0x0;#endif    }//.........这里部分代码省略.........

//*****************************************************************************////! Sets the transfer parameters for a uDMA channel.//!//! /param ulChannel is the logical or of the uDMA channel number with either//! /b UDMA_PRI_SELECT or /b UDMA_ALT_SELECT.//! /param ulMode is the type of uDMA transfer.//! /param pvSrcAddr is the source address for the transfer.//! /param pvDstAddr is the destination address for the transfer.//! /param ulTransferSize is the number of data items to transfer.//!//! This function is used to set the parameters for a uDMA transfer.  These are//! typically parameters that are changed often.  The function//! uDMAChannelControlSet() MUST be called at least once for this channel prior//! to calling this function.//!//! The /e ulChannel parameter is one of the choices documented in the//! uDMAChannelEnable() function.  It should be the logical OR of the channel//! with either /b UDMA_PRI_SELECT or /b UDMA_ALT_SELECT to choose whether the//! primary or alternate data structure is used.//!//! The /e ulMode parameter should be one of the following values://!//! - /b UDMA_MODE_STOP stops the uDMA transfer.  The controller sets the mode//!   to this value at the end of a transfer.//! - /b UDMA_MODE_BASIC to perform a basic transfer based on request.//! - /b UDMA_MODE_AUTO to perform a transfer that will always complete once//!   started even if request is removed.//! - /b UDMA_MODE_PINGPONG to set up a transfer that switches between the//!   primary and alternate control structures for the channel.  This allows//!   use of ping-pong buffering for uDMA transfers.//! - /b UDMA_MODE_MEM_SCATTER_GATHER to set up a memory scatter-gather//!   transfer.//! - /b UDMA_MODE_PER_SCATTER_GATHER to set up a peripheral scatter-gather//!   transfer.//!//! The /e pvSrcAddr and /e pvDstAddr parameters are pointers to the first//! location of the data to be transferred.  These addresses should be aligned//! according to the item size.  The compiler will take care of this if the//! pointers are pointing to storage of the appropriate data type.//!//! The /e ulTransferSize parameter is the number of data items, not the number//! of bytes.//!//! The two scatter/gather modes, memory and peripheral, are actually different//! depending on whether the primary or alternate control structure is//! selected.  This function will look for the /b UDMA_PRI_SELECT and//! /b UDMA_ALT_SELECT flag along with the channel number and will set the//! scatter/gather mode as appropriate for the primary or alternate control//! structure.//!//! The channel must also be enabled using uDMAChannelEnable() after calling//! this function.  The transfer will not begin until the channel has been set//! up and enabled.  Note that the channel is automatically disabled after the//! transfer is completed, meaning that uDMAChannelEnable() must be called//! again after setting up the next transfer.//!//! /note Great care must be taken to not modify a channel control structure//! that is in use or else the results will be unpredictable, including the//! possibility of undesired data transfers to or from memory or peripherals.//! For BASIC and AUTO modes, it is safe to make changes when the channel is//! disabled, or the uDMAChannelModeGet() returns /b UDMA_MODE_STOP.  For//! PINGPONG or one of the SCATTER_GATHER modes, it is safe to modify the//! primary or alternate control structure only when the other is being used.//! The uDMAChannelModeGet() function will return /b UDMA_MODE_STOP when a//! channel control structure is inactive and safe to modify.//!//! /return None.////*****************************************************************************voiduDMAChannelTransferSet(unsigned long ulChannel, unsigned long ulMode,                       void *pvSrcAddr, void *pvDstAddr,                       unsigned long ulTransferSize){    tDMAControlTable *pControlTable;    unsigned long ulControl;    unsigned long ulSize;    unsigned long ulInc;    //    // Check the arguments.    //    ASSERT(ulChannel < 64);    ASSERT(HWREG(UDMA_CTLBASE) != 0);    ASSERT(ulMode <= UDMA_MODE_PER_SCATTER_GATHER);    ASSERT((unsigned long)pvSrcAddr >= 0x20000000);    ASSERT((unsigned long)pvDstAddr >= 0x20000000);    ASSERT((ulTransferSize != 0) && (ulTransferSize <= 1024));    //    // Get the base address of the control table.    //    pControlTable = (tDMAControlTable *)HWREG(UDMA_CTLBASE);    //    // Get the current control word value and mask off the mode and size    // fields.    //    ulControl = (pControlTable[ulChannel].ulControl &//.........这里部分代码省略.........