自学教程：C++ IEEE80211_IS_CHAN_2GHZ函数代码示例

voidar9280olcGetTxGainIndex(struct ath_hal *ah,    const struct ieee80211_channel *chan,    struct calDataPerFreqOpLoop *rawDatasetOpLoop,    uint8_t *calChans, uint16_t availPiers, uint8_t *pwr, uint8_t *pcdacIdx){	uint8_t pcdac, i = 0;	uint16_t idxL = 0, idxR = 0, numPiers;	HAL_BOOL match;	CHAN_CENTERS centers;	ar5416GetChannelCenters(ah, chan, &centers);	for (numPiers = 0; numPiers < availPiers; numPiers++)		if (calChans[numPiers] == AR5416_BCHAN_UNUSED)			break;	match = ath_ee_getLowerUpperIndex((uint8_t)FREQ2FBIN(centers.synth_center,		    IEEE80211_IS_CHAN_2GHZ(chan)), calChans, numPiers,		    &idxL, &idxR);	if (match) {		pcdac = rawDatasetOpLoop[idxL].pcdac[0][0];		*pwr = rawDatasetOpLoop[idxL].pwrPdg[0][0];	} else {		pcdac = rawDatasetOpLoop[idxR].pcdac[0][0];		*pwr = (rawDatasetOpLoop[idxL].pwrPdg[0][0] +				rawDatasetOpLoop[idxR].pwrPdg[0][0])/2;	}	while (pcdac > AH9280(ah)->originalGain[i] &&			i < (AR9280_TX_GAIN_TABLE_SIZE - 1))		i++;	*pcdacIdx = i;}

voidar9287olcGetTxGainIndex(struct ath_hal *ah,    const struct ieee80211_channel *chan,    struct cal_data_op_loop_ar9287 *pRawDatasetOpLoop,    uint8_t *pCalChans,  uint16_t availPiers, int8_t *pPwr){        uint16_t idxL = 0, idxR = 0, numPiers;        HAL_BOOL match;        CHAN_CENTERS centers;        ar5416GetChannelCenters(ah, chan, &centers);        for (numPiers = 0; numPiers < availPiers; numPiers++) {                if (pCalChans[numPiers] == AR5416_BCHAN_UNUSED)                        break;        }        match = ath_ee_getLowerUpperIndex(                (uint8_t)FREQ2FBIN(centers.synth_center, IEEE80211_IS_CHAN_2GHZ(chan)),                pCalChans, numPiers, &idxL, &idxR);        if (match) {                *pPwr = (int8_t) pRawDatasetOpLoop[idxL].pwrPdg[0][0];        } else {                *pPwr = ((int8_t) pRawDatasetOpLoop[idxL].pwrPdg[0][0] +                         (int8_t) pRawDatasetOpLoop[idxR].pwrPdg[0][0])/2;        }}

static voidar5416SanitizeNF(struct ath_hal *ah, int16_t *nf){        struct ar5416NfLimits *limit;        int i;        if (IEEE80211_IS_CHAN_2GHZ(AH_PRIVATE(ah)->ah_curchan))                limit = &AH5416(ah)->nf_2g;        else                limit = &AH5416(ah)->nf_5g;        for (i = 0; i < AR5416_NUM_NF_READINGS; i++) {                if (!nf[i])                        continue;                if (nf[i] > limit->max) {                        HALDEBUG(ah, HAL_DEBUG_NFCAL,                                  "NF[%d] (%d) > MAX (%d), correcting to MAX/n",                                  i, nf[i], limit->max);                        nf[i] = limit->max;                } else if (nf[i] < limit->min) {                        HALDEBUG(ah, HAL_DEBUG_NFCAL,                                  "NF[%d] (%d) < MIN (%d), correcting to NOM/n",                                  i, nf[i], limit->min);                        nf[i] = limit->nominal;                }        }}

static uint32_tiwm_mvm_scan_rxon_flags(struct ieee80211_channel *c){	if (IEEE80211_IS_CHAN_2GHZ(c))		return htole32(IWM_PHY_BAND_24);	else		return htole32(IWM_PHY_BAND_5);}

/* * Reads EEPROM header info from device structure and programs * all rf registers * * REQUIRES: Access to the analog rf device */static HAL_BOOLar2133SetRfRegs(struct ath_hal *ah, const struct ieee80211_channel *chan,                uint16_t modesIndex, uint16_t *rfXpdGain){	struct ar2133State *priv = AR2133(ah);	int writes;	HALASSERT(priv);	/* Setup Bank 0 Write */	ath_hal_ini_bank_setup(priv->Bank0Data, &AH5416(ah)->ah_ini_bank0, 1);	/* Setup Bank 1 Write */	ath_hal_ini_bank_setup(priv->Bank1Data, &AH5416(ah)->ah_ini_bank1, 1);	/* Setup Bank 2 Write */	ath_hal_ini_bank_setup(priv->Bank2Data, &AH5416(ah)->ah_ini_bank2, 1);	/* Setup Bank 3 Write */	ath_hal_ini_bank_setup(priv->Bank3Data, &AH5416(ah)->ah_ini_bank3, modesIndex);	/* Setup Bank 6 Write */	ath_hal_ini_bank_setup(priv->Bank6Data, &AH5416(ah)->ah_ini_bank6, modesIndex);		/* Only the 5 or 2 GHz OB/DB need to be set for a mode */	if (IEEE80211_IS_CHAN_2GHZ(chan)) {		ar5416ModifyRfBuffer(priv->Bank6Data,		    ath_hal_eepromGet(ah, AR_EEP_OB_2, AH_NULL), 3, 197, 0);		ar5416ModifyRfBuffer(priv->Bank6Data,		    ath_hal_eepromGet(ah, AR_EEP_DB_2, AH_NULL), 3, 194, 0);	} else {		ar5416ModifyRfBuffer(priv->Bank6Data,		    ath_hal_eepromGet(ah, AR_EEP_OB_5, AH_NULL), 3, 203, 0);		ar5416ModifyRfBuffer(priv->Bank6Data,		    ath_hal_eepromGet(ah, AR_EEP_DB_5, AH_NULL), 3, 200, 0);	}	/* Setup Bank 7 Setup */	ath_hal_ini_bank_setup(priv->Bank7Data, &AH5416(ah)->ah_ini_bank7, 1);	/* Write Analog registers */	writes = ath_hal_ini_bank_write(ah, &AH5416(ah)->ah_ini_bank0,	    priv->Bank0Data, 0);	writes = ath_hal_ini_bank_write(ah, &AH5416(ah)->ah_ini_bank1,	    priv->Bank1Data, writes);	writes = ath_hal_ini_bank_write(ah, &AH5416(ah)->ah_ini_bank2,	    priv->Bank2Data, writes);	writes = ath_hal_ini_bank_write(ah, &AH5416(ah)->ah_ini_bank3,	    priv->Bank3Data, writes);	writes = ath_hal_ini_bank_write(ah, &AH5416(ah)->ah_ini_bank6,	    priv->Bank6Data, writes);	(void) ath_hal_ini_bank_write(ah, &AH5416(ah)->ah_ini_bank7,	    priv->Bank7Data, writes);	return AH_TRUE;#undef  RF_BANK_SETUP}

static intiwm_mvm_scan_skip_channel(struct ieee80211_channel *c){	if (IEEE80211_IS_CHAN_2GHZ(c) && IEEE80211_IS_CHAN_B(c))		return 0;	else if (IEEE80211_IS_CHAN_5GHZ(c) && IEEE80211_IS_CHAN_A(c))		return 0;	else		return 1;}

static uint16_tar5416GetDefaultNF(struct ath_hal *ah, const struct ieee80211_channel *chan){        struct ar5416NfLimits *limit;        if (!chan || IEEE80211_IS_CHAN_2GHZ(chan))                limit = &AH5416(ah)->nf_2g;        else                limit = &AH5416(ah)->nf_5g;        return limit->nominal;}

/* * Add the phy configuration to the PHY context command */static voidiwm_mvm_phy_ctxt_cmd_data(struct iwm_softc *sc,                          struct iwm_phy_context_cmd *cmd, struct ieee80211_channel *chan,                          uint8_t chains_static, uint8_t chains_dynamic){    struct ieee80211com *ic = &sc->sc_ic;    uint8_t active_cnt, idle_cnt;    IWM_DPRINTF(sc, IWM_DEBUG_RESET | IWM_DEBUG_CMD,                "%s: 2ghz=%d, channel=%d, chains static=0x%x, dynamic=0x%x, "                "rx_ant=0x%x, tx_ant=0x%x/n",                __func__,                !! IEEE80211_IS_CHAN_2GHZ(chan),                ieee80211_chan2ieee(ic, chan),                chains_static,                chains_dynamic,                iwm_fw_valid_rx_ant(sc),                iwm_fw_valid_tx_ant(sc));    cmd->ci.band = IEEE80211_IS_CHAN_2GHZ(chan) ?                   IWM_PHY_BAND_24 : IWM_PHY_BAND_5;    cmd->ci.channel = ieee80211_chan2ieee(ic, chan);    cmd->ci.width = IWM_PHY_VHT_CHANNEL_MODE20;    cmd->ci.ctrl_pos = IWM_PHY_VHT_CTRL_POS_1_BELOW;    /* Set rx the chains */    idle_cnt = chains_static;    active_cnt = chains_dynamic;    cmd->rxchain_info = htole32(iwm_fw_valid_rx_ant(sc) <<                                IWM_PHY_RX_CHAIN_VALID_POS);    cmd->rxchain_info |= htole32(idle_cnt << IWM_PHY_RX_CHAIN_CNT_POS);    cmd->rxchain_info |= htole32(active_cnt <<                                 IWM_PHY_RX_CHAIN_MIMO_CNT_POS);    cmd->txchain_info = htole32(iwm_fw_valid_tx_ant(sc));}

voidar9280_reset_tx_gain(struct athn_softc *sc, struct ieee80211_channel *c){	const struct athn_gain *prog = sc->tx_gain;	const uint32_t *pvals;	int i;	if (IEEE80211_IS_CHAN_2GHZ(c))		pvals = prog->vals_2g;	else		pvals = prog->vals_5g;	for (i = 0; i < prog->nregs; i++)		AR_WRITE(sc, prog->regs[i], pvals[i]);}

static voidar9280WriteIni(struct ath_hal *ah, const struct ieee80211_channel *chan){    u_int modesIndex, freqIndex;    int regWrites = 0;    /* Setup the indices for the next set of register array writes */    /* XXX Ignore 11n dynamic mode on the AR5416 for the moment */    if (IEEE80211_IS_CHAN_2GHZ(chan)) {        freqIndex = 2;        if (IEEE80211_IS_CHAN_HT40(chan))            modesIndex = 3;        else if (IEEE80211_IS_CHAN_108G(chan))            modesIndex = 5;        else            modesIndex = 4;    } else {        freqIndex = 1;        if (IEEE80211_IS_CHAN_HT40(chan) ||                IEEE80211_IS_CHAN_TURBO(chan))            modesIndex = 2;        else            modesIndex = 1;    }    /* Set correct Baseband to analog shift setting to access analog chips. */    OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);    OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);    /* XXX Merlin ini fixups */    /* XXX Merlin 100us delay for shift registers */    regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_modes,                                  modesIndex, regWrites);    if (AR_SREV_MERLIN_20_OR_LATER(ah)) {        regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_rxgain,                                      modesIndex, regWrites);        regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_txgain,                                      modesIndex, regWrites);    }    /* XXX Merlin 100us delay for shift registers */    regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common,                                  1, regWrites);    if (AR_SREV_MERLIN_20(ah) && IS_5GHZ_FAST_CLOCK_EN(ah, chan)) {        /* 5GHz channels w/ Fast Clock use different modal values */        regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_xmodes,                                      modesIndex, regWrites);    }}

static HAL_BOOLar5416GetEepromNoiseFloorThresh(struct ath_hal *ah,	const struct ieee80211_channel *chan, int16_t *nft){	if (IEEE80211_IS_CHAN_5GHZ(chan)) {		ath_hal_eepromGet(ah, AR_EEP_NFTHRESH_5, nft);		return AH_TRUE;	}	if (IEEE80211_IS_CHAN_2GHZ(chan)) {		ath_hal_eepromGet(ah, AR_EEP_NFTHRESH_2, nft);		return AH_TRUE;	}	HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x/n",	    __func__, chan->ic_flags);	return AH_FALSE;}

voidar9280_olpc_get_pdadcs(struct athn_softc *sc, struct ieee80211_channel *c,    int chain, uint8_t *boundaries, uint8_t *pdadcs, uint8_t *txgain){	const struct ar5416_eeprom *eep = sc->eep;	const struct ar_cal_data_per_freq_olpc *pierdata;	const uint8_t *pierfreq;	uint8_t fbin, pcdac, pwr, idx;	int i, lo, hi, npiers;	if (IEEE80211_IS_CHAN_2GHZ(c)) {		pierfreq = eep->calFreqPier2G;		pierdata = (const struct ar_cal_data_per_freq_olpc *)		    eep->calPierData2G[chain];		npiers = AR5416_NUM_2G_CAL_PIERS;	} else {		pierfreq = eep->calFreqPier5G;		pierdata = (const struct ar_cal_data_per_freq_olpc *)		    eep->calPierData5G[chain];		npiers = AR5416_NUM_5G_CAL_PIERS;	}	/* Find channel in ROM pier table. */	fbin = athn_chan2fbin(c);	athn_get_pier_ival(fbin, pierfreq, npiers, &lo, &hi);	/* Get average. */	pwr = (pierdata[lo].pwrPdg[0][0] + pierdata[hi].pwrPdg[0][0]) / 2;	pwr /= 2;	/* Convert to dB. */	/* Find power control digital-to-analog converter (PCDAC) value. */	pcdac = pierdata[hi].pcdac[0][0];	for (idx = 0; idx < AR9280_TX_GAIN_TABLE_SIZE - 1; idx++)		if (pcdac <= sc->tx_gain_tbl[idx])			break;	*txgain = idx;	DPRINTFN(3, ("fbin=%d lo=%d hi=%d pwr=%d pcdac=%d txgain=%d/n",	    fbin, lo, hi, pwr, pcdac, idx));	/* Fill phase domain analog-to-digital converter (PDADC) table. */	for (i = 0; i < AR_NUM_PDADC_VALUES; i++)		pdadcs[i] = (i < pwr) ? 0x00 : 0xff;	for (i = 0; i < AR_PD_GAINS_IN_MASK; i++)		boundaries[i] = AR9280_PD_GAIN_BOUNDARY_DEFAULT;}

/* * Determine if calibration is supported by device and channel flags */static OS_INLINE HAL_BOOLar5416IsCalSupp(struct ath_hal *ah, const struct ieee80211_channel *chan,	HAL_CAL_TYPE calType) {	struct ar5416PerCal *cal = &AH5416(ah)->ah_cal;	switch (calType & cal->suppCals) {	case IQ_MISMATCH_CAL:		/* Run IQ Mismatch for non-CCK only */		return !IEEE80211_IS_CHAN_B(chan);	case ADC_GAIN_CAL:	case ADC_DC_CAL:		/* Run ADC Gain Cal for non-CCK & non 2GHz-HT20 only */		return !IEEE80211_IS_CHAN_B(chan) &&		    !(IEEE80211_IS_CHAN_2GHZ(chan) && IEEE80211_IS_CHAN_HT20(chan));	}	return AH_FALSE;}

static uint8_tiwm_mvm_lmac_scan_fill_channels(struct iwm_softc *sc,    struct iwm_scan_channel_cfg_lmac *chan, int n_ssids){	struct ieee80211com *ic = &sc->sc_ic;	struct ieee80211_scan_state *ss = ic->ic_scan;	struct ieee80211_channel *c;	uint8_t nchan;	int j;	for (nchan = j = 0;	    j < ss->ss_last && nchan < sc->ucode_capa.n_scan_channels; j++) {		c = ss->ss_chans[j];		/*		 * Catch other channels, in case we have 900MHz channels or		 * something in the chanlist.		 */		if (!IEEE80211_IS_CHAN_2GHZ(c) && !IEEE80211_IS_CHAN_5GHZ(c)) {			IWM_DPRINTF(sc, IWM_DEBUG_RESET | IWM_DEBUG_EEPROM,			    "%s: skipping channel (freq=%d, ieee=%d, flags=0x%08x)/n",			    __func__, c->ic_freq, c->ic_ieee, c->ic_flags);			continue;		}		IWM_DPRINTF(sc, IWM_DEBUG_RESET | IWM_DEBUG_EEPROM,		    "Adding channel %d (%d Mhz) to the list/n",		    nchan, c->ic_freq);		chan->channel_num = htole16(ieee80211_mhz2ieee(c->ic_freq, 0));		chan->iter_count = htole16(1);		chan->iter_interval = htole32(0);		chan->flags = htole32(IWM_UNIFIED_SCAN_CHANNEL_PARTIAL);		chan->flags |= htole32(IWM_SCAN_CHANNEL_NSSIDS(n_ssids));		/* XXX IEEE80211_SCAN_NOBCAST flag is never set. */		if (!IEEE80211_IS_CHAN_PASSIVE(c) &&		    (!(ss->ss_flags & IEEE80211_SCAN_NOBCAST) || n_ssids != 0))			chan->flags |= htole32(IWM_SCAN_CHANNEL_TYPE_ACTIVE);		chan++;		nchan++;	}	return nchan;}

static intr92c_get_power_group(struct rtwn_softc *sc, struct ieee80211_channel *c){	uint8_t chan;	int group;	chan = rtwn_chan2centieee(c);	if (IEEE80211_IS_CHAN_2GHZ(c)) {		if (chan <= 3)			group = 0;		else if (chan <= 9)		group = 1;		else if (chan <= 14)		group = 2;		else {			KASSERT(0, ("wrong 2GHz channel %d!/n", chan));			return (-1);		}	} else {		KASSERT(0, ("wrong channel band (flags %08X)/n", c->ic_flags));		return (-1);	}	return (group);}

/* * Return the test group for the specific channel based on * the current regulatory setup. */u_intath_hal_getctl(struct ath_hal *ah, const struct ieee80211_channel *c){	u_int ctl;	if (AH_PRIVATE(ah)->ah_rd2GHz == AH_PRIVATE(ah)->ah_rd5GHz ||	    (ah->ah_countryCode == CTRY_DEFAULT && isWwrSKU(ah)))		ctl = SD_NO_CTL;	else if (IEEE80211_IS_CHAN_2GHZ(c))		ctl = AH_PRIVATE(ah)->ah_rd2GHz->conformanceTestLimit;	else		ctl = AH_PRIVATE(ah)->ah_rd5GHz->conformanceTestLimit;	if (IEEE80211_IS_CHAN_B(c))		return ctl | CTL_11B;	if (IEEE80211_IS_CHAN_G(c))		return ctl | CTL_11G;	if (IEEE80211_IS_CHAN_108G(c))		return ctl | CTL_108G;	if (IEEE80211_IS_CHAN_TURBO(c))		return ctl | CTL_TURBO;	if (IEEE80211_IS_CHAN_A(c))		return ctl | CTL_11A;	return ctl;}

static voidiwm_mvm_mac_ctxt_cmd_common(struct iwm_softc *sc, struct iwm_node *in,	struct iwm_mac_ctx_cmd *cmd, uint32_t action){	struct ieee80211com *ic = sc->sc_ic;	struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);	struct ieee80211_node *ni = vap->iv_bss;	int cck_ack_rates, ofdm_ack_rates;	int i;	int is2ghz;	/*	 * id is the MAC address ID - something to do with MAC filtering.	 * color - not sure.	 *	 * These are both functions of the vap, not of the node.	 * So, for now, hard-code both to 0 (default).	 */	cmd->id_and_color = htole32(IWM_FW_CMD_ID_AND_COLOR(IWM_DEFAULT_MACID,	    IWM_DEFAULT_COLOR));	cmd->action = htole32(action);	cmd->mac_type = htole32(IWM_FW_MAC_TYPE_BSS_STA);	/*	 * The TSF ID is one of four TSF tracking resources in the firmware.	 * Read the iwlwifi/mvm code for more details.	 *	 * For now, just hard-code it to TSF tracking ID 0; we only support	 * a single STA mode VAP.	 *	 * It's per-vap, not per-node.	 */	cmd->tsf_id = htole32(IWM_DEFAULT_TSFID);	IEEE80211_ADDR_COPY(cmd->node_addr, sc->sc_bssid);	/*	 * XXX should we error out if in_assoc is 1 and ni == NULL?	 */	if (in->in_assoc) {		IEEE80211_ADDR_COPY(cmd->bssid_addr, ni->ni_bssid);	} else {		/* eth broadcast address */		memset(cmd->bssid_addr, 0xff, sizeof(cmd->bssid_addr));	}	/*	 * Default to 2ghz if no node information is given.	 */	if (in) {		is2ghz = !! IEEE80211_IS_CHAN_2GHZ(in->in_ni.ni_chan);	} else {		is2ghz = 1;	}	iwm_mvm_ack_rates(sc, is2ghz, &cck_ack_rates, &ofdm_ack_rates);	cmd->cck_rates = htole32(cck_ack_rates);	cmd->ofdm_rates = htole32(ofdm_ack_rates);	cmd->cck_short_preamble	    = htole32((ic->ic_flags & IEEE80211_F_SHPREAMBLE)	      ? IWM_MAC_FLG_SHORT_PREAMBLE : 0);	cmd->short_slot	    = htole32((ic->ic_flags & IEEE80211_F_SHSLOT)	      ? IWM_MAC_FLG_SHORT_SLOT : 0);	/* XXX TODO: set wme parameters; also handle getting updated wme parameters */	for (i = 0; i < IWM_AC_NUM+1; i++) {		int txf = i;		cmd->ac[txf].cw_min = htole16(0x0f);		cmd->ac[txf].cw_max = htole16(0x3f);		cmd->ac[txf].aifsn = 1;		cmd->ac[txf].fifos_mask = (1 << txf);		cmd->ac[txf].edca_txop = 0;	}	if (ic->ic_flags & IEEE80211_F_USEPROT)		cmd->protection_flags |= htole32(IWM_MAC_PROT_FLG_TGG_PROTECT);	cmd->filter_flags = htole32(IWM_MAC_FILTER_ACCEPT_GRP);}

Static voidar9287_set_txpower(struct athn_softc *sc, struct ieee80211_channel *c,    struct ieee80211_channel *extc){	const struct ar9287_eeprom *eep = sc->sc_eep;	const struct ar9287_modal_eep_header *modal = &eep->modalHeader;	uint8_t tpow_cck[4], tpow_ofdm[4];#ifndef IEEE80211_NO_HT	uint8_t tpow_cck_ext[4], tpow_ofdm_ext[4];	uint8_t tpow_ht20[8], tpow_ht40[8];	uint8_t ht40inc;#endif	int16_t pwr = 0, max_ant_gain, power[ATHN_POWER_COUNT];	int i;	ar9287_set_power_calib(sc, c);	/* Compute transmit power reduction due to antenna gain. */	max_ant_gain = MAX(modal->antennaGainCh[0], modal->antennaGainCh[1]);	/* XXX */	/*	 * Reduce scaled power by number of active chains to get per-chain	 * transmit power level.	 */	if (sc->sc_ntxchains == 2)		pwr -= AR_PWR_DECREASE_FOR_2_CHAIN;	if (pwr < 0)		pwr = 0;	/* Get CCK target powers. */	ar5008_get_lg_tpow(sc, c, AR_CTL_11B, eep->calTargetPowerCck,	    AR9287_NUM_2G_CCK_TARGET_POWERS, tpow_cck);	/* Get OFDM target powers. */	ar5008_get_lg_tpow(sc, c, AR_CTL_11G, eep->calTargetPower2G,	    AR9287_NUM_2G_20_TARGET_POWERS, tpow_ofdm);#ifndef IEEE80211_NO_HT	/* Get HT-20 target powers. */	ar5008_get_ht_tpow(sc, c, AR_CTL_2GHT20, eep->calTargetPower2GHT20,	    AR9287_NUM_2G_20_TARGET_POWERS, tpow_ht20);	if (extc != NULL) {		/* Get HT-40 target powers. */		ar5008_get_ht_tpow(sc, c, AR_CTL_2GHT40,		    eep->calTargetPower2GHT40, AR9287_NUM_2G_40_TARGET_POWERS,		    tpow_ht40);		/* Get secondary channel CCK target powers. */		ar5008_get_lg_tpow(sc, extc, AR_CTL_11B,		    eep->calTargetPowerCck, AR9287_NUM_2G_CCK_TARGET_POWERS,		    tpow_cck_ext);		/* Get secondary channel OFDM target powers. */		ar5008_get_lg_tpow(sc, extc, AR_CTL_11G,		    eep->calTargetPower2G, AR9287_NUM_2G_20_TARGET_POWERS,		    tpow_ofdm_ext);	}#endif	memset(power, 0, sizeof(power));	/* Shuffle target powers accross transmit rates. */	power[ATHN_POWER_OFDM6   ] =	power[ATHN_POWER_OFDM9   ] =	power[ATHN_POWER_OFDM12  ] =	power[ATHN_POWER_OFDM18  ] =	power[ATHN_POWER_OFDM24  ] = tpow_ofdm[0];	power[ATHN_POWER_OFDM36  ] = tpow_ofdm[1];	power[ATHN_POWER_OFDM48  ] = tpow_ofdm[2];	power[ATHN_POWER_OFDM54  ] = tpow_ofdm[3];	power[ATHN_POWER_XR      ] = tpow_ofdm[0];	power[ATHN_POWER_CCK1_LP ] = tpow_cck[0];	power[ATHN_POWER_CCK2_LP ] =	power[ATHN_POWER_CCK2_SP ] = tpow_cck[1];	power[ATHN_POWER_CCK55_LP] =	power[ATHN_POWER_CCK55_SP] = tpow_cck[2];	power[ATHN_POWER_CCK11_LP] =	power[ATHN_POWER_CCK11_SP] = tpow_cck[3];#ifndef IEEE80211_NO_HT	for (i = 0; i < nitems(tpow_ht20); i++)		power[ATHN_POWER_HT20(i)] = tpow_ht20[i];	if (extc != NULL) {		/* Correct PAR difference between HT40 and HT20/Legacy. */		if (sc->sc_eep_rev >= AR_EEP_MINOR_VER_2)			ht40inc = modal->ht40PowerIncForPdadc;		else			ht40inc = AR_HT40_POWER_INC_FOR_PDADC;		for (i = 0; i < nitems(tpow_ht40); i++)			power[ATHN_POWER_HT40(i)] = tpow_ht40[i] + ht40inc;		power[ATHN_POWER_OFDM_DUP] = tpow_ht40[0];		power[ATHN_POWER_CCK_DUP ] = tpow_ht40[0];		power[ATHN_POWER_OFDM_EXT] = tpow_ofdm_ext[0];		if (IEEE80211_IS_CHAN_2GHZ(c))			power[ATHN_POWER_CCK_EXT] = tpow_cck_ext[0];	}#endif	for (i = 0; i < ATHN_POWER_COUNT; i++) {		power[i] -= AR_PWR_TABLE_OFFSET_DB * 2;	/* In half dB. *///.........这里部分代码省略.........

/* * Restore/reset the ANI parameters and reset the statistics. * This routine must be called for every channel change. * * NOTE: This is where ah_curani is set; other ani code assumes *       it is setup to reflect the current channel. */voidar5416AniReset(struct ath_hal *ah, const struct ieee80211_channel *chan,	HAL_OPMODE opmode, int restore){	struct ath_hal_5212 *ahp = AH5212(ah);	HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan);	/* XXX bounds check ic_devdata */	struct ar5212AniState *aniState = &ahp->ah_ani[chan->ic_devdata];	uint32_t rxfilter;	if ((ichan->privFlags & CHANNEL_ANI_INIT) == 0) {		OS_MEMZERO(aniState, sizeof(*aniState));		if (IEEE80211_IS_CHAN_2GHZ(chan))			aniState->params = &ahp->ah_aniParams24;		else			aniState->params = &ahp->ah_aniParams5;		ichan->privFlags |= CHANNEL_ANI_INIT;		HALASSERT((ichan->privFlags & CHANNEL_ANI_SETUP) == 0);	}	ahp->ah_curani = aniState;#if 0	ath_hal_printf(ah,"%s: chan %u/0x%x restore %d opmode %u%s/n",	    __func__, chan->ic_freq, chan->ic_flags, restore, opmode,	    ichan->privFlags & CHANNEL_ANI_SETUP ? " setup" : "");#else	HALDEBUG(ah, HAL_DEBUG_ANI, "%s: chan %u/0x%x restore %d opmode %u%s/n",	    __func__, chan->ic_freq, chan->ic_flags, restore, opmode,	    ichan->privFlags & CHANNEL_ANI_SETUP ? " setup" : "");#endif	OS_MARK(ah, AH_MARK_ANI_RESET, opmode);	/*	 * Turn off PHY error frame delivery while we futz with settings.	 */	rxfilter = ar5212GetRxFilter(ah);	ar5212SetRxFilter(ah, rxfilter &~ HAL_RX_FILTER_PHYERR);	/*	 * Automatic processing is done only in station mode right now.	 */	if (opmode == HAL_M_STA)		ahp->ah_procPhyErr |= HAL_RSSI_ANI_ENA;	else		ahp->ah_procPhyErr &= ~HAL_RSSI_ANI_ENA;	/*	 * Set all ani parameters.  We either set them to initial	 * values or restore the previous ones for the channel.	 * XXX if ANI follows hardware, we don't care what mode we're	 * XXX in, we should keep the ani parameters	 */	if (restore && (ichan->privFlags & CHANNEL_ANI_SETUP)) {		ar5416AniControl(ah, HAL_ANI_NOISE_IMMUNITY_LEVEL,				 aniState->noiseImmunityLevel);		ar5416AniControl(ah, HAL_ANI_SPUR_IMMUNITY_LEVEL,				 aniState->spurImmunityLevel);		ar5416AniControl(ah, HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,				 !aniState->ofdmWeakSigDetectOff);		ar5416AniControl(ah, HAL_ANI_CCK_WEAK_SIGNAL_THR,				 aniState->cckWeakSigThreshold);		ar5416AniControl(ah, HAL_ANI_FIRSTEP_LEVEL,				 aniState->firstepLevel);	} else {		ar5416AniControl(ah, HAL_ANI_NOISE_IMMUNITY_LEVEL, 0);		ar5416AniControl(ah, HAL_ANI_SPUR_IMMUNITY_LEVEL, 0);		ar5416AniControl(ah, HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,			AH_TRUE);		ar5416AniControl(ah, HAL_ANI_CCK_WEAK_SIGNAL_THR, AH_FALSE);		ar5416AniControl(ah, HAL_ANI_FIRSTEP_LEVEL, 0);		ichan->privFlags |= CHANNEL_ANI_SETUP;	}	ar5416AniRestart(ah, aniState);	/* restore RX filter mask */	ar5212SetRxFilter(ah, rxfilter);}

voidar9280_spur_mitigate(struct athn_softc *sc, struct ieee80211_channel *c,    struct ieee80211_channel *extc){	const struct ar_spur_chan *spurchans;	int spur, bin, spur_delta_phase, spur_freq_sd, spur_subchannel_sd;	int spur_off, range, i;	/* NB: Always clear. */	AR_CLRBITS(sc, AR_PHY_FORCE_CLKEN_CCK, AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);	range = (extc != NULL) ? 19 : 10;	spurchans = sc->ops.get_spur_chans(sc, IEEE80211_IS_CHAN_2GHZ(c));	for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {		spur = spurchans[i].spurChan;		if (spur == AR_NO_SPUR)			return;	/* XXX disable if it was enabled! */		spur /= 10;		if (IEEE80211_IS_CHAN_2GHZ(c))			spur += AR_BASE_FREQ_2GHZ;		else			spur += AR_BASE_FREQ_5GHZ;		spur -= c->ic_freq;		if (abs(spur) < range)			break;	}	if (i == AR_EEPROM_MODAL_SPURS)		return;	/* XXX disable if it was enabled! */	DPRINTFN(2, ("enabling spur mitigation/n"));	AR_SETBITS(sc, AR_PHY_TIMING_CTRL4_0,	    AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |	    AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |	    AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |	    AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);	AR_WRITE(sc, AR_PHY_SPUR_REG,	    AR_PHY_SPUR_REG_MASK_RATE_CNTL |	    AR_PHY_SPUR_REG_ENABLE_MASK_PPM |	    AR_PHY_SPUR_REG_MASK_RATE_SELECT |	    AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |	    SM(AR_PHY_SPUR_REG_SPUR_RSSI_THRESH, AR_SPUR_RSSI_THRESH));#ifndef IEEE80211_NO_HT	if (extc != NULL) {		spur_delta_phase = (spur * 262144) / 10;		if (spur < 0) {			spur_subchannel_sd = 1;			spur_off = spur + 10;		} else {			spur_subchannel_sd = 0;			spur_off = spur - 10;		}	} else#endif	{		spur_delta_phase = (spur * 524288) / 10;		spur_subchannel_sd = 0;		spur_off = spur;	}	if (IEEE80211_IS_CHAN_2GHZ(c))		spur_freq_sd = (spur_off * 2048) / 44;	else		spur_freq_sd = (spur_off * 2048) / 40;	AR_WRITE(sc, AR_PHY_TIMING11,	    AR_PHY_TIMING11_USE_SPUR_IN_AGC |	    SM(AR_PHY_TIMING11_SPUR_FREQ_SD, spur_freq_sd) |	    SM(AR_PHY_TIMING11_SPUR_DELTA_PHASE, spur_delta_phase));	AR_WRITE(sc, AR_PHY_SFCORR_EXT,	    SM(AR_PHY_SFCORR_SPUR_SUBCHNL_SD, spur_subchannel_sd));	AR_WRITE_BARRIER(sc);	bin = spur * 320;	ar5008_set_viterbi_mask(sc, bin);}

//.........这里部分代码省略.........	}	/*	 * Preserve the antenna on a channel change	 */	saveDefAntenna = OS_REG_READ(ah, AR_DEF_ANTENNA);	if (saveDefAntenna == 0)		/* XXX magic constants */		saveDefAntenna = 1;	/* Save hardware flag before chip reset clears the register */	macStaId1 = OS_REG_READ(ah, AR_STA_ID1) & 		(AR_STA_ID1_BASE_RATE_11B | AR_STA_ID1_USE_DEFANT);	/* Save led state from pci config register */	if (!IS_5315(ah))		saveLedState = OS_REG_READ(ah, AR5312_PCICFG) &			(AR_PCICFG_LEDCTL | AR_PCICFG_LEDMODE | AR_PCICFG_LEDBLINK |			 AR_PCICFG_LEDSLOW);	ar5312RestoreClock(ah, opmode);		/* move to refclk operation */	/*	 * Adjust gain parameters before reset if	 * there's an outstanding gain updated.	 */	(void) ar5212GetRfgain(ah);	if (!ar5312ChipReset(ah, chan)) {		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed/n", __func__);		FAIL(HAL_EIO);	}	/* Setup the indices for the next set of register array writes */	if (IEEE80211_IS_CHAN_2GHZ(chan)) {		freqIndex  = 2;		modesIndex = IEEE80211_IS_CHAN_108G(chan) ? 5 :			     IEEE80211_IS_CHAN_G(chan) ? 4 : 3;	} else {		freqIndex  = 1;		modesIndex = IEEE80211_IS_CHAN_ST(chan) ? 2 : 1;	}	OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__);	/* Set correct Baseband to analog shift setting to access analog chips. */	OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);	regWrites = ath_hal_ini_write(ah, &ahp->ah_ini_modes, modesIndex, 0);	regWrites = write_common(ah, &ahp->ah_ini_common, bChannelChange,		regWrites);	ahp->ah_rfHal->writeRegs(ah, modesIndex, freqIndex, regWrites);	OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__);	if (IEEE80211_IS_CHAN_HALF(chan) || IEEE80211_IS_CHAN_QUARTER(chan))		ar5212SetIFSTiming(ah, chan);	/* Overwrite INI values for revised chipsets */	if (AH_PRIVATE(ah)->ah_phyRev >= AR_PHY_CHIP_ID_REV_2) {		/* ADC_CTL */		OS_REG_WRITE(ah, AR_PHY_ADC_CTL,			     SM(2, AR_PHY_ADC_CTL_OFF_INBUFGAIN) |			     SM(2, AR_PHY_ADC_CTL_ON_INBUFGAIN) |			     AR_PHY_ADC_CTL_OFF_PWDDAC |			     AR_PHY_ADC_CTL_OFF_PWDADC);